1 /*
2 * bonito board support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 */
21
22 #include <linux/kernel.h>
23 #include <linux/i2c.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/irq.h>
27 #include <linux/platform_device.h>
28 #include <linux/gpio.h>
29 #include <linux/smsc911x.h>
30 #include <linux/videodev2.h>
31 #include <mach/common.h>
32 #include <asm/mach-types.h>
33 #include <asm/mach/arch.h>
34 #include <asm/mach/map.h>
35 #include <asm/mach/time.h>
36 #include <asm/hardware/cache-l2x0.h>
37 #include <mach/r8a7740.h>
38 #include <video/sh_mobile_lcdc.h>
39
40 /*
41 * CS Address device note
42 *----------------------------------------------------------------
43 * 0 0x0000_0000 NOR Flash (64MB) SW12 : bit3 = OFF
44 * 2 0x0800_0000 ExtNOR (64MB) SW12 : bit3 = OFF
45 * 4 -
46 * 5A -
47 * 5B 0x1600_0000 SRAM (8MB)
48 * 6 0x1800_0000 FPGA (64K)
49 * 0x1801_0000 Ether (4KB)
50 * 0x1801_1000 USB (4KB)
51 */
52
53 /*
54 * SW12
55 *
56 * bit1 bit2 bit3
57 *----------------------------------------------------------------------------
58 * ON NOR WriteProtect NAND WriteProtect CS0 ExtNOR / CS2 NOR
59 * OFF NOR Not WriteProtect NAND Not WriteProtect CS0 NOR / CS2 ExtNOR
60 */
61
62 /*
63 * SCIFA5 (CN42)
64 *
65 * S38.3 = ON
66 * S39.6 = ON
67 * S43.1 = ON
68 */
69
70 /*
71 * LCDC0 (CN3/CN4/CN7)
72 *
73 * S38.1 = OFF
74 * S38.2 = OFF
75 */
76
77 /*
78 * FPGA
79 */
80 #define IRQSR0 0x0020
81 #define IRQSR1 0x0022
82 #define IRQMR0 0x0030
83 #define IRQMR1 0x0032
84 #define BUSSWMR1 0x0070
85 #define BUSSWMR2 0x0072
86 #define BUSSWMR3 0x0074
87 #define BUSSWMR4 0x0076
88
89 #define LCDCR 0x10B4
90 #define DEVRSTCR1 0x10D0
91 #define DEVRSTCR2 0x10D2
92 #define A1MDSR 0x10E0
93 #define BVERR 0x1100
94
95 /* FPGA IRQ */
96 #define FPGA_IRQ_BASE (512)
97 #define FPGA_IRQ0 (FPGA_IRQ_BASE)
98 #define FPGA_IRQ1 (FPGA_IRQ_BASE + 16)
99 #define FPGA_ETH_IRQ (FPGA_IRQ0 + 15)
bonito_fpga_read(u32 offset)100 static u16 bonito_fpga_read(u32 offset)
101 {
102 return __raw_readw(0xf0003000 + offset);
103 }
104
bonito_fpga_write(u32 offset,u16 val)105 static void bonito_fpga_write(u32 offset, u16 val)
106 {
107 __raw_writew(val, 0xf0003000 + offset);
108 }
109
bonito_fpga_irq_disable(struct irq_data * data)110 static void bonito_fpga_irq_disable(struct irq_data *data)
111 {
112 unsigned int irq = data->irq;
113 u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
114 int shift = irq % 16;
115
116 bonito_fpga_write(addr, bonito_fpga_read(addr) | (1 << shift));
117 }
118
bonito_fpga_irq_enable(struct irq_data * data)119 static void bonito_fpga_irq_enable(struct irq_data *data)
120 {
121 unsigned int irq = data->irq;
122 u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
123 int shift = irq % 16;
124
125 bonito_fpga_write(addr, bonito_fpga_read(addr) & ~(1 << shift));
126 }
127
128 static struct irq_chip bonito_fpga_irq_chip __read_mostly = {
129 .name = "bonito FPGA",
130 .irq_mask = bonito_fpga_irq_disable,
131 .irq_unmask = bonito_fpga_irq_enable,
132 };
133
bonito_fpga_irq_demux(unsigned int irq,struct irq_desc * desc)134 static void bonito_fpga_irq_demux(unsigned int irq, struct irq_desc *desc)
135 {
136 u32 val = bonito_fpga_read(IRQSR1) << 16 |
137 bonito_fpga_read(IRQSR0);
138 u32 mask = bonito_fpga_read(IRQMR1) << 16 |
139 bonito_fpga_read(IRQMR0);
140
141 int i;
142
143 val &= ~mask;
144
145 for (i = 0; i < 32; i++) {
146 if (!(val & (1 << i)))
147 continue;
148
149 generic_handle_irq(FPGA_IRQ_BASE + i);
150 }
151 }
152
bonito_fpga_init(void)153 static void bonito_fpga_init(void)
154 {
155 int i;
156
157 bonito_fpga_write(IRQMR0, 0xffff); /* mask all */
158 bonito_fpga_write(IRQMR1, 0xffff); /* mask all */
159
160 /* Device reset */
161 bonito_fpga_write(DEVRSTCR1,
162 (1 << 2)); /* Eth */
163
164 /* FPGA irq require special handling */
165 for (i = FPGA_IRQ_BASE; i < FPGA_IRQ_BASE + 32; i++) {
166 irq_set_chip_and_handler_name(i, &bonito_fpga_irq_chip,
167 handle_level_irq, "level");
168 set_irq_flags(i, IRQF_VALID); /* yuck */
169 }
170
171 irq_set_chained_handler(evt2irq(0x0340), bonito_fpga_irq_demux);
172 irq_set_irq_type(evt2irq(0x0340), IRQ_TYPE_LEVEL_LOW);
173 }
174
175 /*
176 * PMIC settings
177 *
178 * FIXME
179 *
180 * bonito board needs some settings by pmic which use i2c access.
181 * pmic settings use device_initcall() here for use it.
182 */
183 static __u8 *pmic_settings = NULL;
184 static __u8 pmic_do_2A[] = {
185 0x1C, 0x09,
186 0x1A, 0x80,
187 0xff, 0xff,
188 };
189
pmic_init(void)190 static int __init pmic_init(void)
191 {
192 struct i2c_adapter *a = i2c_get_adapter(0);
193 struct i2c_msg msg;
194 __u8 buf[2];
195 int i, ret;
196
197 if (!pmic_settings)
198 return 0;
199 if (!a)
200 return 0;
201
202 msg.addr = 0x46;
203 msg.buf = buf;
204 msg.len = 2;
205 msg.flags = 0;
206
207 for (i = 0; ; i += 2) {
208 buf[0] = pmic_settings[i + 0];
209 buf[1] = pmic_settings[i + 1];
210
211 if ((0xff == buf[0]) && (0xff == buf[1]))
212 break;
213
214 ret = i2c_transfer(a, &msg, 1);
215 if (ret < 0) {
216 pr_err("i2c transfer fail\n");
217 break;
218 }
219 }
220
221 return 0;
222 }
223 device_initcall(pmic_init);
224
225 /*
226 * LCDC0
227 */
228 static const struct fb_videomode lcdc0_mode = {
229 .name = "WVGA Panel",
230 .xres = 800,
231 .yres = 480,
232 .left_margin = 88,
233 .right_margin = 40,
234 .hsync_len = 128,
235 .upper_margin = 20,
236 .lower_margin = 5,
237 .vsync_len = 5,
238 .sync = 0,
239 };
240
241 static struct sh_mobile_lcdc_info lcdc0_info = {
242 .clock_source = LCDC_CLK_BUS,
243 .ch[0] = {
244 .chan = LCDC_CHAN_MAINLCD,
245 .fourcc = V4L2_PIX_FMT_RGB565,
246 .interface_type = RGB24,
247 .clock_divider = 5,
248 .flags = 0,
249 .lcd_cfg = &lcdc0_mode,
250 .num_cfg = 1,
251 .lcd_size_cfg = {
252 .width = 152,
253 .height = 91,
254 },
255 },
256 };
257
258 static struct resource lcdc0_resources[] = {
259 [0] = {
260 .name = "LCDC0",
261 .start = 0xfe940000,
262 .end = 0xfe943fff,
263 .flags = IORESOURCE_MEM,
264 },
265 [1] = {
266 .start = intcs_evt2irq(0x0580),
267 .flags = IORESOURCE_IRQ,
268 },
269 };
270
271 static struct platform_device lcdc0_device = {
272 .name = "sh_mobile_lcdc_fb",
273 .id = 0,
274 .resource = lcdc0_resources,
275 .num_resources = ARRAY_SIZE(lcdc0_resources),
276 .dev = {
277 .platform_data = &lcdc0_info,
278 .coherent_dma_mask = ~0,
279 },
280 };
281
282 /*
283 * SMSC 9221
284 */
285 static struct resource smsc_resources[] = {
286 [0] = {
287 .start = 0x18010000,
288 .end = 0x18011000 - 1,
289 .flags = IORESOURCE_MEM,
290 },
291 [1] = {
292 .start = FPGA_ETH_IRQ,
293 .flags = IORESOURCE_IRQ,
294 },
295 };
296
297 static struct smsc911x_platform_config smsc_platdata = {
298 .flags = SMSC911X_USE_16BIT,
299 .phy_interface = PHY_INTERFACE_MODE_MII,
300 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
301 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
302 };
303
304 static struct platform_device smsc_device = {
305 .name = "smsc911x",
306 .dev = {
307 .platform_data = &smsc_platdata,
308 },
309 .resource = smsc_resources,
310 .num_resources = ARRAY_SIZE(smsc_resources),
311 };
312
313 /*
314 * core board devices
315 */
316 static struct platform_device *bonito_core_devices[] __initdata = {
317 };
318
319 /*
320 * base board devices
321 */
322 static struct platform_device *bonito_base_devices[] __initdata = {
323 &lcdc0_device,
324 &smsc_device,
325 };
326
327 /*
328 * map I/O
329 */
330 static struct map_desc bonito_io_desc[] __initdata = {
331 /*
332 * for CPGA/INTC/PFC
333 * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
334 */
335 {
336 .virtual = 0xe6000000,
337 .pfn = __phys_to_pfn(0xe6000000),
338 .length = 160 << 20,
339 .type = MT_DEVICE_NONSHARED
340 },
341 #ifdef CONFIG_CACHE_L2X0
342 /*
343 * for l2x0_init()
344 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
345 */
346 {
347 .virtual = 0xf0002000,
348 .pfn = __phys_to_pfn(0xf0100000),
349 .length = PAGE_SIZE,
350 .type = MT_DEVICE_NONSHARED
351 },
352 #endif
353 /*
354 * for FPGA (0x1800000-0x19ffffff)
355 * 0x18000000-0x18002000 -> 0xf0003000-0xf0005000
356 */
357 {
358 .virtual = 0xf0003000,
359 .pfn = __phys_to_pfn(0x18000000),
360 .length = PAGE_SIZE * 2,
361 .type = MT_DEVICE_NONSHARED
362 }
363 };
364
bonito_map_io(void)365 static void __init bonito_map_io(void)
366 {
367 iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc));
368
369 /* setup early devices and console here as well */
370 r8a7740_add_early_devices();
371 shmobile_setup_console();
372 }
373
374 /*
375 * board init
376 */
377 #define BIT_ON(sw, bit) (sw & (1 << bit))
378 #define BIT_OFF(sw, bit) (!(sw & (1 << bit)))
379
380 #define VCCQ1CR 0xE6058140
381 #define VCCQ1LCDCR 0xE6058186
382
bonito_init(void)383 static void __init bonito_init(void)
384 {
385 u16 val;
386
387 r8a7740_pinmux_init();
388 bonito_fpga_init();
389
390 pmic_settings = pmic_do_2A;
391
392 /*
393 * core board settings
394 */
395
396 #ifdef CONFIG_CACHE_L2X0
397 /* Early BRESP enable, Shared attribute override enable, 32K*8way */
398 l2x0_init(__io(0xf0002000), 0x40440000, 0x82000fff);
399 #endif
400
401 r8a7740_add_standard_devices();
402
403 platform_add_devices(bonito_core_devices,
404 ARRAY_SIZE(bonito_core_devices));
405
406 /*
407 * base board settings
408 */
409 gpio_request(GPIO_PORT176, NULL);
410 gpio_direction_input(GPIO_PORT176);
411 if (!gpio_get_value(GPIO_PORT176)) {
412 u16 bsw2;
413 u16 bsw3;
414 u16 bsw4;
415
416 /*
417 * FPGA
418 */
419 gpio_request(GPIO_FN_CS5B, NULL);
420 gpio_request(GPIO_FN_CS6A, NULL);
421 gpio_request(GPIO_FN_CS5A_PORT105, NULL);
422 gpio_request(GPIO_FN_IRQ10, NULL);
423
424 val = bonito_fpga_read(BVERR);
425 pr_info("bonito version: cpu %02x, base %02x\n",
426 ((val >> 8) & 0xFF),
427 ((val >> 0) & 0xFF));
428
429 bsw2 = bonito_fpga_read(BUSSWMR2);
430 bsw3 = bonito_fpga_read(BUSSWMR3);
431 bsw4 = bonito_fpga_read(BUSSWMR4);
432
433 /*
434 * SCIFA5 (CN42)
435 */
436 if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */
437 BIT_OFF(bsw3, 9) && /* S39.6 = ON */
438 BIT_OFF(bsw4, 4)) { /* S43.1 = ON */
439 gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL);
440 gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL);
441 }
442
443 /*
444 * LCDC0 (CN3)
445 */
446 if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */
447 BIT_ON(bsw2, 2)) { /* S38.2 = OFF */
448 gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
449 gpio_request(GPIO_FN_LCD0_D0, NULL);
450 gpio_request(GPIO_FN_LCD0_D1, NULL);
451 gpio_request(GPIO_FN_LCD0_D2, NULL);
452 gpio_request(GPIO_FN_LCD0_D3, NULL);
453 gpio_request(GPIO_FN_LCD0_D4, NULL);
454 gpio_request(GPIO_FN_LCD0_D5, NULL);
455 gpio_request(GPIO_FN_LCD0_D6, NULL);
456 gpio_request(GPIO_FN_LCD0_D7, NULL);
457 gpio_request(GPIO_FN_LCD0_D8, NULL);
458 gpio_request(GPIO_FN_LCD0_D9, NULL);
459 gpio_request(GPIO_FN_LCD0_D10, NULL);
460 gpio_request(GPIO_FN_LCD0_D11, NULL);
461 gpio_request(GPIO_FN_LCD0_D12, NULL);
462 gpio_request(GPIO_FN_LCD0_D13, NULL);
463 gpio_request(GPIO_FN_LCD0_D14, NULL);
464 gpio_request(GPIO_FN_LCD0_D15, NULL);
465 gpio_request(GPIO_FN_LCD0_D16, NULL);
466 gpio_request(GPIO_FN_LCD0_D17, NULL);
467 gpio_request(GPIO_FN_LCD0_D18_PORT163, NULL);
468 gpio_request(GPIO_FN_LCD0_D19_PORT162, NULL);
469 gpio_request(GPIO_FN_LCD0_D20_PORT161, NULL);
470 gpio_request(GPIO_FN_LCD0_D21_PORT158, NULL);
471 gpio_request(GPIO_FN_LCD0_D22_PORT160, NULL);
472 gpio_request(GPIO_FN_LCD0_D23_PORT159, NULL);
473 gpio_request(GPIO_FN_LCD0_DCK, NULL);
474 gpio_request(GPIO_FN_LCD0_VSYN, NULL);
475 gpio_request(GPIO_FN_LCD0_HSYN, NULL);
476 gpio_request(GPIO_FN_LCD0_DISP, NULL);
477 gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
478
479 gpio_request(GPIO_PORT61, NULL); /* LCDDON */
480 gpio_direction_output(GPIO_PORT61, 1);
481
482 /* backlight on */
483 bonito_fpga_write(LCDCR, 1);
484
485 /* drivability Max */
486 __raw_writew(0x00FF , VCCQ1LCDCR);
487 __raw_writew(0xFFFF , VCCQ1CR);
488 }
489
490 platform_add_devices(bonito_base_devices,
491 ARRAY_SIZE(bonito_base_devices));
492 }
493 }
494
bonito_timer_init(void)495 static void __init bonito_timer_init(void)
496 {
497 u16 val;
498 u8 md_ck = 0;
499
500 /* read MD_CK value */
501 val = bonito_fpga_read(A1MDSR);
502 if (val & (1 << 10))
503 md_ck |= MD_CK2;
504 if (val & (1 << 9))
505 md_ck |= MD_CK1;
506 if (val & (1 << 8))
507 md_ck |= MD_CK0;
508
509 r8a7740_clock_init(md_ck);
510 shmobile_timer.init();
511 }
512
513 struct sys_timer bonito_timer = {
514 .init = bonito_timer_init,
515 };
516
517 MACHINE_START(BONITO, "bonito")
518 .map_io = bonito_map_io,
519 .init_irq = r8a7740_init_irq,
520 .handle_irq = shmobile_handle_irq_intc,
521 .init_machine = bonito_init,
522 .timer = &bonito_timer,
523 MACHINE_END
524