1 /*
2  * linux/arch/arm/mach-sa1100/time.c
3  *
4  * Copyright (C) 1998 Deborah Wallach.
5  * Twiddles  (C) 1999 Hugo Fiennes <hugo@empeg.com>
6  *
7  * 2000/03/29 (C) Nicolas Pitre <nico@fluxnic.net>
8  *	Rewritten: big cleanup, much simpler, better HZ accuracy.
9  *
10  */
11 #include <linux/init.h>
12 #include <linux/errno.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/timex.h>
16 #include <linux/clockchips.h>
17 
18 #include <asm/mach/time.h>
19 #include <asm/sched_clock.h>
20 #include <mach/hardware.h>
21 
sa1100_read_sched_clock(void)22 static u32 notrace sa1100_read_sched_clock(void)
23 {
24 	return OSCR;
25 }
26 
27 #define MIN_OSCR_DELTA 2
28 
sa1100_ost0_interrupt(int irq,void * dev_id)29 static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id)
30 {
31 	struct clock_event_device *c = dev_id;
32 
33 	/* Disarm the compare/match, signal the event. */
34 	OIER &= ~OIER_E0;
35 	OSSR = OSSR_M0;
36 	c->event_handler(c);
37 
38 	return IRQ_HANDLED;
39 }
40 
41 static int
sa1100_osmr0_set_next_event(unsigned long delta,struct clock_event_device * c)42 sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c)
43 {
44 	unsigned long next, oscr;
45 
46 	OIER |= OIER_E0;
47 	next = OSCR + delta;
48 	OSMR0 = next;
49 	oscr = OSCR;
50 
51 	return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
52 }
53 
54 static void
sa1100_osmr0_set_mode(enum clock_event_mode mode,struct clock_event_device * c)55 sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c)
56 {
57 	switch (mode) {
58 	case CLOCK_EVT_MODE_ONESHOT:
59 	case CLOCK_EVT_MODE_UNUSED:
60 	case CLOCK_EVT_MODE_SHUTDOWN:
61 		OIER &= ~OIER_E0;
62 		OSSR = OSSR_M0;
63 		break;
64 
65 	case CLOCK_EVT_MODE_RESUME:
66 	case CLOCK_EVT_MODE_PERIODIC:
67 		break;
68 	}
69 }
70 
71 static struct clock_event_device ckevt_sa1100_osmr0 = {
72 	.name		= "osmr0",
73 	.features	= CLOCK_EVT_FEAT_ONESHOT,
74 	.rating		= 200,
75 	.set_next_event	= sa1100_osmr0_set_next_event,
76 	.set_mode	= sa1100_osmr0_set_mode,
77 };
78 
79 static struct irqaction sa1100_timer_irq = {
80 	.name		= "ost0",
81 	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
82 	.handler	= sa1100_ost0_interrupt,
83 	.dev_id		= &ckevt_sa1100_osmr0,
84 };
85 
sa1100_timer_init(void)86 static void __init sa1100_timer_init(void)
87 {
88 	OIER = 0;
89 	OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
90 
91 	setup_sched_clock(sa1100_read_sched_clock, 32, 3686400);
92 
93 	clockevents_calc_mult_shift(&ckevt_sa1100_osmr0, 3686400, 4);
94 	ckevt_sa1100_osmr0.max_delta_ns =
95 		clockevent_delta2ns(0x7fffffff, &ckevt_sa1100_osmr0);
96 	ckevt_sa1100_osmr0.min_delta_ns =
97 		clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_sa1100_osmr0) + 1;
98 	ckevt_sa1100_osmr0.cpumask = cpumask_of(0);
99 
100 	setup_irq(IRQ_OST0, &sa1100_timer_irq);
101 
102 	clocksource_mmio_init(&OSCR, "oscr", CLOCK_TICK_RATE, 200, 32,
103 		clocksource_mmio_readl_up);
104 	clockevents_register_device(&ckevt_sa1100_osmr0);
105 }
106 
107 #ifdef CONFIG_PM
108 unsigned long osmr[4], oier;
109 
sa1100_timer_suspend(void)110 static void sa1100_timer_suspend(void)
111 {
112 	osmr[0] = OSMR0;
113 	osmr[1] = OSMR1;
114 	osmr[2] = OSMR2;
115 	osmr[3] = OSMR3;
116 	oier = OIER;
117 }
118 
sa1100_timer_resume(void)119 static void sa1100_timer_resume(void)
120 {
121 	OSSR = 0x0f;
122 	OSMR0 = osmr[0];
123 	OSMR1 = osmr[1];
124 	OSMR2 = osmr[2];
125 	OSMR3 = osmr[3];
126 	OIER = oier;
127 
128 	/*
129 	 * OSMR0 is the system timer: make sure OSCR is sufficiently behind
130 	 */
131 	OSCR = OSMR0 - LATCH;
132 }
133 #else
134 #define sa1100_timer_suspend NULL
135 #define sa1100_timer_resume NULL
136 #endif
137 
138 struct sys_timer sa1100_timer = {
139 	.init		= sa1100_timer_init,
140 	.suspend	= sa1100_timer_suspend,
141 	.resume		= sa1100_timer_resume,
142 };
143