1 #ifndef _INCLUDE_SHANNON_H 2 #define _INCLUDE_SHANNON_H 3 4 /* taken from comp.os.inferno Tue, 12 Sep 2000 09:21:50 GMT, 5 * written by <forsyth@vitanuova.com> */ 6 7 #define SHANNON_GPIO_SPI_FLASH GPIO_GPIO (0) /* Output - Driven low, enables SPI to flash */ 8 #define SHANNON_GPIO_SPI_DSP GPIO_GPIO (1) /* Output - Driven low, enables SPI to DSP */ 9 /* lcd lower = GPIO 2-9 */ 10 #define SHANNON_GPIO_SPI_OUTPUT GPIO_GPIO (10) /* Output - SPI output to DSP */ 11 #define SHANNON_GPIO_SPI_INPUT GPIO_GPIO (11) /* Input - SPI input from DSP */ 12 #define SHANNON_GPIO_SPI_CLOCK GPIO_GPIO (12) /* Output - Clock for SPI */ 13 #define SHANNON_GPIO_SPI_FRAME GPIO_GPIO (13) /* Output - Frame marker - not used */ 14 #define SHANNON_GPIO_SPI_RTS GPIO_GPIO (14) /* Input - SPI Ready to Send */ 15 #define SHANNON_IRQ_GPIO_SPI_RTS IRQ_GPIO14 16 #define SHANNON_GPIO_SPI_CTS GPIO_GPIO (15) /* Output - SPI Clear to Send */ 17 #define SHANNON_GPIO_IRQ_CODEC GPIO_GPIO (16) /* in, irq from ucb1200 */ 18 #define SHANNON_IRQ_GPIO_IRQ_CODEC IRQ_GPIO16 19 #define SHANNON_GPIO_DSP_RESET GPIO_GPIO (17) /* Output - Drive low to reset the DSP */ 20 #define SHANNON_GPIO_CODEC_RESET GPIO_GPIO (18) /* Output - Drive low to reset the UCB1x00 */ 21 #define SHANNON_GPIO_U3_RTS GPIO_GPIO (19) /* ?? */ 22 #define SHANNON_GPIO_U3_CTS GPIO_GPIO (20) /* ?? */ 23 #define SHANNON_GPIO_SENSE_12V GPIO_GPIO (21) /* Input, 12v flash unprotect detected */ 24 #define SHANNON_GPIO_DISP_EN GPIO_GPIO (22) /* out */ 25 /* XXX GPIO 23 unaccounted for */ 26 #define SHANNON_GPIO_EJECT_0 GPIO_GPIO (24) /* in */ 27 #define SHANNON_IRQ_GPIO_EJECT_0 IRQ_GPIO24 28 #define SHANNON_GPIO_EJECT_1 GPIO_GPIO (25) /* in */ 29 #define SHANNON_IRQ_GPIO_EJECT_1 IRQ_GPIO25 30 #define SHANNON_GPIO_RDY_0 GPIO_GPIO (26) /* in */ 31 #define SHANNON_IRQ_GPIO_RDY_0 IRQ_GPIO26 32 #define SHANNON_GPIO_RDY_1 GPIO_GPIO (27) /* in */ 33 #define SHANNON_IRQ_GPIO_RDY_1 IRQ_GPIO27 34 35 /* MCP UCB codec GPIO pins... */ 36 37 #define SHANNON_UCB_GPIO_BACKLIGHT 9 38 #define SHANNON_UCB_GPIO_BRIGHT_MASK 7 39 #define SHANNON_UCB_GPIO_BRIGHT 6 40 #define SHANNON_UCB_GPIO_CONTRAST_MASK 0x3f 41 #define SHANNON_UCB_GPIO_CONTRAST 0 42 43 #endif 44