1 /*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Copyright 2009 Samsung Electronics Co.
6 * Byungho Min <bhmin@samsung.com>
7 *
8 * Common Codes for S5PC100
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/interrupt.h>
18 #include <linux/list.h>
19 #include <linux/timer.h>
20 #include <linux/init.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <linux/device.h>
24 #include <linux/serial_core.h>
25 #include <linux/platform_device.h>
26 #include <linux/sched.h>
27
28 #include <asm/irq.h>
29 #include <asm/proc-fns.h>
30 #include <asm/mach/arch.h>
31 #include <asm/mach/map.h>
32 #include <asm/mach/irq.h>
33
34 #include <mach/map.h>
35 #include <mach/hardware.h>
36 #include <mach/regs-clock.h>
37
38 #include <plat/cpu.h>
39 #include <plat/devs.h>
40 #include <plat/clock.h>
41 #include <plat/sdhci.h>
42 #include <plat/adc-core.h>
43 #include <plat/ata-core.h>
44 #include <plat/fb-core.h>
45 #include <plat/iic-core.h>
46 #include <plat/onenand-core.h>
47 #include <plat/regs-serial.h>
48 #include <plat/watchdog-reset.h>
49
50 #include "common.h"
51
52 static const char name_s5pc100[] = "S5PC100";
53
54 static struct cpu_table cpu_ids[] __initdata = {
55 {
56 .idcode = S5PC100_CPU_ID,
57 .idmask = S5PC100_CPU_MASK,
58 .map_io = s5pc100_map_io,
59 .init_clocks = s5pc100_init_clocks,
60 .init_uarts = s5pc100_init_uarts,
61 .init = s5pc100_init,
62 .name = name_s5pc100,
63 },
64 };
65
66 /* Initial IO mappings */
67
68 static struct map_desc s5pc100_iodesc[] __initdata = {
69 {
70 .virtual = (unsigned long)S5P_VA_CHIPID,
71 .pfn = __phys_to_pfn(S5PC100_PA_CHIPID),
72 .length = SZ_4K,
73 .type = MT_DEVICE,
74 }, {
75 .virtual = (unsigned long)S3C_VA_SYS,
76 .pfn = __phys_to_pfn(S5PC100_PA_SYSCON),
77 .length = SZ_64K,
78 .type = MT_DEVICE,
79 }, {
80 .virtual = (unsigned long)S3C_VA_TIMER,
81 .pfn = __phys_to_pfn(S5PC100_PA_TIMER),
82 .length = SZ_16K,
83 .type = MT_DEVICE,
84 }, {
85 .virtual = (unsigned long)S3C_VA_WATCHDOG,
86 .pfn = __phys_to_pfn(S5PC100_PA_WATCHDOG),
87 .length = SZ_4K,
88 .type = MT_DEVICE,
89 }, {
90 .virtual = (unsigned long)S5P_VA_SROMC,
91 .pfn = __phys_to_pfn(S5PC100_PA_SROMC),
92 .length = SZ_4K,
93 .type = MT_DEVICE,
94 }, {
95 .virtual = (unsigned long)S5P_VA_SYSTIMER,
96 .pfn = __phys_to_pfn(S5PC100_PA_SYSTIMER),
97 .length = SZ_16K,
98 .type = MT_DEVICE,
99 }, {
100 .virtual = (unsigned long)S5P_VA_GPIO,
101 .pfn = __phys_to_pfn(S5PC100_PA_GPIO),
102 .length = SZ_4K,
103 .type = MT_DEVICE,
104 }, {
105 .virtual = (unsigned long)VA_VIC0,
106 .pfn = __phys_to_pfn(S5PC100_PA_VIC0),
107 .length = SZ_16K,
108 .type = MT_DEVICE,
109 }, {
110 .virtual = (unsigned long)VA_VIC1,
111 .pfn = __phys_to_pfn(S5PC100_PA_VIC1),
112 .length = SZ_16K,
113 .type = MT_DEVICE,
114 }, {
115 .virtual = (unsigned long)VA_VIC2,
116 .pfn = __phys_to_pfn(S5PC100_PA_VIC2),
117 .length = SZ_16K,
118 .type = MT_DEVICE,
119 }, {
120 .virtual = (unsigned long)S3C_VA_UART,
121 .pfn = __phys_to_pfn(S3C_PA_UART),
122 .length = SZ_512K,
123 .type = MT_DEVICE,
124 }, {
125 .virtual = (unsigned long)S5PC100_VA_OTHERS,
126 .pfn = __phys_to_pfn(S5PC100_PA_OTHERS),
127 .length = SZ_4K,
128 .type = MT_DEVICE,
129 }
130 };
131
s5pc100_idle(void)132 static void s5pc100_idle(void)
133 {
134 if (!need_resched())
135 cpu_do_idle();
136
137 local_irq_enable();
138 }
139
140 /*
141 * s5pc100_map_io
142 *
143 * register the standard CPU IO areas
144 */
145
s5pc100_init_io(struct map_desc * mach_desc,int size)146 void __init s5pc100_init_io(struct map_desc *mach_desc, int size)
147 {
148 /* initialize the io descriptors we need for initialization */
149 iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc));
150 if (mach_desc)
151 iotable_init(mach_desc, size);
152
153 /* detect cpu id and rev. */
154 s5p_init_cpu(S5P_VA_CHIPID);
155
156 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
157 }
158
s5pc100_map_io(void)159 void __init s5pc100_map_io(void)
160 {
161 /* initialise device information early */
162 s5pc100_default_sdhci0();
163 s5pc100_default_sdhci1();
164 s5pc100_default_sdhci2();
165
166 s3c_adc_setname("s3c64xx-adc");
167
168 /* the i2c devices are directly compatible with s3c2440 */
169 s3c_i2c0_setname("s3c2440-i2c");
170 s3c_i2c1_setname("s3c2440-i2c");
171
172 s3c_onenand_setname("s5pc100-onenand");
173 s3c_fb_setname("s5pc100-fb");
174 s3c_cfcon_setname("s5pc100-pata");
175 }
176
s5pc100_init_clocks(int xtal)177 void __init s5pc100_init_clocks(int xtal)
178 {
179 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
180
181 s3c24xx_register_baseclocks(xtal);
182 s5p_register_clocks(xtal);
183 s5pc100_register_clocks();
184 s5pc100_setup_clocks();
185 }
186
s5pc100_init_irq(void)187 void __init s5pc100_init_irq(void)
188 {
189 u32 vic[] = {~0, ~0, ~0};
190
191 /* VIC0, VIC1, and VIC2 are fully populated. */
192 s5p_init_irq(vic, ARRAY_SIZE(vic));
193 }
194
195 static struct bus_type s5pc100_subsys = {
196 .name = "s5pc100-core",
197 .dev_name = "s5pc100-core",
198 };
199
200 static struct device s5pc100_dev = {
201 .bus = &s5pc100_subsys,
202 };
203
s5pc100_core_init(void)204 static int __init s5pc100_core_init(void)
205 {
206 return subsys_system_register(&s5pc100_subsys, NULL);
207 }
208 core_initcall(s5pc100_core_init);
209
s5pc100_init(void)210 int __init s5pc100_init(void)
211 {
212 printk(KERN_INFO "S5PC100: Initializing architecture\n");
213
214 /* set idle function */
215 pm_idle = s5pc100_idle;
216
217 return device_register(&s5pc100_dev);
218 }
219
220 /* uart registration process */
221
s5pc100_init_uarts(struct s3c2410_uartcfg * cfg,int no)222 void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
223 {
224 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
225 }
226
s5pc100_restart(char mode,const char * cmd)227 void s5pc100_restart(char mode, const char *cmd)
228 {
229 if (mode != 's')
230 arch_wdt_reset();
231
232 soft_restart(0);
233 }
234