1 /* linux/arch/arm/plat-s3c64xx/pm.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX CPU PM support.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/suspend.h>
17 #include <linux/serial_core.h>
18 #include <linux/io.h>
19 #include <linux/gpio.h>
20 #include <linux/pm_domain.h>
21
22 #include <mach/map.h>
23 #include <mach/irqs.h>
24
25 #include <plat/devs.h>
26 #include <plat/pm.h>
27 #include <plat/wakeup-mask.h>
28
29 #include <mach/regs-sys.h>
30 #include <mach/regs-gpio.h>
31 #include <mach/regs-clock.h>
32 #include <mach/regs-syscon-power.h>
33 #include <mach/regs-gpio-memport.h>
34 #include <mach/regs-modem.h>
35
36 struct s3c64xx_pm_domain {
37 char *const name;
38 u32 ena;
39 u32 pwr_stat;
40 struct generic_pm_domain pd;
41 };
42
s3c64xx_pd_off(struct generic_pm_domain * domain)43 static int s3c64xx_pd_off(struct generic_pm_domain *domain)
44 {
45 struct s3c64xx_pm_domain *pd;
46 u32 val;
47
48 pd = container_of(domain, struct s3c64xx_pm_domain, pd);
49
50 val = __raw_readl(S3C64XX_NORMAL_CFG);
51 val &= ~(pd->ena);
52 __raw_writel(val, S3C64XX_NORMAL_CFG);
53
54 return 0;
55 }
56
s3c64xx_pd_on(struct generic_pm_domain * domain)57 static int s3c64xx_pd_on(struct generic_pm_domain *domain)
58 {
59 struct s3c64xx_pm_domain *pd;
60 u32 val;
61 long retry = 1000000L;
62
63 pd = container_of(domain, struct s3c64xx_pm_domain, pd);
64
65 val = __raw_readl(S3C64XX_NORMAL_CFG);
66 val |= pd->ena;
67 __raw_writel(val, S3C64XX_NORMAL_CFG);
68
69 /* Not all domains provide power status readback */
70 if (pd->pwr_stat) {
71 do {
72 cpu_relax();
73 if (__raw_readl(S3C64XX_BLK_PWR_STAT) & pd->pwr_stat)
74 break;
75 } while (retry--);
76
77 if (!retry) {
78 pr_err("Failed to start domain %s\n", pd->name);
79 return -EBUSY;
80 }
81 }
82
83 return 0;
84 }
85
86 static struct s3c64xx_pm_domain s3c64xx_pm_irom = {
87 .name = "IROM",
88 .ena = S3C64XX_NORMALCFG_IROM_ON,
89 .pd = {
90 .power_off = s3c64xx_pd_off,
91 .power_on = s3c64xx_pd_on,
92 },
93 };
94
95 static struct s3c64xx_pm_domain s3c64xx_pm_etm = {
96 .name = "ETM",
97 .ena = S3C64XX_NORMALCFG_DOMAIN_ETM_ON,
98 .pwr_stat = S3C64XX_BLKPWRSTAT_ETM,
99 .pd = {
100 .power_off = s3c64xx_pd_off,
101 .power_on = s3c64xx_pd_on,
102 },
103 };
104
105 static struct s3c64xx_pm_domain s3c64xx_pm_s = {
106 .name = "S",
107 .ena = S3C64XX_NORMALCFG_DOMAIN_S_ON,
108 .pwr_stat = S3C64XX_BLKPWRSTAT_S,
109 .pd = {
110 .power_off = s3c64xx_pd_off,
111 .power_on = s3c64xx_pd_on,
112 },
113 };
114
115 static struct s3c64xx_pm_domain s3c64xx_pm_f = {
116 .name = "F",
117 .ena = S3C64XX_NORMALCFG_DOMAIN_F_ON,
118 .pwr_stat = S3C64XX_BLKPWRSTAT_F,
119 .pd = {
120 .power_off = s3c64xx_pd_off,
121 .power_on = s3c64xx_pd_on,
122 },
123 };
124
125 static struct s3c64xx_pm_domain s3c64xx_pm_p = {
126 .name = "P",
127 .ena = S3C64XX_NORMALCFG_DOMAIN_P_ON,
128 .pwr_stat = S3C64XX_BLKPWRSTAT_P,
129 .pd = {
130 .power_off = s3c64xx_pd_off,
131 .power_on = s3c64xx_pd_on,
132 },
133 };
134
135 static struct s3c64xx_pm_domain s3c64xx_pm_i = {
136 .name = "I",
137 .ena = S3C64XX_NORMALCFG_DOMAIN_I_ON,
138 .pwr_stat = S3C64XX_BLKPWRSTAT_I,
139 .pd = {
140 .power_off = s3c64xx_pd_off,
141 .power_on = s3c64xx_pd_on,
142 },
143 };
144
145 static struct s3c64xx_pm_domain s3c64xx_pm_g = {
146 .name = "G",
147 .ena = S3C64XX_NORMALCFG_DOMAIN_G_ON,
148 .pd = {
149 .power_off = s3c64xx_pd_off,
150 .power_on = s3c64xx_pd_on,
151 },
152 };
153
154 static struct s3c64xx_pm_domain s3c64xx_pm_v = {
155 .name = "V",
156 .ena = S3C64XX_NORMALCFG_DOMAIN_V_ON,
157 .pwr_stat = S3C64XX_BLKPWRSTAT_V,
158 .pd = {
159 .power_off = s3c64xx_pd_off,
160 .power_on = s3c64xx_pd_on,
161 },
162 };
163
164 static struct s3c64xx_pm_domain *s3c64xx_always_on_pm_domains[] = {
165 &s3c64xx_pm_irom,
166 };
167
168 static struct s3c64xx_pm_domain *s3c64xx_pm_domains[] = {
169 &s3c64xx_pm_etm,
170 &s3c64xx_pm_g,
171 &s3c64xx_pm_v,
172 &s3c64xx_pm_i,
173 &s3c64xx_pm_p,
174 &s3c64xx_pm_s,
175 &s3c64xx_pm_f,
176 };
177
178 #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
s3c_pm_debug_smdkled(u32 set,u32 clear)179 void s3c_pm_debug_smdkled(u32 set, u32 clear)
180 {
181 unsigned long flags;
182 int i;
183
184 local_irq_save(flags);
185 for (i = 0; i < 4; i++) {
186 if (clear & (1 << i))
187 gpio_set_value(S3C64XX_GPN(12 + i), 0);
188 if (set & (1 << i))
189 gpio_set_value(S3C64XX_GPN(12 + i), 1);
190 }
191 local_irq_restore(flags);
192 }
193 #endif
194
195 static struct sleep_save core_save[] = {
196 SAVE_ITEM(S3C_APLL_LOCK),
197 SAVE_ITEM(S3C_MPLL_LOCK),
198 SAVE_ITEM(S3C_EPLL_LOCK),
199 SAVE_ITEM(S3C_CLK_SRC),
200 SAVE_ITEM(S3C_CLK_DIV0),
201 SAVE_ITEM(S3C_CLK_DIV1),
202 SAVE_ITEM(S3C_CLK_DIV2),
203 SAVE_ITEM(S3C_CLK_OUT),
204 SAVE_ITEM(S3C_HCLK_GATE),
205 SAVE_ITEM(S3C_PCLK_GATE),
206 SAVE_ITEM(S3C_SCLK_GATE),
207 SAVE_ITEM(S3C_MEM0_GATE),
208
209 SAVE_ITEM(S3C_EPLL_CON1),
210 SAVE_ITEM(S3C_EPLL_CON0),
211
212 SAVE_ITEM(S3C64XX_MEM0DRVCON),
213 SAVE_ITEM(S3C64XX_MEM1DRVCON),
214
215 #ifndef CONFIG_CPU_FREQ
216 SAVE_ITEM(S3C_APLL_CON),
217 SAVE_ITEM(S3C_MPLL_CON),
218 #endif
219 };
220
221 static struct sleep_save misc_save[] = {
222 SAVE_ITEM(S3C64XX_AHB_CON0),
223 SAVE_ITEM(S3C64XX_AHB_CON1),
224 SAVE_ITEM(S3C64XX_AHB_CON2),
225
226 SAVE_ITEM(S3C64XX_SPCON),
227
228 SAVE_ITEM(S3C64XX_MEM0CONSTOP),
229 SAVE_ITEM(S3C64XX_MEM1CONSTOP),
230 SAVE_ITEM(S3C64XX_MEM0CONSLP0),
231 SAVE_ITEM(S3C64XX_MEM0CONSLP1),
232 SAVE_ITEM(S3C64XX_MEM1CONSLP),
233
234 SAVE_ITEM(S3C64XX_SDMA_SEL),
235 SAVE_ITEM(S3C64XX_MODEM_MIFPCON),
236
237 SAVE_ITEM(S3C64XX_NORMAL_CFG),
238 };
239
s3c_pm_configure_extint(void)240 void s3c_pm_configure_extint(void)
241 {
242 __raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK);
243 }
244
s3c_pm_restore_core(void)245 void s3c_pm_restore_core(void)
246 {
247 __raw_writel(0, S3C64XX_EINT_MASK);
248
249 s3c_pm_debug_smdkled(1 << 2, 0);
250
251 s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
252 s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
253 }
254
s3c_pm_save_core(void)255 void s3c_pm_save_core(void)
256 {
257 s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
258 s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
259 }
260
261 /* since both s3c6400 and s3c6410 share the same sleep pm calls, we
262 * put the per-cpu code in here until any new cpu comes along and changes
263 * this.
264 */
265
s3c64xx_cpu_suspend(unsigned long arg)266 static int s3c64xx_cpu_suspend(unsigned long arg)
267 {
268 unsigned long tmp;
269
270 /* set our standby method to sleep */
271
272 tmp = __raw_readl(S3C64XX_PWR_CFG);
273 tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
274 tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP;
275 __raw_writel(tmp, S3C64XX_PWR_CFG);
276
277 /* clear any old wakeup */
278
279 __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT),
280 S3C64XX_WAKEUP_STAT);
281
282 /* set the LED state to 0110 over sleep */
283 s3c_pm_debug_smdkled(3 << 1, 0xf);
284
285 /* issue the standby signal into the pm unit. Note, we
286 * issue a write-buffer drain just in case */
287
288 tmp = 0;
289
290 asm("b 1f\n\t"
291 ".align 5\n\t"
292 "1:\n\t"
293 "mcr p15, 0, %0, c7, c10, 5\n\t"
294 "mcr p15, 0, %0, c7, c10, 4\n\t"
295 "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
296
297 /* we should never get past here */
298
299 panic("sleep resumed to originator?");
300 }
301
302 /* mapping of interrupts to parts of the wakeup mask */
303 static struct samsung_wakeup_mask wake_irqs[] = {
304 { .irq = IRQ_RTC_ALARM, .bit = S3C64XX_PWRCFG_RTC_ALARM_DISABLE, },
305 { .irq = IRQ_RTC_TIC, .bit = S3C64XX_PWRCFG_RTC_TICK_DISABLE, },
306 { .irq = IRQ_PENDN, .bit = S3C64XX_PWRCFG_TS_DISABLE, },
307 { .irq = IRQ_HSMMC0, .bit = S3C64XX_PWRCFG_MMC0_DISABLE, },
308 { .irq = IRQ_HSMMC1, .bit = S3C64XX_PWRCFG_MMC1_DISABLE, },
309 { .irq = IRQ_HSMMC2, .bit = S3C64XX_PWRCFG_MMC2_DISABLE, },
310 { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_BATF_DISABLE},
311 { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE },
312 { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_HSI_DISABLE },
313 { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE },
314 };
315
s3c64xx_pm_prepare(void)316 static void s3c64xx_pm_prepare(void)
317 {
318 samsung_sync_wakemask(S3C64XX_PWR_CFG,
319 wake_irqs, ARRAY_SIZE(wake_irqs));
320
321 /* store address of resume. */
322 __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0);
323
324 /* ensure previous wakeup state is cleared before sleeping */
325 __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
326 }
327
s3c64xx_pm_init(void)328 int __init s3c64xx_pm_init(void)
329 {
330 int i;
331
332 s3c_pm_init();
333
334 for (i = 0; i < ARRAY_SIZE(s3c64xx_always_on_pm_domains); i++)
335 pm_genpd_init(&s3c64xx_always_on_pm_domains[i]->pd,
336 &pm_domain_always_on_gov, false);
337
338 for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); i++)
339 pm_genpd_init(&s3c64xx_pm_domains[i]->pd, NULL, false);
340
341 if (dev_get_platdata(&s3c_device_fb.dev))
342 pm_genpd_add_device(&s3c64xx_pm_f.pd, &s3c_device_fb.dev);
343
344 return 0;
345 }
346
s3c64xx_pm_initcall(void)347 static __init int s3c64xx_pm_initcall(void)
348 {
349 pm_cpu_prep = s3c64xx_pm_prepare;
350 pm_cpu_sleep = s3c64xx_cpu_suspend;
351 pm_uart_udivslot = 1;
352
353 #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
354 gpio_request(S3C64XX_GPN(12), "DEBUG_LED0");
355 gpio_request(S3C64XX_GPN(13), "DEBUG_LED1");
356 gpio_request(S3C64XX_GPN(14), "DEBUG_LED2");
357 gpio_request(S3C64XX_GPN(15), "DEBUG_LED3");
358 gpio_direction_output(S3C64XX_GPN(12), 0);
359 gpio_direction_output(S3C64XX_GPN(13), 0);
360 gpio_direction_output(S3C64XX_GPN(14), 0);
361 gpio_direction_output(S3C64XX_GPN(15), 0);
362 #endif
363
364 return 0;
365 }
366 arch_initcall(s3c64xx_pm_initcall);
367
s3c64xx_pm_late_initcall(void)368 static __init int s3c64xx_pm_late_initcall(void)
369 {
370 pm_genpd_poweroff_unused();
371
372 return 0;
373 }
374 late_initcall(s3c64xx_pm_late_initcall);
375