1 /* linux/arch/arm/mach-s3c2442/s3c2442.c
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2442 core and lock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24 #include <linux/init.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/list.h>
28 #include <linux/errno.h>
29 #include <linux/err.h>
30 #include <linux/device.h>
31 #include <linux/syscore_ops.h>
32 #include <linux/interrupt.h>
33 #include <linux/ioport.h>
34 #include <linux/mutex.h>
35 #include <linux/gpio.h>
36 #include <linux/clk.h>
37 #include <linux/io.h>
38
39 #include <mach/hardware.h>
40 #include <linux/atomic.h>
41 #include <asm/irq.h>
42
43 #include <mach/regs-clock.h>
44
45 #include <plat/clock.h>
46 #include <plat/cpu.h>
47 #include <plat/s3c244x.h>
48 #include <plat/pm.h>
49
50 #include <plat/gpio-core.h>
51 #include <plat/gpio-cfg.h>
52 #include <plat/gpio-cfg-helpers.h>
53
54 /* S3C2442 extended clock support */
55
s3c2442_camif_upll_round(struct clk * clk,unsigned long rate)56 static unsigned long s3c2442_camif_upll_round(struct clk *clk,
57 unsigned long rate)
58 {
59 unsigned long parent_rate = clk_get_rate(clk->parent);
60 int div;
61
62 if (rate > parent_rate)
63 return parent_rate;
64
65 div = parent_rate / rate;
66
67 if (div == 3)
68 return parent_rate / 3;
69
70 /* note, we remove the +/- 1 calculations for the divisor */
71
72 div /= 2;
73
74 if (div < 1)
75 div = 1;
76 else if (div > 16)
77 div = 16;
78
79 return parent_rate / (div * 2);
80 }
81
s3c2442_camif_upll_setrate(struct clk * clk,unsigned long rate)82 static int s3c2442_camif_upll_setrate(struct clk *clk, unsigned long rate)
83 {
84 unsigned long parent_rate = clk_get_rate(clk->parent);
85 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
86
87 rate = s3c2442_camif_upll_round(clk, rate);
88
89 camdivn &= ~S3C2442_CAMDIVN_CAMCLK_DIV3;
90
91 if (rate == parent_rate) {
92 camdivn &= ~S3C2440_CAMDIVN_CAMCLK_SEL;
93 } else if ((parent_rate / rate) == 3) {
94 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
95 camdivn |= S3C2442_CAMDIVN_CAMCLK_DIV3;
96 } else {
97 camdivn &= ~S3C2440_CAMDIVN_CAMCLK_MASK;
98 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
99 camdivn |= (((parent_rate / rate) / 2) - 1);
100 }
101
102 __raw_writel(camdivn, S3C2440_CAMDIVN);
103
104 return 0;
105 }
106
107 /* Extra S3C2442 clocks */
108
109 static struct clk s3c2442_clk_cam = {
110 .name = "camif",
111 .id = -1,
112 .enable = s3c2410_clkcon_enable,
113 .ctrlbit = S3C2440_CLKCON_CAMERA,
114 };
115
116 static struct clk s3c2442_clk_cam_upll = {
117 .name = "camif-upll",
118 .id = -1,
119 .ops = &(struct clk_ops) {
120 .set_rate = s3c2442_camif_upll_setrate,
121 .round_rate = s3c2442_camif_upll_round,
122 },
123 };
124
s3c2442_clk_add(struct device * dev,struct subsys_interface * sif)125 static int s3c2442_clk_add(struct device *dev, struct subsys_interface *sif)
126 {
127 struct clk *clock_upll;
128 struct clk *clock_h;
129 struct clk *clock_p;
130
131 clock_p = clk_get(NULL, "pclk");
132 clock_h = clk_get(NULL, "hclk");
133 clock_upll = clk_get(NULL, "upll");
134
135 if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
136 printk(KERN_ERR "S3C2442: Failed to get parent clocks\n");
137 return -EINVAL;
138 }
139
140 s3c2442_clk_cam.parent = clock_h;
141 s3c2442_clk_cam_upll.parent = clock_upll;
142
143 s3c24xx_register_clock(&s3c2442_clk_cam);
144 s3c24xx_register_clock(&s3c2442_clk_cam_upll);
145
146 clk_disable(&s3c2442_clk_cam);
147
148 return 0;
149 }
150
151 static struct subsys_interface s3c2442_clk_interface = {
152 .name = "s3c2442_clk",
153 .subsys = &s3c2442_subsys,
154 .add_dev = s3c2442_clk_add,
155 };
156
s3c2442_clk_init(void)157 static __init int s3c2442_clk_init(void)
158 {
159 return subsys_interface_register(&s3c2442_clk_interface);
160 }
161
162 arch_initcall(s3c2442_clk_init);
163
164
165 static struct device s3c2442_dev = {
166 .bus = &s3c2442_subsys,
167 };
168
s3c2442_init(void)169 int __init s3c2442_init(void)
170 {
171 printk("S3C2442: Initialising architecture\n");
172
173 #ifdef CONFIG_PM
174 register_syscore_ops(&s3c2410_pm_syscore_ops);
175 #endif
176 register_syscore_ops(&s3c244x_pm_syscore_ops);
177 register_syscore_ops(&s3c24xx_irq_syscore_ops);
178
179 return device_register(&s3c2442_dev);
180 }
181
s3c2442_map_io(void)182 void __init s3c2442_map_io(void)
183 {
184 s3c244x_map_io();
185
186 s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1down;
187 s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1down;
188 }
189