1 /* linux/arch/arm/mach-s3c2440/mach-at2440evb.c
2 *
3 * Copyright (c) 2008 Ramax Lo <ramaxlo@gmail.com>
4 * Based on mach-anubis.c by Ben Dooks <ben@simtec.co.uk>
5 * and modifications by SBZ <sbz@spgui.org> and
6 * Weibing <http://weibing.blogbus.com>
7 *
8 * For product information, visit http://www.arm.com/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/interrupt.h>
18 #include <linux/list.h>
19 #include <linux/timer.h>
20 #include <linux/init.h>
21 #include <linux/io.h>
22 #include <linux/serial_core.h>
23 #include <linux/dm9000.h>
24 #include <linux/platform_device.h>
25
26 #include <asm/mach/arch.h>
27 #include <asm/mach/map.h>
28 #include <asm/mach/irq.h>
29
30 #include <mach/hardware.h>
31 #include <mach/fb.h>
32 #include <asm/irq.h>
33 #include <asm/mach-types.h>
34
35 #include <plat/regs-serial.h>
36 #include <mach/regs-gpio.h>
37 #include <mach/regs-mem.h>
38 #include <mach/regs-lcd.h>
39 #include <plat/nand.h>
40 #include <plat/iic.h>
41
42 #include <linux/mtd/mtd.h>
43 #include <linux/mtd/nand.h>
44 #include <linux/mtd/nand_ecc.h>
45 #include <linux/mtd/partitions.h>
46
47 #include <plat/clock.h>
48 #include <plat/devs.h>
49 #include <plat/cpu.h>
50 #include <plat/mci.h>
51
52 #include "common.h"
53
54 static struct map_desc at2440evb_iodesc[] __initdata = {
55 /* Nothing here */
56 };
57
58 #define UCON S3C2410_UCON_DEFAULT
59 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
60 #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
61
62 static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
63 [0] = {
64 .hwport = 0,
65 .flags = 0,
66 .ucon = UCON,
67 .ulcon = ULCON,
68 .ufcon = UFCON,
69 .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
70 },
71 [1] = {
72 .hwport = 1,
73 .flags = 0,
74 .ucon = UCON,
75 .ulcon = ULCON,
76 .ufcon = UFCON,
77 .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
78 },
79 };
80
81 /* NAND Flash on AT2440EVB board */
82
83 static struct mtd_partition __initdata at2440evb_default_nand_part[] = {
84 [0] = {
85 .name = "Boot Agent",
86 .size = SZ_256K,
87 .offset = 0,
88 },
89 [1] = {
90 .name = "Kernel",
91 .size = SZ_2M,
92 .offset = SZ_256K,
93 },
94 [2] = {
95 .name = "Root",
96 .offset = SZ_256K + SZ_2M,
97 .size = MTDPART_SIZ_FULL,
98 },
99 };
100
101 static struct s3c2410_nand_set __initdata at2440evb_nand_sets[] = {
102 [0] = {
103 .name = "nand",
104 .nr_chips = 1,
105 .nr_partitions = ARRAY_SIZE(at2440evb_default_nand_part),
106 .partitions = at2440evb_default_nand_part,
107 },
108 };
109
110 static struct s3c2410_platform_nand __initdata at2440evb_nand_info = {
111 .tacls = 25,
112 .twrph0 = 55,
113 .twrph1 = 40,
114 .nr_sets = ARRAY_SIZE(at2440evb_nand_sets),
115 .sets = at2440evb_nand_sets,
116 };
117
118 /* DM9000AEP 10/100 ethernet controller */
119
120 static struct resource at2440evb_dm9k_resource[] = {
121 [0] = {
122 .start = S3C2410_CS3,
123 .end = S3C2410_CS3 + 3,
124 .flags = IORESOURCE_MEM
125 },
126 [1] = {
127 .start = S3C2410_CS3 + 4,
128 .end = S3C2410_CS3 + 7,
129 .flags = IORESOURCE_MEM
130 },
131 [2] = {
132 .start = IRQ_EINT7,
133 .end = IRQ_EINT7,
134 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
135 }
136 };
137
138 static struct dm9000_plat_data at2440evb_dm9k_pdata = {
139 .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
140 };
141
142 static struct platform_device at2440evb_device_eth = {
143 .name = "dm9000",
144 .id = -1,
145 .num_resources = ARRAY_SIZE(at2440evb_dm9k_resource),
146 .resource = at2440evb_dm9k_resource,
147 .dev = {
148 .platform_data = &at2440evb_dm9k_pdata,
149 },
150 };
151
152 static struct s3c24xx_mci_pdata at2440evb_mci_pdata __initdata = {
153 .gpio_detect = S3C2410_GPG(10),
154 };
155
156 /* 7" LCD panel */
157
158 static struct s3c2410fb_display at2440evb_lcd_cfg __initdata = {
159
160 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
161 S3C2410_LCDCON5_INVVLINE |
162 S3C2410_LCDCON5_INVVFRAME |
163 S3C2410_LCDCON5_PWREN |
164 S3C2410_LCDCON5_HWSWP,
165
166 .type = S3C2410_LCDCON1_TFT,
167
168 .width = 800,
169 .height = 480,
170
171 .pixclock = 33333, /* HCLK 60 MHz, divisor 2 */
172 .xres = 800,
173 .yres = 480,
174 .bpp = 16,
175 .left_margin = 88,
176 .right_margin = 40,
177 .hsync_len = 128,
178 .upper_margin = 32,
179 .lower_margin = 11,
180 .vsync_len = 2,
181 };
182
183 static struct s3c2410fb_mach_info at2440evb_fb_info __initdata = {
184 .displays = &at2440evb_lcd_cfg,
185 .num_displays = 1,
186 .default_display = 0,
187 };
188
189 static struct platform_device *at2440evb_devices[] __initdata = {
190 &s3c_device_ohci,
191 &s3c_device_wdt,
192 &s3c_device_adc,
193 &s3c_device_i2c0,
194 &s3c_device_rtc,
195 &s3c_device_nand,
196 &s3c_device_sdi,
197 &s3c_device_lcd,
198 &at2440evb_device_eth,
199 };
200
at2440evb_map_io(void)201 static void __init at2440evb_map_io(void)
202 {
203 s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
204 s3c24xx_init_clocks(16934400);
205 s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs));
206 }
207
at2440evb_init(void)208 static void __init at2440evb_init(void)
209 {
210 s3c24xx_fb_set_platdata(&at2440evb_fb_info);
211 s3c24xx_mci_set_platdata(&at2440evb_mci_pdata);
212 s3c_nand_set_platdata(&at2440evb_nand_info);
213 s3c_i2c0_set_platdata(NULL);
214
215 platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices));
216 }
217
218
219 MACHINE_START(AT2440EVB, "AT2440EVB")
220 .atag_offset = 0x100,
221 .map_io = at2440evb_map_io,
222 .init_machine = at2440evb_init,
223 .init_irq = s3c24xx_init_irq,
224 .timer = &s3c24xx_timer,
225 .restart = s3c244x_restart,
226 MACHINE_END
227