1 /* linux/arch/arm/mach-s3c2440/mach-anubis.c
2 *
3 * Copyright 2003-2009 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/interrupt.h>
15 #include <linux/list.h>
16 #include <linux/timer.h>
17 #include <linux/init.h>
18 #include <linux/gpio.h>
19 #include <linux/serial_core.h>
20 #include <linux/platform_device.h>
21 #include <linux/ata_platform.h>
22 #include <linux/i2c.h>
23 #include <linux/io.h>
24 #include <linux/sm501.h>
25 #include <linux/sm501-regs.h>
26
27 #include <asm/mach/arch.h>
28 #include <asm/mach/map.h>
29 #include <asm/mach/irq.h>
30
31 #include <mach/anubis-map.h>
32 #include <mach/anubis-irq.h>
33 #include <mach/anubis-cpld.h>
34
35 #include <mach/hardware.h>
36 #include <asm/irq.h>
37 #include <asm/mach-types.h>
38
39 #include <plat/regs-serial.h>
40 #include <mach/regs-gpio.h>
41 #include <mach/regs-mem.h>
42 #include <mach/regs-lcd.h>
43 #include <plat/nand.h>
44 #include <plat/iic.h>
45
46 #include <linux/mtd/mtd.h>
47 #include <linux/mtd/nand.h>
48 #include <linux/mtd/nand_ecc.h>
49 #include <linux/mtd/partitions.h>
50
51 #include <net/ax88796.h>
52
53 #include <plat/clock.h>
54 #include <plat/devs.h>
55 #include <plat/cpu.h>
56 #include <plat/audio-simtec.h>
57
58 #include "common.h"
59
60 #define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"
61
62 static struct map_desc anubis_iodesc[] __initdata = {
63 /* ISA IO areas */
64
65 {
66 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
67 .pfn = __phys_to_pfn(0x0),
68 .length = SZ_4M,
69 .type = MT_DEVICE,
70 }, {
71 .virtual = (u32)S3C24XX_VA_ISA_WORD,
72 .pfn = __phys_to_pfn(0x0),
73 .length = SZ_4M,
74 .type = MT_DEVICE,
75 },
76
77 /* we could possibly compress the next set down into a set of smaller tables
78 * pagetables, but that would mean using an L2 section, and it still means
79 * we cannot actually feed the same register to an LDR due to 16K spacing
80 */
81
82 /* CPLD control registers */
83
84 {
85 .virtual = (u32)ANUBIS_VA_CTRL1,
86 .pfn = __phys_to_pfn(ANUBIS_PA_CTRL1),
87 .length = SZ_4K,
88 .type = MT_DEVICE,
89 }, {
90 .virtual = (u32)ANUBIS_VA_IDREG,
91 .pfn = __phys_to_pfn(ANUBIS_PA_IDREG),
92 .length = SZ_4K,
93 .type = MT_DEVICE,
94 },
95 };
96
97 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
98 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
99 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
100
101 static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
102 [0] = {
103 .hwport = 0,
104 .flags = 0,
105 .ucon = UCON,
106 .ulcon = ULCON,
107 .ufcon = UFCON,
108 .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
109 },
110 [1] = {
111 .hwport = 2,
112 .flags = 0,
113 .ucon = UCON,
114 .ulcon = ULCON,
115 .ufcon = UFCON,
116 .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
117 },
118 };
119
120 /* NAND Flash on Anubis board */
121
122 static int external_map[] = { 2 };
123 static int chip0_map[] = { 0 };
124 static int chip1_map[] = { 1 };
125
126 static struct mtd_partition __initdata anubis_default_nand_part[] = {
127 [0] = {
128 .name = "Boot Agent",
129 .size = SZ_16K,
130 .offset = 0,
131 },
132 [1] = {
133 .name = "/boot",
134 .size = SZ_4M - SZ_16K,
135 .offset = SZ_16K,
136 },
137 [2] = {
138 .name = "user1",
139 .offset = SZ_4M,
140 .size = SZ_32M - SZ_4M,
141 },
142 [3] = {
143 .name = "user2",
144 .offset = SZ_32M,
145 .size = MTDPART_SIZ_FULL,
146 }
147 };
148
149 static struct mtd_partition __initdata anubis_default_nand_part_large[] = {
150 [0] = {
151 .name = "Boot Agent",
152 .size = SZ_128K,
153 .offset = 0,
154 },
155 [1] = {
156 .name = "/boot",
157 .size = SZ_4M - SZ_128K,
158 .offset = SZ_128K,
159 },
160 [2] = {
161 .name = "user1",
162 .offset = SZ_4M,
163 .size = SZ_32M - SZ_4M,
164 },
165 [3] = {
166 .name = "user2",
167 .offset = SZ_32M,
168 .size = MTDPART_SIZ_FULL,
169 }
170 };
171
172 /* the Anubis has 3 selectable slots for nand-flash, the two
173 * on-board chip areas, as well as the external slot.
174 *
175 * Note, there is no current hot-plug support for the External
176 * socket.
177 */
178
179 static struct s3c2410_nand_set __initdata anubis_nand_sets[] = {
180 [1] = {
181 .name = "External",
182 .nr_chips = 1,
183 .nr_map = external_map,
184 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
185 .partitions = anubis_default_nand_part,
186 },
187 [0] = {
188 .name = "chip0",
189 .nr_chips = 1,
190 .nr_map = chip0_map,
191 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
192 .partitions = anubis_default_nand_part,
193 },
194 [2] = {
195 .name = "chip1",
196 .nr_chips = 1,
197 .nr_map = chip1_map,
198 .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
199 .partitions = anubis_default_nand_part,
200 },
201 };
202
anubis_nand_select(struct s3c2410_nand_set * set,int slot)203 static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
204 {
205 unsigned int tmp;
206
207 slot = set->nr_map[slot] & 3;
208
209 pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
210 slot, set, set->nr_map);
211
212 tmp = __raw_readb(ANUBIS_VA_CTRL1);
213 tmp &= ~ANUBIS_CTRL1_NANDSEL;
214 tmp |= slot;
215
216 pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
217
218 __raw_writeb(tmp, ANUBIS_VA_CTRL1);
219 }
220
221 static struct s3c2410_platform_nand __initdata anubis_nand_info = {
222 .tacls = 25,
223 .twrph0 = 55,
224 .twrph1 = 40,
225 .nr_sets = ARRAY_SIZE(anubis_nand_sets),
226 .sets = anubis_nand_sets,
227 .select_chip = anubis_nand_select,
228 };
229
230 /* IDE channels */
231
232 static struct pata_platform_info anubis_ide_platdata = {
233 .ioport_shift = 5,
234 };
235
236 static struct resource anubis_ide0_resource[] = {
237 {
238 .start = S3C2410_CS3,
239 .end = S3C2410_CS3 + (8*32) - 1,
240 .flags = IORESOURCE_MEM,
241 }, {
242 .start = S3C2410_CS3 + (1<<26) + (6*32),
243 .end = S3C2410_CS3 + (1<<26) + (7*32) - 1,
244 .flags = IORESOURCE_MEM,
245 }, {
246 .start = IRQ_IDE0,
247 .end = IRQ_IDE0,
248 .flags = IORESOURCE_IRQ,
249 },
250 };
251
252 static struct platform_device anubis_device_ide0 = {
253 .name = "pata_platform",
254 .id = 0,
255 .num_resources = ARRAY_SIZE(anubis_ide0_resource),
256 .resource = anubis_ide0_resource,
257 .dev = {
258 .platform_data = &anubis_ide_platdata,
259 .coherent_dma_mask = ~0,
260 },
261 };
262
263 static struct resource anubis_ide1_resource[] = {
264 {
265 .start = S3C2410_CS4,
266 .end = S3C2410_CS4 + (8*32) - 1,
267 .flags = IORESOURCE_MEM,
268 }, {
269 .start = S3C2410_CS4 + (1<<26) + (6*32),
270 .end = S3C2410_CS4 + (1<<26) + (7*32) - 1,
271 .flags = IORESOURCE_MEM,
272 }, {
273 .start = IRQ_IDE0,
274 .end = IRQ_IDE0,
275 .flags = IORESOURCE_IRQ,
276 },
277 };
278
279 static struct platform_device anubis_device_ide1 = {
280 .name = "pata_platform",
281 .id = 1,
282 .num_resources = ARRAY_SIZE(anubis_ide1_resource),
283 .resource = anubis_ide1_resource,
284 .dev = {
285 .platform_data = &anubis_ide_platdata,
286 .coherent_dma_mask = ~0,
287 },
288 };
289
290 /* Asix AX88796 10/100 ethernet controller */
291
292 static struct ax_plat_data anubis_asix_platdata = {
293 .flags = AXFLG_MAC_FROMDEV,
294 .wordlength = 2,
295 .dcr_val = 0x48,
296 .rcr_val = 0x40,
297 };
298
299 static struct resource anubis_asix_resource[] = {
300 [0] = {
301 .start = S3C2410_CS5,
302 .end = S3C2410_CS5 + (0x20 * 0x20) -1,
303 .flags = IORESOURCE_MEM
304 },
305 [1] = {
306 .start = IRQ_ASIX,
307 .end = IRQ_ASIX,
308 .flags = IORESOURCE_IRQ
309 }
310 };
311
312 static struct platform_device anubis_device_asix = {
313 .name = "ax88796",
314 .id = 0,
315 .num_resources = ARRAY_SIZE(anubis_asix_resource),
316 .resource = anubis_asix_resource,
317 .dev = {
318 .platform_data = &anubis_asix_platdata,
319 }
320 };
321
322 /* SM501 */
323
324 static struct resource anubis_sm501_resource[] = {
325 [0] = {
326 .start = S3C2410_CS2,
327 .end = S3C2410_CS2 + SZ_8M,
328 .flags = IORESOURCE_MEM,
329 },
330 [1] = {
331 .start = S3C2410_CS2 + SZ_64M - SZ_2M,
332 .end = S3C2410_CS2 + SZ_64M - 1,
333 .flags = IORESOURCE_MEM,
334 },
335 [2] = {
336 .start = IRQ_EINT0,
337 .end = IRQ_EINT0,
338 .flags = IORESOURCE_IRQ,
339 },
340 };
341
342 static struct sm501_initdata anubis_sm501_initdata = {
343 .gpio_high = {
344 .set = 0x3F000000, /* 24bit panel */
345 .mask = 0x0,
346 },
347 .misc_timing = {
348 .set = 0x010100, /* SDRAM timing */
349 .mask = 0x1F1F00,
350 },
351 .misc_control = {
352 .set = SM501_MISC_PNL_24BIT,
353 .mask = 0,
354 },
355
356 .devices = SM501_USE_GPIO,
357
358 /* set the SDRAM and bus clocks */
359 .mclk = 72 * MHZ,
360 .m1xclk = 144 * MHZ,
361 };
362
363 static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
364 [0] = {
365 .bus_num = 1,
366 .pin_scl = 44,
367 .pin_sda = 45,
368 },
369 [1] = {
370 .bus_num = 2,
371 .pin_scl = 40,
372 .pin_sda = 41,
373 },
374 };
375
376 static struct sm501_platdata anubis_sm501_platdata = {
377 .init = &anubis_sm501_initdata,
378 .gpio_base = -1,
379 .gpio_i2c = anubis_sm501_gpio_i2c,
380 .gpio_i2c_nr = ARRAY_SIZE(anubis_sm501_gpio_i2c),
381 };
382
383 static struct platform_device anubis_device_sm501 = {
384 .name = "sm501",
385 .id = 0,
386 .num_resources = ARRAY_SIZE(anubis_sm501_resource),
387 .resource = anubis_sm501_resource,
388 .dev = {
389 .platform_data = &anubis_sm501_platdata,
390 },
391 };
392
393 /* Standard Anubis devices */
394
395 static struct platform_device *anubis_devices[] __initdata = {
396 &s3c_device_ohci,
397 &s3c_device_wdt,
398 &s3c_device_adc,
399 &s3c_device_i2c0,
400 &s3c_device_rtc,
401 &s3c_device_nand,
402 &anubis_device_ide0,
403 &anubis_device_ide1,
404 &anubis_device_asix,
405 &anubis_device_sm501,
406 };
407
408 static struct clk *anubis_clocks[] __initdata = {
409 &s3c24xx_dclk0,
410 &s3c24xx_dclk1,
411 &s3c24xx_clkout0,
412 &s3c24xx_clkout1,
413 &s3c24xx_uclk,
414 };
415
416 /* I2C devices. */
417
418 static struct i2c_board_info anubis_i2c_devs[] __initdata = {
419 {
420 I2C_BOARD_INFO("tps65011", 0x48),
421 .irq = IRQ_EINT20,
422 }
423 };
424
425 /* Audio setup */
426 static struct s3c24xx_audio_simtec_pdata __initdata anubis_audio = {
427 .have_mic = 1,
428 .have_lout = 1,
429 .output_cdclk = 1,
430 .use_mpllin = 1,
431 .amp_gpio = S3C2410_GPB(2),
432 .amp_gain[0] = S3C2410_GPD(10),
433 .amp_gain[1] = S3C2410_GPD(11),
434 };
435
anubis_map_io(void)436 static void __init anubis_map_io(void)
437 {
438 /* initialise the clocks */
439
440 s3c24xx_dclk0.parent = &clk_upll;
441 s3c24xx_dclk0.rate = 12*1000*1000;
442
443 s3c24xx_dclk1.parent = &clk_upll;
444 s3c24xx_dclk1.rate = 24*1000*1000;
445
446 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
447 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
448
449 s3c24xx_uclk.parent = &s3c24xx_clkout1;
450
451 s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));
452
453 s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
454 s3c24xx_init_clocks(0);
455 s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
456
457 /* check for the newer revision boards with large page nand */
458
459 if ((__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK) >= 4) {
460 printk(KERN_INFO "ANUBIS-B detected (revision %d)\n",
461 __raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK);
462 anubis_nand_sets[0].partitions = anubis_default_nand_part_large;
463 anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
464 } else {
465 /* ensure that the GPIO is setup */
466 s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
467 }
468 }
469
anubis_init(void)470 static void __init anubis_init(void)
471 {
472 s3c_i2c0_set_platdata(NULL);
473 s3c_nand_set_platdata(&anubis_nand_info);
474 simtec_audio_add(NULL, false, &anubis_audio);
475
476 platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
477
478 i2c_register_board_info(0, anubis_i2c_devs,
479 ARRAY_SIZE(anubis_i2c_devs));
480 }
481
482
483 MACHINE_START(ANUBIS, "Simtec-Anubis")
484 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
485 .atag_offset = 0x100,
486 .map_io = anubis_map_io,
487 .init_machine = anubis_init,
488 .init_irq = s3c24xx_init_irq,
489 .timer = &s3c24xx_timer,
490 .restart = s3c244x_restart,
491 MACHINE_END
492