1 /* linux/arch/arm/mach-s3c2410/mach-bast.c
2 *
3 * Copyright 2003-2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.simtec.co.uk/products/EB2410ITX/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 #include <linux/timer.h>
18 #include <linux/init.h>
19 #include <linux/gpio.h>
20 #include <linux/syscore_ops.h>
21 #include <linux/serial_core.h>
22 #include <linux/platform_device.h>
23 #include <linux/dm9000.h>
24 #include <linux/ata_platform.h>
25 #include <linux/i2c.h>
26 #include <linux/io.h>
27
28 #include <net/ax88796.h>
29
30 #include <asm/mach/arch.h>
31 #include <asm/mach/map.h>
32 #include <asm/mach/irq.h>
33
34 #include <mach/bast-map.h>
35 #include <mach/bast-irq.h>
36 #include <mach/bast-cpld.h>
37
38 #include <mach/hardware.h>
39 #include <asm/irq.h>
40 #include <asm/mach-types.h>
41
42 //#include <asm/debug-ll.h>
43 #include <plat/regs-serial.h>
44 #include <mach/regs-gpio.h>
45 #include <mach/regs-mem.h>
46 #include <mach/regs-lcd.h>
47
48 #include <plat/hwmon.h>
49 #include <plat/nand.h>
50 #include <plat/iic.h>
51 #include <mach/fb.h>
52
53 #include <linux/mtd/mtd.h>
54 #include <linux/mtd/nand.h>
55 #include <linux/mtd/nand_ecc.h>
56 #include <linux/mtd/partitions.h>
57
58 #include <linux/serial_8250.h>
59
60 #include <plat/clock.h>
61 #include <plat/devs.h>
62 #include <plat/cpu.h>
63 #include <plat/cpu-freq.h>
64 #include <plat/gpio-cfg.h>
65 #include <plat/audio-simtec.h>
66
67 #include "usb-simtec.h"
68 #include "nor-simtec.h"
69 #include "common.h"
70
71 #define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
72
73 /* macros for virtual address mods for the io space entries */
74 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
75 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
76 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
77 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
78
79 /* macros to modify the physical addresses for io space */
80
81 #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
82 #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
83 #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
84 #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
85
86 static struct map_desc bast_iodesc[] __initdata = {
87 /* ISA IO areas */
88 {
89 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
90 .pfn = PA_CS2(BAST_PA_ISAIO),
91 .length = SZ_16M,
92 .type = MT_DEVICE,
93 }, {
94 .virtual = (u32)S3C24XX_VA_ISA_WORD,
95 .pfn = PA_CS3(BAST_PA_ISAIO),
96 .length = SZ_16M,
97 .type = MT_DEVICE,
98 },
99 /* bast CPLD control registers, and external interrupt controls */
100 {
101 .virtual = (u32)BAST_VA_CTRL1,
102 .pfn = __phys_to_pfn(BAST_PA_CTRL1),
103 .length = SZ_1M,
104 .type = MT_DEVICE,
105 }, {
106 .virtual = (u32)BAST_VA_CTRL2,
107 .pfn = __phys_to_pfn(BAST_PA_CTRL2),
108 .length = SZ_1M,
109 .type = MT_DEVICE,
110 }, {
111 .virtual = (u32)BAST_VA_CTRL3,
112 .pfn = __phys_to_pfn(BAST_PA_CTRL3),
113 .length = SZ_1M,
114 .type = MT_DEVICE,
115 }, {
116 .virtual = (u32)BAST_VA_CTRL4,
117 .pfn = __phys_to_pfn(BAST_PA_CTRL4),
118 .length = SZ_1M,
119 .type = MT_DEVICE,
120 },
121 /* PC104 IRQ mux */
122 {
123 .virtual = (u32)BAST_VA_PC104_IRQREQ,
124 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
125 .length = SZ_1M,
126 .type = MT_DEVICE,
127 }, {
128 .virtual = (u32)BAST_VA_PC104_IRQRAW,
129 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
130 .length = SZ_1M,
131 .type = MT_DEVICE,
132 }, {
133 .virtual = (u32)BAST_VA_PC104_IRQMASK,
134 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
135 .length = SZ_1M,
136 .type = MT_DEVICE,
137 },
138
139 /* peripheral space... one for each of fast/slow/byte/16bit */
140 /* note, ide is only decoded in word space, even though some registers
141 * are only 8bit */
142
143 /* slow, byte */
144 { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
145 { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
146 { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
147
148 /* slow, word */
149 { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
150 { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
151 { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
152
153 /* fast, byte */
154 { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
155 { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
156 { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
157
158 /* fast, word */
159 { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
160 { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
161 { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
162 };
163
164 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
165 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
166 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
167
168 static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
169 [0] = {
170 .hwport = 0,
171 .flags = 0,
172 .ucon = UCON,
173 .ulcon = ULCON,
174 .ufcon = UFCON,
175 },
176 [1] = {
177 .hwport = 1,
178 .flags = 0,
179 .ucon = UCON,
180 .ulcon = ULCON,
181 .ufcon = UFCON,
182 },
183 /* port 2 is not actually used */
184 [2] = {
185 .hwport = 2,
186 .flags = 0,
187 .ucon = UCON,
188 .ulcon = ULCON,
189 .ufcon = UFCON,
190 }
191 };
192
193 /* NAND Flash on BAST board */
194
195 #ifdef CONFIG_PM
bast_pm_suspend(void)196 static int bast_pm_suspend(void)
197 {
198 /* ensure that an nRESET is not generated on resume. */
199 gpio_direction_output(S3C2410_GPA(21), 1);
200 return 0;
201 }
202
bast_pm_resume(void)203 static void bast_pm_resume(void)
204 {
205 s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
206 }
207
208 #else
209 #define bast_pm_suspend NULL
210 #define bast_pm_resume NULL
211 #endif
212
213 static struct syscore_ops bast_pm_syscore_ops = {
214 .suspend = bast_pm_suspend,
215 .resume = bast_pm_resume,
216 };
217
218 static int smartmedia_map[] = { 0 };
219 static int chip0_map[] = { 1 };
220 static int chip1_map[] = { 2 };
221 static int chip2_map[] = { 3 };
222
223 static struct mtd_partition __initdata bast_default_nand_part[] = {
224 [0] = {
225 .name = "Boot Agent",
226 .size = SZ_16K,
227 .offset = 0,
228 },
229 [1] = {
230 .name = "/boot",
231 .size = SZ_4M - SZ_16K,
232 .offset = SZ_16K,
233 },
234 [2] = {
235 .name = "user",
236 .offset = SZ_4M,
237 .size = MTDPART_SIZ_FULL,
238 }
239 };
240
241 /* the bast has 4 selectable slots for nand-flash, the three
242 * on-board chip areas, as well as the external SmartMedia
243 * slot.
244 *
245 * Note, there is no current hot-plug support for the SmartMedia
246 * socket.
247 */
248
249 static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
250 [0] = {
251 .name = "SmartMedia",
252 .nr_chips = 1,
253 .nr_map = smartmedia_map,
254 .options = NAND_SCAN_SILENT_NODEV,
255 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
256 .partitions = bast_default_nand_part,
257 },
258 [1] = {
259 .name = "chip0",
260 .nr_chips = 1,
261 .nr_map = chip0_map,
262 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
263 .partitions = bast_default_nand_part,
264 },
265 [2] = {
266 .name = "chip1",
267 .nr_chips = 1,
268 .nr_map = chip1_map,
269 .options = NAND_SCAN_SILENT_NODEV,
270 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
271 .partitions = bast_default_nand_part,
272 },
273 [3] = {
274 .name = "chip2",
275 .nr_chips = 1,
276 .nr_map = chip2_map,
277 .options = NAND_SCAN_SILENT_NODEV,
278 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
279 .partitions = bast_default_nand_part,
280 }
281 };
282
bast_nand_select(struct s3c2410_nand_set * set,int slot)283 static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
284 {
285 unsigned int tmp;
286
287 slot = set->nr_map[slot] & 3;
288
289 pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
290 slot, set, set->nr_map);
291
292 tmp = __raw_readb(BAST_VA_CTRL2);
293 tmp &= BAST_CPLD_CTLR2_IDERST;
294 tmp |= slot;
295 tmp |= BAST_CPLD_CTRL2_WNAND;
296
297 pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
298
299 __raw_writeb(tmp, BAST_VA_CTRL2);
300 }
301
302 static struct s3c2410_platform_nand __initdata bast_nand_info = {
303 .tacls = 30,
304 .twrph0 = 60,
305 .twrph1 = 60,
306 .nr_sets = ARRAY_SIZE(bast_nand_sets),
307 .sets = bast_nand_sets,
308 .select_chip = bast_nand_select,
309 };
310
311 /* DM9000 */
312
313 static struct resource bast_dm9k_resource[] = {
314 [0] = {
315 .start = S3C2410_CS5 + BAST_PA_DM9000,
316 .end = S3C2410_CS5 + BAST_PA_DM9000 + 3,
317 .flags = IORESOURCE_MEM,
318 },
319 [1] = {
320 .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
321 .end = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
322 .flags = IORESOURCE_MEM,
323 },
324 [2] = {
325 .start = IRQ_DM9000,
326 .end = IRQ_DM9000,
327 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
328 }
329
330 };
331
332 /* for the moment we limit ourselves to 16bit IO until some
333 * better IO routines can be written and tested
334 */
335
336 static struct dm9000_plat_data bast_dm9k_platdata = {
337 .flags = DM9000_PLATF_16BITONLY,
338 };
339
340 static struct platform_device bast_device_dm9k = {
341 .name = "dm9000",
342 .id = 0,
343 .num_resources = ARRAY_SIZE(bast_dm9k_resource),
344 .resource = bast_dm9k_resource,
345 .dev = {
346 .platform_data = &bast_dm9k_platdata,
347 }
348 };
349
350 /* serial devices */
351
352 #define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
353 #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
354 #define SERIAL_CLK (1843200)
355
356 static struct plat_serial8250_port bast_sio_data[] = {
357 [0] = {
358 .mapbase = SERIAL_BASE + 0x2f8,
359 .irq = IRQ_PCSERIAL1,
360 .flags = SERIAL_FLAGS,
361 .iotype = UPIO_MEM,
362 .regshift = 0,
363 .uartclk = SERIAL_CLK,
364 },
365 [1] = {
366 .mapbase = SERIAL_BASE + 0x3f8,
367 .irq = IRQ_PCSERIAL2,
368 .flags = SERIAL_FLAGS,
369 .iotype = UPIO_MEM,
370 .regshift = 0,
371 .uartclk = SERIAL_CLK,
372 },
373 { }
374 };
375
376 static struct platform_device bast_sio = {
377 .name = "serial8250",
378 .id = PLAT8250_DEV_PLATFORM,
379 .dev = {
380 .platform_data = &bast_sio_data,
381 },
382 };
383
384 /* we have devices on the bus which cannot work much over the
385 * standard 100KHz i2c bus frequency
386 */
387
388 static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
389 .flags = 0,
390 .slave_addr = 0x10,
391 .frequency = 100*1000,
392 };
393
394 /* Asix AX88796 10/100 ethernet controller */
395
396 static struct ax_plat_data bast_asix_platdata = {
397 .flags = AXFLG_MAC_FROMDEV,
398 .wordlength = 2,
399 .dcr_val = 0x48,
400 .rcr_val = 0x40,
401 };
402
403 static struct resource bast_asix_resource[] = {
404 [0] = {
405 .start = S3C2410_CS5 + BAST_PA_ASIXNET,
406 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
407 .flags = IORESOURCE_MEM,
408 },
409 [1] = {
410 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
411 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
412 .flags = IORESOURCE_MEM,
413 },
414 [2] = {
415 .start = IRQ_ASIX,
416 .end = IRQ_ASIX,
417 .flags = IORESOURCE_IRQ
418 }
419 };
420
421 static struct platform_device bast_device_asix = {
422 .name = "ax88796",
423 .id = 0,
424 .num_resources = ARRAY_SIZE(bast_asix_resource),
425 .resource = bast_asix_resource,
426 .dev = {
427 .platform_data = &bast_asix_platdata
428 }
429 };
430
431 /* Asix AX88796 10/100 ethernet controller parallel port */
432
433 static struct resource bast_asixpp_resource[] = {
434 [0] = {
435 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
436 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
437 .flags = IORESOURCE_MEM,
438 }
439 };
440
441 static struct platform_device bast_device_axpp = {
442 .name = "ax88796-pp",
443 .id = 0,
444 .num_resources = ARRAY_SIZE(bast_asixpp_resource),
445 .resource = bast_asixpp_resource,
446 };
447
448 /* LCD/VGA controller */
449
450 static struct s3c2410fb_display __initdata bast_lcd_info[] = {
451 {
452 .type = S3C2410_LCDCON1_TFT,
453 .width = 640,
454 .height = 480,
455
456 .pixclock = 33333,
457 .xres = 640,
458 .yres = 480,
459 .bpp = 4,
460 .left_margin = 40,
461 .right_margin = 20,
462 .hsync_len = 88,
463 .upper_margin = 30,
464 .lower_margin = 32,
465 .vsync_len = 3,
466
467 .lcdcon5 = 0x00014b02,
468 },
469 {
470 .type = S3C2410_LCDCON1_TFT,
471 .width = 640,
472 .height = 480,
473
474 .pixclock = 33333,
475 .xres = 640,
476 .yres = 480,
477 .bpp = 8,
478 .left_margin = 40,
479 .right_margin = 20,
480 .hsync_len = 88,
481 .upper_margin = 30,
482 .lower_margin = 32,
483 .vsync_len = 3,
484
485 .lcdcon5 = 0x00014b02,
486 },
487 {
488 .type = S3C2410_LCDCON1_TFT,
489 .width = 640,
490 .height = 480,
491
492 .pixclock = 33333,
493 .xres = 640,
494 .yres = 480,
495 .bpp = 16,
496 .left_margin = 40,
497 .right_margin = 20,
498 .hsync_len = 88,
499 .upper_margin = 30,
500 .lower_margin = 32,
501 .vsync_len = 3,
502
503 .lcdcon5 = 0x00014b02,
504 },
505 };
506
507 /* LCD/VGA controller */
508
509 static struct s3c2410fb_mach_info __initdata bast_fb_info = {
510
511 .displays = bast_lcd_info,
512 .num_displays = ARRAY_SIZE(bast_lcd_info),
513 .default_display = 1,
514 };
515
516 /* I2C devices fitted. */
517
518 static struct i2c_board_info bast_i2c_devs[] __initdata = {
519 {
520 I2C_BOARD_INFO("tlv320aic23", 0x1a),
521 }, {
522 I2C_BOARD_INFO("simtec-pmu", 0x6b),
523 }, {
524 I2C_BOARD_INFO("ch7013", 0x75),
525 },
526 };
527
528 static struct s3c_hwmon_pdata bast_hwmon_info = {
529 /* LCD contrast (0-6.6V) */
530 .in[0] = &(struct s3c_hwmon_chcfg) {
531 .name = "lcd-contrast",
532 .mult = 3300,
533 .div = 512,
534 },
535 /* LED current feedback */
536 .in[1] = &(struct s3c_hwmon_chcfg) {
537 .name = "led-feedback",
538 .mult = 3300,
539 .div = 1024,
540 },
541 /* LCD feedback (0-6.6V) */
542 .in[2] = &(struct s3c_hwmon_chcfg) {
543 .name = "lcd-feedback",
544 .mult = 3300,
545 .div = 512,
546 },
547 /* Vcore (1.8-2.0V), Vref 3.3V */
548 .in[3] = &(struct s3c_hwmon_chcfg) {
549 .name = "vcore",
550 .mult = 3300,
551 .div = 1024,
552 },
553 };
554
555 /* Standard BAST devices */
556 // cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
557
558 static struct platform_device *bast_devices[] __initdata = {
559 &s3c_device_ohci,
560 &s3c_device_lcd,
561 &s3c_device_wdt,
562 &s3c_device_i2c0,
563 &s3c_device_rtc,
564 &s3c_device_nand,
565 &s3c_device_adc,
566 &s3c_device_hwmon,
567 &bast_device_dm9k,
568 &bast_device_asix,
569 &bast_device_axpp,
570 &bast_sio,
571 };
572
573 static struct clk *bast_clocks[] __initdata = {
574 &s3c24xx_dclk0,
575 &s3c24xx_dclk1,
576 &s3c24xx_clkout0,
577 &s3c24xx_clkout1,
578 &s3c24xx_uclk,
579 };
580
581 static struct s3c_cpufreq_board __initdata bast_cpufreq = {
582 .refresh = 7800, /* 7.8usec */
583 .auto_io = 1,
584 .need_io = 1,
585 };
586
587 static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
588 .have_mic = 1,
589 .have_lout = 1,
590 };
591
bast_map_io(void)592 static void __init bast_map_io(void)
593 {
594 /* initialise the clocks */
595
596 s3c24xx_dclk0.parent = &clk_upll;
597 s3c24xx_dclk0.rate = 12*1000*1000;
598
599 s3c24xx_dclk1.parent = &clk_upll;
600 s3c24xx_dclk1.rate = 24*1000*1000;
601
602 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
603 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
604
605 s3c24xx_uclk.parent = &s3c24xx_clkout1;
606
607 s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
608
609 s3c_hwmon_set_platdata(&bast_hwmon_info);
610
611 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
612 s3c24xx_init_clocks(0);
613 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
614 }
615
bast_init(void)616 static void __init bast_init(void)
617 {
618 register_syscore_ops(&bast_pm_syscore_ops);
619
620 s3c_i2c0_set_platdata(&bast_i2c_info);
621 s3c_nand_set_platdata(&bast_nand_info);
622 s3c24xx_fb_set_platdata(&bast_fb_info);
623 platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
624
625 i2c_register_board_info(0, bast_i2c_devs,
626 ARRAY_SIZE(bast_i2c_devs));
627
628 usb_simtec_init();
629 nor_simtec_init();
630 simtec_audio_add(NULL, true, &bast_audio);
631
632 WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset"));
633
634 s3c_cpufreq_setboard(&bast_cpufreq);
635 }
636
637 MACHINE_START(BAST, "Simtec-BAST")
638 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
639 .atag_offset = 0x100,
640 .map_io = bast_map_io,
641 .init_irq = s3c24xx_init_irq,
642 .init_machine = bast_init,
643 .timer = &s3c24xx_timer,
644 .restart = s3c2410_restart,
645 MACHINE_END
646