1 /* arch/arm/mach-s3c2410/include/mach/dma.h
2 *
3 * Copyright (C) 2003-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C24XX DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #ifndef __ASM_ARCH_DMA_H
14 #define __ASM_ARCH_DMA_H __FILE__
15
16 #include <linux/device.h>
17
18 #define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
19
20 /* We use `virtual` dma channels to hide the fact we have only a limited
21 * number of DMA channels, and not of all of them (dependent on the device)
22 * can be attached to any DMA source. We therefore let the DMA core handle
23 * the allocation of hardware channels to clients.
24 */
25
26 enum dma_ch {
27 DMACH_XD0,
28 DMACH_XD1,
29 DMACH_SDI,
30 DMACH_SPI0,
31 DMACH_SPI1,
32 DMACH_UART0,
33 DMACH_UART1,
34 DMACH_UART2,
35 DMACH_TIMER,
36 DMACH_I2S_IN,
37 DMACH_I2S_OUT,
38 DMACH_PCM_IN,
39 DMACH_PCM_OUT,
40 DMACH_MIC_IN,
41 DMACH_USB_EP1,
42 DMACH_USB_EP2,
43 DMACH_USB_EP3,
44 DMACH_USB_EP4,
45 DMACH_UART0_SRC2, /* s3c2412 second uart sources */
46 DMACH_UART1_SRC2,
47 DMACH_UART2_SRC2,
48 DMACH_UART3, /* s3c2443 has extra uart */
49 DMACH_UART3_SRC2,
50 DMACH_MAX, /* the end entry */
51 };
52
samsung_dma_has_circular(void)53 static inline bool samsung_dma_has_circular(void)
54 {
55 return false;
56 }
57
samsung_dma_is_dmadev(void)58 static inline bool samsung_dma_is_dmadev(void)
59 {
60 return false;
61 }
62
63 #include <plat/dma.h>
64
65 #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
66
67 /* we have 4 dma channels */
68 #if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416)
69 #define S3C_DMA_CHANNELS (4)
70 #else
71 #define S3C_DMA_CHANNELS (6)
72 #endif
73
74 /* types */
75
76 enum s3c2410_dma_state {
77 S3C2410_DMA_IDLE,
78 S3C2410_DMA_RUNNING,
79 S3C2410_DMA_PAUSED
80 };
81
82 /* enum s3c2410_dma_loadst
83 *
84 * This represents the state of the DMA engine, wrt to the loaded / running
85 * transfers. Since we don't have any way of knowing exactly the state of
86 * the DMA transfers, we need to know the state to make decisions on wether
87 * we can
88 *
89 * S3C2410_DMA_NONE
90 *
91 * There are no buffers loaded (the channel should be inactive)
92 *
93 * S3C2410_DMA_1LOADED
94 *
95 * There is one buffer loaded, however it has not been confirmed to be
96 * loaded by the DMA engine. This may be because the channel is not
97 * yet running, or the DMA driver decided that it was too costly to
98 * sit and wait for it to happen.
99 *
100 * S3C2410_DMA_1RUNNING
101 *
102 * The buffer has been confirmed running, and not finisged
103 *
104 * S3C2410_DMA_1LOADED_1RUNNING
105 *
106 * There is a buffer waiting to be loaded by the DMA engine, and one
107 * currently running.
108 */
109
110 enum s3c2410_dma_loadst {
111 S3C2410_DMALOAD_NONE,
112 S3C2410_DMALOAD_1LOADED,
113 S3C2410_DMALOAD_1RUNNING,
114 S3C2410_DMALOAD_1LOADED_1RUNNING,
115 };
116
117
118 /* flags */
119
120 #define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about
121 * waiting for reloads */
122 #define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */
123
124 #define S3C2410_DMAF_CIRCULAR (1 << 2) /* no circular dma support */
125
126 /* dma buffer */
127
128 struct s3c2410_dma_buf;
129
130 /* s3c2410_dma_buf
131 *
132 * internally used buffer structure to describe a queued or running
133 * buffer.
134 */
135
136 struct s3c2410_dma_buf {
137 struct s3c2410_dma_buf *next;
138 int magic; /* magic */
139 int size; /* buffer size in bytes */
140 dma_addr_t data; /* start of DMA data */
141 dma_addr_t ptr; /* where the DMA got to [1] */
142 void *id; /* client's id */
143 };
144
145 /* [1] is this updated for both recv/send modes? */
146
147 struct s3c2410_dma_stats {
148 unsigned long loads;
149 unsigned long timeout_longest;
150 unsigned long timeout_shortest;
151 unsigned long timeout_avg;
152 unsigned long timeout_failed;
153 };
154
155 struct s3c2410_dma_map;
156
157 /* struct s3c2410_dma_chan
158 *
159 * full state information for each DMA channel
160 */
161
162 struct s3c2410_dma_chan {
163 /* channel state flags and information */
164 unsigned char number; /* number of this dma channel */
165 unsigned char in_use; /* channel allocated */
166 unsigned char irq_claimed; /* irq claimed for channel */
167 unsigned char irq_enabled; /* irq enabled for channel */
168 unsigned char xfer_unit; /* size of an transfer */
169
170 /* channel state */
171
172 enum s3c2410_dma_state state;
173 enum s3c2410_dma_loadst load_state;
174 struct s3c2410_dma_client *client;
175
176 /* channel configuration */
177 enum dma_data_direction source;
178 enum dma_ch req_ch;
179 unsigned long dev_addr;
180 unsigned long load_timeout;
181 unsigned int flags; /* channel flags */
182
183 struct s3c24xx_dma_map *map; /* channel hw maps */
184
185 /* channel's hardware position and configuration */
186 void __iomem *regs; /* channels registers */
187 void __iomem *addr_reg; /* data address register */
188 unsigned int irq; /* channel irq */
189 unsigned long dcon; /* default value of DCON */
190
191 /* driver handles */
192 s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
193 s3c2410_dma_opfn_t op_fn; /* channel op callback */
194
195 /* stats gathering */
196 struct s3c2410_dma_stats *stats;
197 struct s3c2410_dma_stats stats_store;
198
199 /* buffer list and information */
200 struct s3c2410_dma_buf *curr; /* current dma buffer */
201 struct s3c2410_dma_buf *next; /* next buffer to load */
202 struct s3c2410_dma_buf *end; /* end of queue */
203
204 /* system device */
205 struct device dev;
206 };
207
208 typedef unsigned long dma_device_t;
209
210 #endif /* __ASM_ARCH_DMA_H */
211