1 /* 2 * arch/arm/mach-realview/include/mach/board-pb11mp.h 3 * 4 * Copyright (C) 2008 ARM Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 18 * MA 02110-1301, USA. 19 */ 20 21 #ifndef __ASM_ARCH_BOARD_PB11MP_H 22 #define __ASM_ARCH_BOARD_PB11MP_H 23 24 #include <mach/platform.h> 25 26 /* 27 * Peripheral addresses 28 */ 29 #define REALVIEW_PB11MP_UART0_BASE 0x10009000 /* UART 0 */ 30 #define REALVIEW_PB11MP_UART1_BASE 0x1000A000 /* UART 1 */ 31 #define REALVIEW_PB11MP_UART2_BASE 0x1000B000 /* UART 2 */ 32 #define REALVIEW_PB11MP_UART3_BASE 0x1000C000 /* UART 3 */ 33 #define REALVIEW_PB11MP_SSP_BASE 0x1000D000 /* Synchronous Serial Port */ 34 #define REALVIEW_PB11MP_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */ 35 #define REALVIEW_PB11MP_WATCHDOG_BASE 0x10010000 /* watchdog interface */ 36 #define REALVIEW_PB11MP_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */ 37 #define REALVIEW_PB11MP_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */ 38 #define REALVIEW_PB11MP_GPIO0_BASE 0x10013000 /* GPIO port 0 */ 39 #define REALVIEW_PB11MP_RTC_BASE 0x10017000 /* Real Time Clock */ 40 #define REALVIEW_PB11MP_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */ 41 #define REALVIEW_PB11MP_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */ 42 #define REALVIEW_PB11MP_SCTL_BASE 0x1001A000 /* System Controller */ 43 #define REALVIEW_PB11MP_CLCD_BASE 0x10020000 /* CLCD */ 44 #define REALVIEW_PB11MP_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */ 45 #define REALVIEW_PB11MP_DMC_BASE 0x100E0000 /* DMC configuration */ 46 #define REALVIEW_PB11MP_SMC_BASE 0x100E1000 /* SMC configuration */ 47 #define REALVIEW_PB11MP_CAN_BASE 0x100E2000 /* CAN bus */ 48 #define REALVIEW_PB11MP_CF_BASE 0x18000000 /* Compact flash */ 49 #define REALVIEW_PB11MP_CF_MEM_BASE 0x18003000 /* SMC for Compact flash */ 50 #define REALVIEW_PB11MP_GIC_CPU_BASE 0x1E000000 /* Generic interrupt controller CPU interface */ 51 #define REALVIEW_PB11MP_FLASH0_BASE 0x40000000 52 #define REALVIEW_PB11MP_FLASH0_SIZE SZ_64M 53 #define REALVIEW_PB11MP_FLASH1_BASE 0x44000000 54 #define REALVIEW_PB11MP_FLASH1_SIZE SZ_64M 55 #define REALVIEW_PB11MP_ETH_BASE 0x4E000000 /* Ethernet */ 56 #define REALVIEW_PB11MP_USB_BASE 0x4F000000 /* USB */ 57 #define REALVIEW_PB11MP_GIC_DIST_BASE 0x1E001000 /* Generic interrupt controller distributor */ 58 #define REALVIEW_PB11MP_LT_BASE 0xC0000000 /* Logic Tile expansion */ 59 #define REALVIEW_PB11MP_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */ 60 #define REALVIEW_PB11MP_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */ 61 62 #define REALVIEW_PB11MP_SYS_PLD_CTRL1 0x74 63 64 /* 65 * PB11MPCore PCI regions 66 */ 67 #define REALVIEW_PB11MP_PCI_BASE 0x90040000 /* PCI-X Unit base */ 68 #define REALVIEW_PB11MP_PCI_IO_BASE 0x90050000 /* IO Region on AHB */ 69 #define REALVIEW_PB11MP_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */ 70 71 #define REALVIEW_PB11MP_PCI_BASE_SIZE 0x10000 /* 16 Kb */ 72 #define REALVIEW_PB11MP_PCI_IO_SIZE 0x1000 /* 4 Kb */ 73 #define REALVIEW_PB11MP_PCI_MEM_SIZE 0x20000000 /* 512 MB */ 74 75 /* 76 * Testchip peripheral and fpga gic regions 77 */ 78 #define REALVIEW_TC11MP_PRIV_MEM_BASE 0x1F000000 79 #define REALVIEW_TC11MP_PRIV_MEM_SIZE SZ_8K 80 #define REALVIEW_TC11MP_SCU_BASE 0x1F000000 /* IRQ, Test chip */ 81 #define REALVIEW_TC11MP_GIC_CPU_BASE 0x1F000100 /* Test chip interrupt controller CPU interface */ 82 #define REALVIEW_TC11MP_TWD_BASE 0x1F000600 83 #define REALVIEW_TC11MP_GIC_DIST_BASE 0x1F001000 /* Test chip interrupt controller distributor */ 84 #define REALVIEW_TC11MP_L220_BASE 0x1F002000 /* L220 registers */ 85 86 /* 87 * Values for REALVIEW_SYS_RESET_CTRL 88 */ 89 #define REALVIEW_PB11MP_SYS_CTRL_RESET_CONFIGCLR 0x01 90 #define REALVIEW_PB11MP_SYS_CTRL_RESET_CONFIGINIT 0x02 91 #define REALVIEW_PB11MP_SYS_CTRL_RESET_DLLRESET 0x03 92 #define REALVIEW_PB11MP_SYS_CTRL_RESET_PLLRESET 0x04 93 #define REALVIEW_PB11MP_SYS_CTRL_RESET_POR 0x05 94 #define REALVIEW_PB11MP_SYS_CTRL_RESET_DoC 0x06 95 96 #define REALVIEW_PB11MP_SYS_CTRL_LED (1 << 0) 97 98 #endif /* __ASM_ARCH_BOARD_PB11MP_H */ 99