1 /*
2 * interrupt controller support for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9 #include <linux/init.h>
10 #include <linux/io.h>
11 #include <linux/irq.h>
12 #include <mach/hardware.h>
13 #include <asm/mach/irq.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/irqdomain.h>
17 #include <linux/syscore_ops.h>
18
19 #define SIRFSOC_INT_RISC_MASK0 0x0018
20 #define SIRFSOC_INT_RISC_MASK1 0x001C
21 #define SIRFSOC_INT_RISC_LEVEL0 0x0020
22 #define SIRFSOC_INT_RISC_LEVEL1 0x0024
23
24 void __iomem *sirfsoc_intc_base;
25
26 static __init void
sirfsoc_alloc_gc(void __iomem * base,unsigned int irq_start,unsigned int num)27 sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
28 {
29 struct irq_chip_generic *gc;
30 struct irq_chip_type *ct;
31
32 gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
33 ct = gc->chip_types;
34
35 ct->chip.irq_mask = irq_gc_mask_clr_bit;
36 ct->chip.irq_unmask = irq_gc_mask_set_bit;
37 ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
38
39 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
40 }
41
sirfsoc_irq_init(void)42 static __init void sirfsoc_irq_init(void)
43 {
44 sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32);
45 sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32, SIRFSOC_INTENAL_IRQ_END - 32);
46
47 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
48 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
49
50 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
51 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
52 }
53
54 static struct of_device_id intc_ids[] = {
55 { .compatible = "sirf,prima2-intc" },
56 {},
57 };
58
sirfsoc_of_irq_init(void)59 void __init sirfsoc_of_irq_init(void)
60 {
61 struct device_node *np;
62
63 np = of_find_matching_node(NULL, intc_ids);
64 if (!np)
65 panic("unable to find compatible intc node in dtb\n");
66
67 sirfsoc_intc_base = of_iomap(np, 0);
68 if (!sirfsoc_intc_base)
69 panic("unable to map intc cpu registers\n");
70
71 irq_domain_add_simple(np, 0);
72
73 of_node_put(np);
74
75 sirfsoc_irq_init();
76 }
77
78 struct sirfsoc_irq_status {
79 u32 mask0;
80 u32 mask1;
81 u32 level0;
82 u32 level1;
83 };
84
85 static struct sirfsoc_irq_status sirfsoc_irq_st;
86
sirfsoc_irq_suspend(void)87 static int sirfsoc_irq_suspend(void)
88 {
89 sirfsoc_irq_st.mask0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
90 sirfsoc_irq_st.mask1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
91 sirfsoc_irq_st.level0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
92 sirfsoc_irq_st.level1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
93
94 return 0;
95 }
96
sirfsoc_irq_resume(void)97 static void sirfsoc_irq_resume(void)
98 {
99 writel_relaxed(sirfsoc_irq_st.mask0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
100 writel_relaxed(sirfsoc_irq_st.mask1, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
101 writel_relaxed(sirfsoc_irq_st.level0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
102 writel_relaxed(sirfsoc_irq_st.level1, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
103 }
104
105 static struct syscore_ops sirfsoc_irq_syscore_ops = {
106 .suspend = sirfsoc_irq_suspend,
107 .resume = sirfsoc_irq_resume,
108 };
109
sirfsoc_irq_pm_init(void)110 static int __init sirfsoc_irq_pm_init(void)
111 {
112 register_syscore_ops(&sirfsoc_irq_syscore_ops);
113 return 0;
114 }
115 device_initcall(sirfsoc_irq_pm_init);
116