1 /*
2 * Hardware modules present on the OMAP44xx chips
3 *
4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21 #include <linux/io.h>
22
23 #include <plat/omap_hwmod.h>
24 #include <plat/cpu.h>
25 #include <plat/i2c.h>
26 #include <plat/gpio.h>
27 #include <plat/dma.h>
28 #include <plat/mcspi.h>
29 #include <plat/mcbsp.h>
30 #include <plat/mmc.h>
31 #include <plat/i2c.h>
32 #include <plat/dmtimer.h>
33 #include <plat/common.h>
34
35 #include "omap_hwmod_common_data.h"
36
37 #include "cm1_44xx.h"
38 #include "cm2_44xx.h"
39 #include "prm44xx.h"
40 #include "prm-regbits-44xx.h"
41 #include "wd_timer.h"
42
43 /* Base offset for all OMAP4 interrupts external to MPUSS */
44 #define OMAP44XX_IRQ_GIC_START 32
45
46 /* Base offset for all OMAP4 dma requests */
47 #define OMAP44XX_DMA_REQ_START 1
48
49 /* Backward references (IPs with Bus Master capability) */
50 static struct omap_hwmod omap44xx_aess_hwmod;
51 static struct omap_hwmod omap44xx_dma_system_hwmod;
52 static struct omap_hwmod omap44xx_dmm_hwmod;
53 static struct omap_hwmod omap44xx_dsp_hwmod;
54 static struct omap_hwmod omap44xx_dss_hwmod;
55 static struct omap_hwmod omap44xx_emif_fw_hwmod;
56 static struct omap_hwmod omap44xx_hsi_hwmod;
57 static struct omap_hwmod omap44xx_ipu_hwmod;
58 static struct omap_hwmod omap44xx_iss_hwmod;
59 static struct omap_hwmod omap44xx_iva_hwmod;
60 static struct omap_hwmod omap44xx_l3_instr_hwmod;
61 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
62 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
63 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
64 static struct omap_hwmod omap44xx_l4_abe_hwmod;
65 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
66 static struct omap_hwmod omap44xx_l4_per_hwmod;
67 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
68 static struct omap_hwmod omap44xx_mmc1_hwmod;
69 static struct omap_hwmod omap44xx_mmc2_hwmod;
70 static struct omap_hwmod omap44xx_mpu_hwmod;
71 static struct omap_hwmod omap44xx_mpu_private_hwmod;
72 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
73 static struct omap_hwmod omap44xx_usb_host_hs_hwmod;
74 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod;
75
76 /*
77 * Interconnects omap_hwmod structures
78 * hwmods that compose the global OMAP interconnect
79 */
80
81 /*
82 * 'dmm' class
83 * instance(s): dmm
84 */
85 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
86 .name = "dmm",
87 };
88
89 /* dmm */
90 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
91 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
92 { .irq = -1 }
93 };
94
95 /* l3_main_1 -> dmm */
96 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
97 .master = &omap44xx_l3_main_1_hwmod,
98 .slave = &omap44xx_dmm_hwmod,
99 .clk = "l3_div_ck",
100 .user = OCP_USER_SDMA,
101 };
102
103 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
104 {
105 .pa_start = 0x4e000000,
106 .pa_end = 0x4e0007ff,
107 .flags = ADDR_TYPE_RT
108 },
109 { }
110 };
111
112 /* mpu -> dmm */
113 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
114 .master = &omap44xx_mpu_hwmod,
115 .slave = &omap44xx_dmm_hwmod,
116 .clk = "l3_div_ck",
117 .addr = omap44xx_dmm_addrs,
118 .user = OCP_USER_MPU,
119 };
120
121 /* dmm slave ports */
122 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
123 &omap44xx_l3_main_1__dmm,
124 &omap44xx_mpu__dmm,
125 };
126
127 static struct omap_hwmod omap44xx_dmm_hwmod = {
128 .name = "dmm",
129 .class = &omap44xx_dmm_hwmod_class,
130 .clkdm_name = "l3_emif_clkdm",
131 .prcm = {
132 .omap4 = {
133 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
134 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
135 },
136 },
137 .slaves = omap44xx_dmm_slaves,
138 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
139 .mpu_irqs = omap44xx_dmm_irqs,
140 };
141
142 /*
143 * 'emif_fw' class
144 * instance(s): emif_fw
145 */
146 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
147 .name = "emif_fw",
148 };
149
150 /* emif_fw */
151 /* dmm -> emif_fw */
152 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
153 .master = &omap44xx_dmm_hwmod,
154 .slave = &omap44xx_emif_fw_hwmod,
155 .clk = "l3_div_ck",
156 .user = OCP_USER_MPU | OCP_USER_SDMA,
157 };
158
159 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
160 {
161 .pa_start = 0x4a20c000,
162 .pa_end = 0x4a20c0ff,
163 .flags = ADDR_TYPE_RT
164 },
165 { }
166 };
167
168 /* l4_cfg -> emif_fw */
169 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
170 .master = &omap44xx_l4_cfg_hwmod,
171 .slave = &omap44xx_emif_fw_hwmod,
172 .clk = "l4_div_ck",
173 .addr = omap44xx_emif_fw_addrs,
174 .user = OCP_USER_MPU,
175 };
176
177 /* emif_fw slave ports */
178 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
179 &omap44xx_dmm__emif_fw,
180 &omap44xx_l4_cfg__emif_fw,
181 };
182
183 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
184 .name = "emif_fw",
185 .class = &omap44xx_emif_fw_hwmod_class,
186 .clkdm_name = "l3_emif_clkdm",
187 .prcm = {
188 .omap4 = {
189 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
190 .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
191 },
192 },
193 .slaves = omap44xx_emif_fw_slaves,
194 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
195 };
196
197 /*
198 * 'l3' class
199 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
200 */
201 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
202 .name = "l3",
203 };
204
205 /* l3_instr */
206 /* iva -> l3_instr */
207 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
208 .master = &omap44xx_iva_hwmod,
209 .slave = &omap44xx_l3_instr_hwmod,
210 .clk = "l3_div_ck",
211 .user = OCP_USER_MPU | OCP_USER_SDMA,
212 };
213
214 /* l3_main_3 -> l3_instr */
215 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
216 .master = &omap44xx_l3_main_3_hwmod,
217 .slave = &omap44xx_l3_instr_hwmod,
218 .clk = "l3_div_ck",
219 .user = OCP_USER_MPU | OCP_USER_SDMA,
220 };
221
222 /* l3_instr slave ports */
223 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
224 &omap44xx_iva__l3_instr,
225 &omap44xx_l3_main_3__l3_instr,
226 };
227
228 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
229 .name = "l3_instr",
230 .class = &omap44xx_l3_hwmod_class,
231 .clkdm_name = "l3_instr_clkdm",
232 .prcm = {
233 .omap4 = {
234 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
235 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
236 .modulemode = MODULEMODE_HWCTRL,
237 },
238 },
239 .slaves = omap44xx_l3_instr_slaves,
240 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
241 };
242
243 /* l3_main_1 */
244 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
245 { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
246 { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
247 { .irq = -1 }
248 };
249
250 /* dsp -> l3_main_1 */
251 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
252 .master = &omap44xx_dsp_hwmod,
253 .slave = &omap44xx_l3_main_1_hwmod,
254 .clk = "l3_div_ck",
255 .user = OCP_USER_MPU | OCP_USER_SDMA,
256 };
257
258 /* dss -> l3_main_1 */
259 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
260 .master = &omap44xx_dss_hwmod,
261 .slave = &omap44xx_l3_main_1_hwmod,
262 .clk = "l3_div_ck",
263 .user = OCP_USER_MPU | OCP_USER_SDMA,
264 };
265
266 /* l3_main_2 -> l3_main_1 */
267 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
268 .master = &omap44xx_l3_main_2_hwmod,
269 .slave = &omap44xx_l3_main_1_hwmod,
270 .clk = "l3_div_ck",
271 .user = OCP_USER_MPU | OCP_USER_SDMA,
272 };
273
274 /* l4_cfg -> l3_main_1 */
275 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
276 .master = &omap44xx_l4_cfg_hwmod,
277 .slave = &omap44xx_l3_main_1_hwmod,
278 .clk = "l4_div_ck",
279 .user = OCP_USER_MPU | OCP_USER_SDMA,
280 };
281
282 /* mmc1 -> l3_main_1 */
283 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
284 .master = &omap44xx_mmc1_hwmod,
285 .slave = &omap44xx_l3_main_1_hwmod,
286 .clk = "l3_div_ck",
287 .user = OCP_USER_MPU | OCP_USER_SDMA,
288 };
289
290 /* mmc2 -> l3_main_1 */
291 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
292 .master = &omap44xx_mmc2_hwmod,
293 .slave = &omap44xx_l3_main_1_hwmod,
294 .clk = "l3_div_ck",
295 .user = OCP_USER_MPU | OCP_USER_SDMA,
296 };
297
298 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
299 {
300 .pa_start = 0x44000000,
301 .pa_end = 0x44000fff,
302 .flags = ADDR_TYPE_RT
303 },
304 { }
305 };
306
307 /* mpu -> l3_main_1 */
308 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
309 .master = &omap44xx_mpu_hwmod,
310 .slave = &omap44xx_l3_main_1_hwmod,
311 .clk = "l3_div_ck",
312 .addr = omap44xx_l3_main_1_addrs,
313 .user = OCP_USER_MPU,
314 };
315
316 /* l3_main_1 slave ports */
317 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
318 &omap44xx_dsp__l3_main_1,
319 &omap44xx_dss__l3_main_1,
320 &omap44xx_l3_main_2__l3_main_1,
321 &omap44xx_l4_cfg__l3_main_1,
322 &omap44xx_mmc1__l3_main_1,
323 &omap44xx_mmc2__l3_main_1,
324 &omap44xx_mpu__l3_main_1,
325 };
326
327 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
328 .name = "l3_main_1",
329 .class = &omap44xx_l3_hwmod_class,
330 .clkdm_name = "l3_1_clkdm",
331 .mpu_irqs = omap44xx_l3_main_1_irqs,
332 .prcm = {
333 .omap4 = {
334 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
335 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
336 },
337 },
338 .slaves = omap44xx_l3_main_1_slaves,
339 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
340 };
341
342 /* l3_main_2 */
343 /* dma_system -> l3_main_2 */
344 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
345 .master = &omap44xx_dma_system_hwmod,
346 .slave = &omap44xx_l3_main_2_hwmod,
347 .clk = "l3_div_ck",
348 .user = OCP_USER_MPU | OCP_USER_SDMA,
349 };
350
351 /* hsi -> l3_main_2 */
352 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
353 .master = &omap44xx_hsi_hwmod,
354 .slave = &omap44xx_l3_main_2_hwmod,
355 .clk = "l3_div_ck",
356 .user = OCP_USER_MPU | OCP_USER_SDMA,
357 };
358
359 /* ipu -> l3_main_2 */
360 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
361 .master = &omap44xx_ipu_hwmod,
362 .slave = &omap44xx_l3_main_2_hwmod,
363 .clk = "l3_div_ck",
364 .user = OCP_USER_MPU | OCP_USER_SDMA,
365 };
366
367 /* iss -> l3_main_2 */
368 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
369 .master = &omap44xx_iss_hwmod,
370 .slave = &omap44xx_l3_main_2_hwmod,
371 .clk = "l3_div_ck",
372 .user = OCP_USER_MPU | OCP_USER_SDMA,
373 };
374
375 /* iva -> l3_main_2 */
376 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
377 .master = &omap44xx_iva_hwmod,
378 .slave = &omap44xx_l3_main_2_hwmod,
379 .clk = "l3_div_ck",
380 .user = OCP_USER_MPU | OCP_USER_SDMA,
381 };
382
383 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
384 {
385 .pa_start = 0x44800000,
386 .pa_end = 0x44801fff,
387 .flags = ADDR_TYPE_RT
388 },
389 { }
390 };
391
392 /* l3_main_1 -> l3_main_2 */
393 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
394 .master = &omap44xx_l3_main_1_hwmod,
395 .slave = &omap44xx_l3_main_2_hwmod,
396 .clk = "l3_div_ck",
397 .addr = omap44xx_l3_main_2_addrs,
398 .user = OCP_USER_MPU,
399 };
400
401 /* l4_cfg -> l3_main_2 */
402 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
403 .master = &omap44xx_l4_cfg_hwmod,
404 .slave = &omap44xx_l3_main_2_hwmod,
405 .clk = "l4_div_ck",
406 .user = OCP_USER_MPU | OCP_USER_SDMA,
407 };
408
409 /* usb_otg_hs -> l3_main_2 */
410 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
411 .master = &omap44xx_usb_otg_hs_hwmod,
412 .slave = &omap44xx_l3_main_2_hwmod,
413 .clk = "l3_div_ck",
414 .user = OCP_USER_MPU | OCP_USER_SDMA,
415 };
416
417 /* l3_main_2 slave ports */
418 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
419 &omap44xx_dma_system__l3_main_2,
420 &omap44xx_hsi__l3_main_2,
421 &omap44xx_ipu__l3_main_2,
422 &omap44xx_iss__l3_main_2,
423 &omap44xx_iva__l3_main_2,
424 &omap44xx_l3_main_1__l3_main_2,
425 &omap44xx_l4_cfg__l3_main_2,
426 &omap44xx_usb_otg_hs__l3_main_2,
427 };
428
429 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
430 .name = "l3_main_2",
431 .class = &omap44xx_l3_hwmod_class,
432 .clkdm_name = "l3_2_clkdm",
433 .prcm = {
434 .omap4 = {
435 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
436 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
437 },
438 },
439 .slaves = omap44xx_l3_main_2_slaves,
440 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
441 };
442
443 /* l3_main_3 */
444 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
445 {
446 .pa_start = 0x45000000,
447 .pa_end = 0x45000fff,
448 .flags = ADDR_TYPE_RT
449 },
450 { }
451 };
452
453 /* l3_main_1 -> l3_main_3 */
454 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
455 .master = &omap44xx_l3_main_1_hwmod,
456 .slave = &omap44xx_l3_main_3_hwmod,
457 .clk = "l3_div_ck",
458 .addr = omap44xx_l3_main_3_addrs,
459 .user = OCP_USER_MPU,
460 };
461
462 /* l3_main_2 -> l3_main_3 */
463 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
464 .master = &omap44xx_l3_main_2_hwmod,
465 .slave = &omap44xx_l3_main_3_hwmod,
466 .clk = "l3_div_ck",
467 .user = OCP_USER_MPU | OCP_USER_SDMA,
468 };
469
470 /* l4_cfg -> l3_main_3 */
471 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
472 .master = &omap44xx_l4_cfg_hwmod,
473 .slave = &omap44xx_l3_main_3_hwmod,
474 .clk = "l4_div_ck",
475 .user = OCP_USER_MPU | OCP_USER_SDMA,
476 };
477
478 /* l3_main_3 slave ports */
479 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
480 &omap44xx_l3_main_1__l3_main_3,
481 &omap44xx_l3_main_2__l3_main_3,
482 &omap44xx_l4_cfg__l3_main_3,
483 };
484
485 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
486 .name = "l3_main_3",
487 .class = &omap44xx_l3_hwmod_class,
488 .clkdm_name = "l3_instr_clkdm",
489 .prcm = {
490 .omap4 = {
491 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
492 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
493 .modulemode = MODULEMODE_HWCTRL,
494 },
495 },
496 .slaves = omap44xx_l3_main_3_slaves,
497 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
498 };
499
500 /*
501 * 'l4' class
502 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
503 */
504 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
505 .name = "l4",
506 };
507
508 /* l4_abe */
509 /* aess -> l4_abe */
510 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
511 .master = &omap44xx_aess_hwmod,
512 .slave = &omap44xx_l4_abe_hwmod,
513 .clk = "ocp_abe_iclk",
514 .user = OCP_USER_MPU | OCP_USER_SDMA,
515 };
516
517 /* dsp -> l4_abe */
518 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
519 .master = &omap44xx_dsp_hwmod,
520 .slave = &omap44xx_l4_abe_hwmod,
521 .clk = "ocp_abe_iclk",
522 .user = OCP_USER_MPU | OCP_USER_SDMA,
523 };
524
525 /* l3_main_1 -> l4_abe */
526 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
527 .master = &omap44xx_l3_main_1_hwmod,
528 .slave = &omap44xx_l4_abe_hwmod,
529 .clk = "l3_div_ck",
530 .user = OCP_USER_MPU | OCP_USER_SDMA,
531 };
532
533 /* mpu -> l4_abe */
534 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
535 .master = &omap44xx_mpu_hwmod,
536 .slave = &omap44xx_l4_abe_hwmod,
537 .clk = "ocp_abe_iclk",
538 .user = OCP_USER_MPU | OCP_USER_SDMA,
539 };
540
541 /* l4_abe slave ports */
542 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
543 &omap44xx_aess__l4_abe,
544 &omap44xx_dsp__l4_abe,
545 &omap44xx_l3_main_1__l4_abe,
546 &omap44xx_mpu__l4_abe,
547 };
548
549 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
550 .name = "l4_abe",
551 .class = &omap44xx_l4_hwmod_class,
552 .clkdm_name = "abe_clkdm",
553 .prcm = {
554 .omap4 = {
555 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
556 },
557 },
558 .slaves = omap44xx_l4_abe_slaves,
559 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
560 };
561
562 /* l4_cfg */
563 /* l3_main_1 -> l4_cfg */
564 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
565 .master = &omap44xx_l3_main_1_hwmod,
566 .slave = &omap44xx_l4_cfg_hwmod,
567 .clk = "l3_div_ck",
568 .user = OCP_USER_MPU | OCP_USER_SDMA,
569 };
570
571 /* l4_cfg slave ports */
572 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
573 &omap44xx_l3_main_1__l4_cfg,
574 };
575
576 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
577 .name = "l4_cfg",
578 .class = &omap44xx_l4_hwmod_class,
579 .clkdm_name = "l4_cfg_clkdm",
580 .prcm = {
581 .omap4 = {
582 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
583 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
584 },
585 },
586 .slaves = omap44xx_l4_cfg_slaves,
587 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
588 };
589
590 /* l4_per */
591 /* l3_main_2 -> l4_per */
592 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
593 .master = &omap44xx_l3_main_2_hwmod,
594 .slave = &omap44xx_l4_per_hwmod,
595 .clk = "l3_div_ck",
596 .user = OCP_USER_MPU | OCP_USER_SDMA,
597 };
598
599 /* l4_per slave ports */
600 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
601 &omap44xx_l3_main_2__l4_per,
602 };
603
604 static struct omap_hwmod omap44xx_l4_per_hwmod = {
605 .name = "l4_per",
606 .class = &omap44xx_l4_hwmod_class,
607 .clkdm_name = "l4_per_clkdm",
608 .prcm = {
609 .omap4 = {
610 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
611 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
612 },
613 },
614 .slaves = omap44xx_l4_per_slaves,
615 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
616 };
617
618 /* l4_wkup */
619 /* l4_cfg -> l4_wkup */
620 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
621 .master = &omap44xx_l4_cfg_hwmod,
622 .slave = &omap44xx_l4_wkup_hwmod,
623 .clk = "l4_div_ck",
624 .user = OCP_USER_MPU | OCP_USER_SDMA,
625 };
626
627 /* l4_wkup slave ports */
628 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
629 &omap44xx_l4_cfg__l4_wkup,
630 };
631
632 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
633 .name = "l4_wkup",
634 .class = &omap44xx_l4_hwmod_class,
635 .clkdm_name = "l4_wkup_clkdm",
636 .prcm = {
637 .omap4 = {
638 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
639 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
640 },
641 },
642 .slaves = omap44xx_l4_wkup_slaves,
643 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
644 };
645
646 /*
647 * 'mpu_bus' class
648 * instance(s): mpu_private
649 */
650 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
651 .name = "mpu_bus",
652 };
653
654 /* mpu_private */
655 /* mpu -> mpu_private */
656 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
657 .master = &omap44xx_mpu_hwmod,
658 .slave = &omap44xx_mpu_private_hwmod,
659 .clk = "l3_div_ck",
660 .user = OCP_USER_MPU | OCP_USER_SDMA,
661 };
662
663 /* mpu_private slave ports */
664 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
665 &omap44xx_mpu__mpu_private,
666 };
667
668 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
669 .name = "mpu_private",
670 .class = &omap44xx_mpu_bus_hwmod_class,
671 .clkdm_name = "mpuss_clkdm",
672 .slaves = omap44xx_mpu_private_slaves,
673 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
674 };
675
676 /*
677 * Modules omap_hwmod structures
678 *
679 * The following IPs are excluded for the moment because:
680 * - They do not need an explicit SW control using omap_hwmod API.
681 * - They still need to be validated with the driver
682 * properly adapted to omap_hwmod / omap_device
683 *
684 * c2c
685 * c2c_target_fw
686 * cm_core
687 * cm_core_aon
688 * ctrl_module_core
689 * ctrl_module_pad_core
690 * ctrl_module_pad_wkup
691 * ctrl_module_wkup
692 * debugss
693 * efuse_ctrl_cust
694 * efuse_ctrl_std
695 * elm
696 * emif1
697 * emif2
698 * fdif
699 * gpmc
700 * gpu
701 * hdq1w
702 * mcasp
703 * mpu_c0
704 * mpu_c1
705 * ocmc_ram
706 * ocp2scp_usb_phy
707 * ocp_wp_noc
708 * prcm_mpu
709 * prm
710 * scrm
711 * sl2if
712 * slimbus1
713 * slimbus2
714 * usb_host_fs
715 * usb_host_hs
716 * usb_phy_cm
717 * usb_tll_hs
718 * usim
719 */
720
721 /*
722 * 'aess' class
723 * audio engine sub system
724 */
725
726 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
727 .rev_offs = 0x0000,
728 .sysc_offs = 0x0010,
729 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
730 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
731 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
732 MSTANDBY_SMART_WKUP),
733 .sysc_fields = &omap_hwmod_sysc_type2,
734 };
735
736 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
737 .name = "aess",
738 .sysc = &omap44xx_aess_sysc,
739 };
740
741 /* aess */
742 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
743 { .irq = 99 + OMAP44XX_IRQ_GIC_START },
744 { .irq = -1 }
745 };
746
747 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
748 { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
749 { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
750 { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
751 { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
752 { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
753 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
754 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
755 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
756 { .dma_req = -1 }
757 };
758
759 /* aess master ports */
760 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
761 &omap44xx_aess__l4_abe,
762 };
763
764 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
765 {
766 .pa_start = 0x401f1000,
767 .pa_end = 0x401f13ff,
768 .flags = ADDR_TYPE_RT
769 },
770 { }
771 };
772
773 /* l4_abe -> aess */
774 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
775 .master = &omap44xx_l4_abe_hwmod,
776 .slave = &omap44xx_aess_hwmod,
777 .clk = "ocp_abe_iclk",
778 .addr = omap44xx_aess_addrs,
779 .user = OCP_USER_MPU,
780 };
781
782 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
783 {
784 .pa_start = 0x490f1000,
785 .pa_end = 0x490f13ff,
786 .flags = ADDR_TYPE_RT
787 },
788 { }
789 };
790
791 /* l4_abe -> aess (dma) */
792 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
793 .master = &omap44xx_l4_abe_hwmod,
794 .slave = &omap44xx_aess_hwmod,
795 .clk = "ocp_abe_iclk",
796 .addr = omap44xx_aess_dma_addrs,
797 .user = OCP_USER_SDMA,
798 };
799
800 /* aess slave ports */
801 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
802 &omap44xx_l4_abe__aess,
803 &omap44xx_l4_abe__aess_dma,
804 };
805
806 static struct omap_hwmod omap44xx_aess_hwmod = {
807 .name = "aess",
808 .class = &omap44xx_aess_hwmod_class,
809 .clkdm_name = "abe_clkdm",
810 .mpu_irqs = omap44xx_aess_irqs,
811 .sdma_reqs = omap44xx_aess_sdma_reqs,
812 .main_clk = "aess_fck",
813 .prcm = {
814 .omap4 = {
815 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
816 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
817 .modulemode = MODULEMODE_SWCTRL,
818 },
819 },
820 .slaves = omap44xx_aess_slaves,
821 .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves),
822 .masters = omap44xx_aess_masters,
823 .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters),
824 };
825
826 /*
827 * 'bandgap' class
828 * bangap reference for ldo regulators
829 */
830
831 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
832 .name = "bandgap",
833 };
834
835 /* bandgap */
836 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
837 { .role = "fclk", .clk = "bandgap_fclk" },
838 };
839
840 static struct omap_hwmod omap44xx_bandgap_hwmod = {
841 .name = "bandgap",
842 .class = &omap44xx_bandgap_hwmod_class,
843 .clkdm_name = "l4_wkup_clkdm",
844 .prcm = {
845 .omap4 = {
846 .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
847 },
848 },
849 .opt_clks = bandgap_opt_clks,
850 .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks),
851 };
852
853 /*
854 * 'counter' class
855 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
856 */
857
858 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
859 .rev_offs = 0x0000,
860 .sysc_offs = 0x0004,
861 .sysc_flags = SYSC_HAS_SIDLEMODE,
862 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
863 SIDLE_SMART_WKUP),
864 .sysc_fields = &omap_hwmod_sysc_type1,
865 };
866
867 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
868 .name = "counter",
869 .sysc = &omap44xx_counter_sysc,
870 };
871
872 /* counter_32k */
873 static struct omap_hwmod omap44xx_counter_32k_hwmod;
874 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
875 {
876 .pa_start = 0x4a304000,
877 .pa_end = 0x4a30401f,
878 .flags = ADDR_TYPE_RT
879 },
880 { }
881 };
882
883 /* l4_wkup -> counter_32k */
884 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
885 .master = &omap44xx_l4_wkup_hwmod,
886 .slave = &omap44xx_counter_32k_hwmod,
887 .clk = "l4_wkup_clk_mux_ck",
888 .addr = omap44xx_counter_32k_addrs,
889 .user = OCP_USER_MPU | OCP_USER_SDMA,
890 };
891
892 /* counter_32k slave ports */
893 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
894 &omap44xx_l4_wkup__counter_32k,
895 };
896
897 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
898 .name = "counter_32k",
899 .class = &omap44xx_counter_hwmod_class,
900 .clkdm_name = "l4_wkup_clkdm",
901 .flags = HWMOD_SWSUP_SIDLE,
902 .main_clk = "sys_32k_ck",
903 .prcm = {
904 .omap4 = {
905 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
906 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
907 },
908 },
909 .slaves = omap44xx_counter_32k_slaves,
910 .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves),
911 };
912
913 /*
914 * 'dma' class
915 * dma controller for data exchange between memory to memory (i.e. internal or
916 * external memory) and gp peripherals to memory or memory to gp peripherals
917 */
918
919 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
920 .rev_offs = 0x0000,
921 .sysc_offs = 0x002c,
922 .syss_offs = 0x0028,
923 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
924 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
925 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
926 SYSS_HAS_RESET_STATUS),
927 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
928 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
929 .sysc_fields = &omap_hwmod_sysc_type1,
930 };
931
932 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
933 .name = "dma",
934 .sysc = &omap44xx_dma_sysc,
935 };
936
937 /* dma dev_attr */
938 static struct omap_dma_dev_attr dma_dev_attr = {
939 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
940 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
941 .lch_count = 32,
942 };
943
944 /* dma_system */
945 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
946 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
947 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
948 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
949 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
950 { .irq = -1 }
951 };
952
953 /* dma_system master ports */
954 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
955 &omap44xx_dma_system__l3_main_2,
956 };
957
958 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
959 {
960 .pa_start = 0x4a056000,
961 .pa_end = 0x4a056fff,
962 .flags = ADDR_TYPE_RT
963 },
964 { }
965 };
966
967 /* l4_cfg -> dma_system */
968 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
969 .master = &omap44xx_l4_cfg_hwmod,
970 .slave = &omap44xx_dma_system_hwmod,
971 .clk = "l4_div_ck",
972 .addr = omap44xx_dma_system_addrs,
973 .user = OCP_USER_MPU | OCP_USER_SDMA,
974 };
975
976 /* dma_system slave ports */
977 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
978 &omap44xx_l4_cfg__dma_system,
979 };
980
981 static struct omap_hwmod omap44xx_dma_system_hwmod = {
982 .name = "dma_system",
983 .class = &omap44xx_dma_hwmod_class,
984 .clkdm_name = "l3_dma_clkdm",
985 .mpu_irqs = omap44xx_dma_system_irqs,
986 .main_clk = "l3_div_ck",
987 .prcm = {
988 .omap4 = {
989 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
990 .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
991 },
992 },
993 .dev_attr = &dma_dev_attr,
994 .slaves = omap44xx_dma_system_slaves,
995 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
996 .masters = omap44xx_dma_system_masters,
997 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
998 };
999
1000 /*
1001 * 'dmic' class
1002 * digital microphone controller
1003 */
1004
1005 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
1006 .rev_offs = 0x0000,
1007 .sysc_offs = 0x0010,
1008 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1009 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1010 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1011 SIDLE_SMART_WKUP),
1012 .sysc_fields = &omap_hwmod_sysc_type2,
1013 };
1014
1015 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
1016 .name = "dmic",
1017 .sysc = &omap44xx_dmic_sysc,
1018 };
1019
1020 /* dmic */
1021 static struct omap_hwmod omap44xx_dmic_hwmod;
1022 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
1023 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
1024 { .irq = -1 }
1025 };
1026
1027 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
1028 { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
1029 { .dma_req = -1 }
1030 };
1031
1032 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
1033 {
1034 .name = "mpu",
1035 .pa_start = 0x4012e000,
1036 .pa_end = 0x4012e07f,
1037 .flags = ADDR_TYPE_RT
1038 },
1039 { }
1040 };
1041
1042 /* l4_abe -> dmic */
1043 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
1044 .master = &omap44xx_l4_abe_hwmod,
1045 .slave = &omap44xx_dmic_hwmod,
1046 .clk = "ocp_abe_iclk",
1047 .addr = omap44xx_dmic_addrs,
1048 .user = OCP_USER_MPU,
1049 };
1050
1051 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
1052 {
1053 .name = "dma",
1054 .pa_start = 0x4902e000,
1055 .pa_end = 0x4902e07f,
1056 .flags = ADDR_TYPE_RT
1057 },
1058 { }
1059 };
1060
1061 /* l4_abe -> dmic (dma) */
1062 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
1063 .master = &omap44xx_l4_abe_hwmod,
1064 .slave = &omap44xx_dmic_hwmod,
1065 .clk = "ocp_abe_iclk",
1066 .addr = omap44xx_dmic_dma_addrs,
1067 .user = OCP_USER_SDMA,
1068 };
1069
1070 /* dmic slave ports */
1071 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
1072 &omap44xx_l4_abe__dmic,
1073 &omap44xx_l4_abe__dmic_dma,
1074 };
1075
1076 static struct omap_hwmod omap44xx_dmic_hwmod = {
1077 .name = "dmic",
1078 .class = &omap44xx_dmic_hwmod_class,
1079 .clkdm_name = "abe_clkdm",
1080 .mpu_irqs = omap44xx_dmic_irqs,
1081 .sdma_reqs = omap44xx_dmic_sdma_reqs,
1082 .main_clk = "dmic_fck",
1083 .prcm = {
1084 .omap4 = {
1085 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
1086 .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
1087 .modulemode = MODULEMODE_SWCTRL,
1088 },
1089 },
1090 .slaves = omap44xx_dmic_slaves,
1091 .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves),
1092 };
1093
1094 /*
1095 * 'dsp' class
1096 * dsp sub-system
1097 */
1098
1099 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1100 .name = "dsp",
1101 };
1102
1103 /* dsp */
1104 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1105 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1106 { .irq = -1 }
1107 };
1108
1109 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1110 { .name = "mmu_cache", .rst_shift = 1 },
1111 };
1112
1113 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1114 { .name = "dsp", .rst_shift = 0 },
1115 };
1116
1117 /* dsp -> iva */
1118 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1119 .master = &omap44xx_dsp_hwmod,
1120 .slave = &omap44xx_iva_hwmod,
1121 .clk = "dpll_iva_m5x2_ck",
1122 };
1123
1124 /* dsp master ports */
1125 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1126 &omap44xx_dsp__l3_main_1,
1127 &omap44xx_dsp__l4_abe,
1128 &omap44xx_dsp__iva,
1129 };
1130
1131 /* l4_cfg -> dsp */
1132 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1133 .master = &omap44xx_l4_cfg_hwmod,
1134 .slave = &omap44xx_dsp_hwmod,
1135 .clk = "l4_div_ck",
1136 .user = OCP_USER_MPU | OCP_USER_SDMA,
1137 };
1138
1139 /* dsp slave ports */
1140 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1141 &omap44xx_l4_cfg__dsp,
1142 };
1143
1144 /* Pseudo hwmod for reset control purpose only */
1145 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1146 .name = "dsp_c0",
1147 .class = &omap44xx_dsp_hwmod_class,
1148 .clkdm_name = "tesla_clkdm",
1149 .flags = HWMOD_INIT_NO_RESET,
1150 .rst_lines = omap44xx_dsp_c0_resets,
1151 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1152 .prcm = {
1153 .omap4 = {
1154 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1155 },
1156 },
1157 };
1158
1159 static struct omap_hwmod omap44xx_dsp_hwmod = {
1160 .name = "dsp",
1161 .class = &omap44xx_dsp_hwmod_class,
1162 .clkdm_name = "tesla_clkdm",
1163 .mpu_irqs = omap44xx_dsp_irqs,
1164 .rst_lines = omap44xx_dsp_resets,
1165 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
1166 .main_clk = "dsp_fck",
1167 .prcm = {
1168 .omap4 = {
1169 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
1170 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1171 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
1172 .modulemode = MODULEMODE_HWCTRL,
1173 },
1174 },
1175 .slaves = omap44xx_dsp_slaves,
1176 .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
1177 .masters = omap44xx_dsp_masters,
1178 .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
1179 };
1180
1181 /*
1182 * 'dss' class
1183 * display sub-system
1184 */
1185
1186 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1187 .rev_offs = 0x0000,
1188 .syss_offs = 0x0014,
1189 .sysc_flags = SYSS_HAS_RESET_STATUS,
1190 };
1191
1192 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1193 .name = "dss",
1194 .sysc = &omap44xx_dss_sysc,
1195 .reset = omap_dss_reset,
1196 };
1197
1198 /* dss */
1199 /* dss master ports */
1200 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1201 &omap44xx_dss__l3_main_1,
1202 };
1203
1204 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1205 {
1206 .pa_start = 0x58000000,
1207 .pa_end = 0x5800007f,
1208 .flags = ADDR_TYPE_RT
1209 },
1210 { }
1211 };
1212
1213 /* l3_main_2 -> dss */
1214 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1215 .master = &omap44xx_l3_main_2_hwmod,
1216 .slave = &omap44xx_dss_hwmod,
1217 .clk = "dss_fck",
1218 .addr = omap44xx_dss_dma_addrs,
1219 .user = OCP_USER_SDMA,
1220 };
1221
1222 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1223 {
1224 .pa_start = 0x48040000,
1225 .pa_end = 0x4804007f,
1226 .flags = ADDR_TYPE_RT
1227 },
1228 { }
1229 };
1230
1231 /* l4_per -> dss */
1232 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1233 .master = &omap44xx_l4_per_hwmod,
1234 .slave = &omap44xx_dss_hwmod,
1235 .clk = "l4_div_ck",
1236 .addr = omap44xx_dss_addrs,
1237 .user = OCP_USER_MPU,
1238 };
1239
1240 /* dss slave ports */
1241 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1242 &omap44xx_l3_main_2__dss,
1243 &omap44xx_l4_per__dss,
1244 };
1245
1246 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1247 { .role = "sys_clk", .clk = "dss_sys_clk" },
1248 { .role = "tv_clk", .clk = "dss_tv_clk" },
1249 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1250 };
1251
1252 static struct omap_hwmod omap44xx_dss_hwmod = {
1253 .name = "dss_core",
1254 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1255 .class = &omap44xx_dss_hwmod_class,
1256 .clkdm_name = "l3_dss_clkdm",
1257 .main_clk = "dss_dss_clk",
1258 .prcm = {
1259 .omap4 = {
1260 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1261 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1262 },
1263 },
1264 .opt_clks = dss_opt_clks,
1265 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1266 .slaves = omap44xx_dss_slaves,
1267 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
1268 .masters = omap44xx_dss_masters,
1269 .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
1270 };
1271
1272 /*
1273 * 'dispc' class
1274 * display controller
1275 */
1276
1277 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1278 .rev_offs = 0x0000,
1279 .sysc_offs = 0x0010,
1280 .syss_offs = 0x0014,
1281 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1282 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1283 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1284 SYSS_HAS_RESET_STATUS),
1285 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1286 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1287 .sysc_fields = &omap_hwmod_sysc_type1,
1288 };
1289
1290 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1291 .name = "dispc",
1292 .sysc = &omap44xx_dispc_sysc,
1293 };
1294
1295 /* dss_dispc */
1296 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1297 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1298 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1299 { .irq = -1 }
1300 };
1301
1302 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1303 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1304 { .dma_req = -1 }
1305 };
1306
1307 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1308 {
1309 .pa_start = 0x58001000,
1310 .pa_end = 0x58001fff,
1311 .flags = ADDR_TYPE_RT
1312 },
1313 { }
1314 };
1315
1316 /* l3_main_2 -> dss_dispc */
1317 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1318 .master = &omap44xx_l3_main_2_hwmod,
1319 .slave = &omap44xx_dss_dispc_hwmod,
1320 .clk = "dss_fck",
1321 .addr = omap44xx_dss_dispc_dma_addrs,
1322 .user = OCP_USER_SDMA,
1323 };
1324
1325 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1326 {
1327 .pa_start = 0x48041000,
1328 .pa_end = 0x48041fff,
1329 .flags = ADDR_TYPE_RT
1330 },
1331 { }
1332 };
1333
1334 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
1335 .manager_count = 3,
1336 .has_framedonetv_irq = 1
1337 };
1338
1339 /* l4_per -> dss_dispc */
1340 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1341 .master = &omap44xx_l4_per_hwmod,
1342 .slave = &omap44xx_dss_dispc_hwmod,
1343 .clk = "l4_div_ck",
1344 .addr = omap44xx_dss_dispc_addrs,
1345 .user = OCP_USER_MPU,
1346 };
1347
1348 /* dss_dispc slave ports */
1349 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1350 &omap44xx_l3_main_2__dss_dispc,
1351 &omap44xx_l4_per__dss_dispc,
1352 };
1353
1354 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1355 .name = "dss_dispc",
1356 .class = &omap44xx_dispc_hwmod_class,
1357 .clkdm_name = "l3_dss_clkdm",
1358 .mpu_irqs = omap44xx_dss_dispc_irqs,
1359 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
1360 .main_clk = "dss_dss_clk",
1361 .prcm = {
1362 .omap4 = {
1363 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1364 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1365 },
1366 },
1367 .slaves = omap44xx_dss_dispc_slaves,
1368 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1369 .dev_attr = &omap44xx_dss_dispc_dev_attr
1370 };
1371
1372 /*
1373 * 'dsi' class
1374 * display serial interface controller
1375 */
1376
1377 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1378 .rev_offs = 0x0000,
1379 .sysc_offs = 0x0010,
1380 .syss_offs = 0x0014,
1381 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1382 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1383 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1384 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1385 .sysc_fields = &omap_hwmod_sysc_type1,
1386 };
1387
1388 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1389 .name = "dsi",
1390 .sysc = &omap44xx_dsi_sysc,
1391 };
1392
1393 /* dss_dsi1 */
1394 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1395 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1396 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1397 { .irq = -1 }
1398 };
1399
1400 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1401 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1402 { .dma_req = -1 }
1403 };
1404
1405 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1406 {
1407 .pa_start = 0x58004000,
1408 .pa_end = 0x580041ff,
1409 .flags = ADDR_TYPE_RT
1410 },
1411 { }
1412 };
1413
1414 /* l3_main_2 -> dss_dsi1 */
1415 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1416 .master = &omap44xx_l3_main_2_hwmod,
1417 .slave = &omap44xx_dss_dsi1_hwmod,
1418 .clk = "dss_fck",
1419 .addr = omap44xx_dss_dsi1_dma_addrs,
1420 .user = OCP_USER_SDMA,
1421 };
1422
1423 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1424 {
1425 .pa_start = 0x48044000,
1426 .pa_end = 0x480441ff,
1427 .flags = ADDR_TYPE_RT
1428 },
1429 { }
1430 };
1431
1432 /* l4_per -> dss_dsi1 */
1433 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1434 .master = &omap44xx_l4_per_hwmod,
1435 .slave = &omap44xx_dss_dsi1_hwmod,
1436 .clk = "l4_div_ck",
1437 .addr = omap44xx_dss_dsi1_addrs,
1438 .user = OCP_USER_MPU,
1439 };
1440
1441 /* dss_dsi1 slave ports */
1442 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1443 &omap44xx_l3_main_2__dss_dsi1,
1444 &omap44xx_l4_per__dss_dsi1,
1445 };
1446
1447 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1448 { .role = "sys_clk", .clk = "dss_sys_clk" },
1449 };
1450
1451 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1452 .name = "dss_dsi1",
1453 .class = &omap44xx_dsi_hwmod_class,
1454 .clkdm_name = "l3_dss_clkdm",
1455 .mpu_irqs = omap44xx_dss_dsi1_irqs,
1456 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
1457 .main_clk = "dss_dss_clk",
1458 .prcm = {
1459 .omap4 = {
1460 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1461 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1462 },
1463 },
1464 .opt_clks = dss_dsi1_opt_clks,
1465 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
1466 .slaves = omap44xx_dss_dsi1_slaves,
1467 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1468 };
1469
1470 /* dss_dsi2 */
1471 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1472 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1473 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1474 { .irq = -1 }
1475 };
1476
1477 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1478 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1479 { .dma_req = -1 }
1480 };
1481
1482 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1483 {
1484 .pa_start = 0x58005000,
1485 .pa_end = 0x580051ff,
1486 .flags = ADDR_TYPE_RT
1487 },
1488 { }
1489 };
1490
1491 /* l3_main_2 -> dss_dsi2 */
1492 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1493 .master = &omap44xx_l3_main_2_hwmod,
1494 .slave = &omap44xx_dss_dsi2_hwmod,
1495 .clk = "dss_fck",
1496 .addr = omap44xx_dss_dsi2_dma_addrs,
1497 .user = OCP_USER_SDMA,
1498 };
1499
1500 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1501 {
1502 .pa_start = 0x48045000,
1503 .pa_end = 0x480451ff,
1504 .flags = ADDR_TYPE_RT
1505 },
1506 { }
1507 };
1508
1509 /* l4_per -> dss_dsi2 */
1510 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1511 .master = &omap44xx_l4_per_hwmod,
1512 .slave = &omap44xx_dss_dsi2_hwmod,
1513 .clk = "l4_div_ck",
1514 .addr = omap44xx_dss_dsi2_addrs,
1515 .user = OCP_USER_MPU,
1516 };
1517
1518 /* dss_dsi2 slave ports */
1519 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1520 &omap44xx_l3_main_2__dss_dsi2,
1521 &omap44xx_l4_per__dss_dsi2,
1522 };
1523
1524 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1525 { .role = "sys_clk", .clk = "dss_sys_clk" },
1526 };
1527
1528 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1529 .name = "dss_dsi2",
1530 .class = &omap44xx_dsi_hwmod_class,
1531 .clkdm_name = "l3_dss_clkdm",
1532 .mpu_irqs = omap44xx_dss_dsi2_irqs,
1533 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
1534 .main_clk = "dss_dss_clk",
1535 .prcm = {
1536 .omap4 = {
1537 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1538 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1539 },
1540 },
1541 .opt_clks = dss_dsi2_opt_clks,
1542 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
1543 .slaves = omap44xx_dss_dsi2_slaves,
1544 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1545 };
1546
1547 /*
1548 * 'hdmi' class
1549 * hdmi controller
1550 */
1551
1552 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1553 .rev_offs = 0x0000,
1554 .sysc_offs = 0x0010,
1555 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1556 SYSC_HAS_SOFTRESET),
1557 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1558 SIDLE_SMART_WKUP),
1559 .sysc_fields = &omap_hwmod_sysc_type2,
1560 };
1561
1562 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1563 .name = "hdmi",
1564 .sysc = &omap44xx_hdmi_sysc,
1565 };
1566
1567 /* dss_hdmi */
1568 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1569 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1570 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1571 { .irq = -1 }
1572 };
1573
1574 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1575 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1576 { .dma_req = -1 }
1577 };
1578
1579 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1580 {
1581 .pa_start = 0x58006000,
1582 .pa_end = 0x58006fff,
1583 .flags = ADDR_TYPE_RT
1584 },
1585 { }
1586 };
1587
1588 /* l3_main_2 -> dss_hdmi */
1589 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1590 .master = &omap44xx_l3_main_2_hwmod,
1591 .slave = &omap44xx_dss_hdmi_hwmod,
1592 .clk = "dss_fck",
1593 .addr = omap44xx_dss_hdmi_dma_addrs,
1594 .user = OCP_USER_SDMA,
1595 };
1596
1597 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1598 {
1599 .pa_start = 0x48046000,
1600 .pa_end = 0x48046fff,
1601 .flags = ADDR_TYPE_RT
1602 },
1603 { }
1604 };
1605
1606 /* l4_per -> dss_hdmi */
1607 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1608 .master = &omap44xx_l4_per_hwmod,
1609 .slave = &omap44xx_dss_hdmi_hwmod,
1610 .clk = "l4_div_ck",
1611 .addr = omap44xx_dss_hdmi_addrs,
1612 .user = OCP_USER_MPU,
1613 };
1614
1615 /* dss_hdmi slave ports */
1616 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1617 &omap44xx_l3_main_2__dss_hdmi,
1618 &omap44xx_l4_per__dss_hdmi,
1619 };
1620
1621 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1622 { .role = "sys_clk", .clk = "dss_sys_clk" },
1623 };
1624
1625 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1626 .name = "dss_hdmi",
1627 .class = &omap44xx_hdmi_hwmod_class,
1628 .clkdm_name = "l3_dss_clkdm",
1629 .mpu_irqs = omap44xx_dss_hdmi_irqs,
1630 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
1631 .main_clk = "dss_48mhz_clk",
1632 .prcm = {
1633 .omap4 = {
1634 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1635 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1636 },
1637 },
1638 .opt_clks = dss_hdmi_opt_clks,
1639 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
1640 .slaves = omap44xx_dss_hdmi_slaves,
1641 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1642 };
1643
1644 /*
1645 * 'rfbi' class
1646 * remote frame buffer interface
1647 */
1648
1649 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1650 .rev_offs = 0x0000,
1651 .sysc_offs = 0x0010,
1652 .syss_offs = 0x0014,
1653 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1654 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1655 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1656 .sysc_fields = &omap_hwmod_sysc_type1,
1657 };
1658
1659 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1660 .name = "rfbi",
1661 .sysc = &omap44xx_rfbi_sysc,
1662 };
1663
1664 /* dss_rfbi */
1665 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1666 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1667 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1668 { .dma_req = -1 }
1669 };
1670
1671 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1672 {
1673 .pa_start = 0x58002000,
1674 .pa_end = 0x580020ff,
1675 .flags = ADDR_TYPE_RT
1676 },
1677 { }
1678 };
1679
1680 /* l3_main_2 -> dss_rfbi */
1681 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1682 .master = &omap44xx_l3_main_2_hwmod,
1683 .slave = &omap44xx_dss_rfbi_hwmod,
1684 .clk = "dss_fck",
1685 .addr = omap44xx_dss_rfbi_dma_addrs,
1686 .user = OCP_USER_SDMA,
1687 };
1688
1689 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1690 {
1691 .pa_start = 0x48042000,
1692 .pa_end = 0x480420ff,
1693 .flags = ADDR_TYPE_RT
1694 },
1695 { }
1696 };
1697
1698 /* l4_per -> dss_rfbi */
1699 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1700 .master = &omap44xx_l4_per_hwmod,
1701 .slave = &omap44xx_dss_rfbi_hwmod,
1702 .clk = "l4_div_ck",
1703 .addr = omap44xx_dss_rfbi_addrs,
1704 .user = OCP_USER_MPU,
1705 };
1706
1707 /* dss_rfbi slave ports */
1708 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1709 &omap44xx_l3_main_2__dss_rfbi,
1710 &omap44xx_l4_per__dss_rfbi,
1711 };
1712
1713 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1714 { .role = "ick", .clk = "dss_fck" },
1715 };
1716
1717 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1718 .name = "dss_rfbi",
1719 .class = &omap44xx_rfbi_hwmod_class,
1720 .clkdm_name = "l3_dss_clkdm",
1721 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
1722 .main_clk = "dss_dss_clk",
1723 .prcm = {
1724 .omap4 = {
1725 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1726 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1727 },
1728 },
1729 .opt_clks = dss_rfbi_opt_clks,
1730 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1731 .slaves = omap44xx_dss_rfbi_slaves,
1732 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1733 };
1734
1735 /*
1736 * 'venc' class
1737 * video encoder
1738 */
1739
1740 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1741 .name = "venc",
1742 };
1743
1744 /* dss_venc */
1745 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1746 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1747 {
1748 .pa_start = 0x58003000,
1749 .pa_end = 0x580030ff,
1750 .flags = ADDR_TYPE_RT
1751 },
1752 { }
1753 };
1754
1755 /* l3_main_2 -> dss_venc */
1756 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1757 .master = &omap44xx_l3_main_2_hwmod,
1758 .slave = &omap44xx_dss_venc_hwmod,
1759 .clk = "dss_fck",
1760 .addr = omap44xx_dss_venc_dma_addrs,
1761 .user = OCP_USER_SDMA,
1762 };
1763
1764 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1765 {
1766 .pa_start = 0x48043000,
1767 .pa_end = 0x480430ff,
1768 .flags = ADDR_TYPE_RT
1769 },
1770 { }
1771 };
1772
1773 /* l4_per -> dss_venc */
1774 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1775 .master = &omap44xx_l4_per_hwmod,
1776 .slave = &omap44xx_dss_venc_hwmod,
1777 .clk = "l4_div_ck",
1778 .addr = omap44xx_dss_venc_addrs,
1779 .user = OCP_USER_MPU,
1780 };
1781
1782 /* dss_venc slave ports */
1783 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1784 &omap44xx_l3_main_2__dss_venc,
1785 &omap44xx_l4_per__dss_venc,
1786 };
1787
1788 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1789 .name = "dss_venc",
1790 .class = &omap44xx_venc_hwmod_class,
1791 .clkdm_name = "l3_dss_clkdm",
1792 .main_clk = "dss_tv_clk",
1793 .prcm = {
1794 .omap4 = {
1795 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1796 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1797 },
1798 },
1799 .slaves = omap44xx_dss_venc_slaves,
1800 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1801 };
1802
1803 /*
1804 * 'gpio' class
1805 * general purpose io module
1806 */
1807
1808 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1809 .rev_offs = 0x0000,
1810 .sysc_offs = 0x0010,
1811 .syss_offs = 0x0114,
1812 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1813 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1814 SYSS_HAS_RESET_STATUS),
1815 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1816 SIDLE_SMART_WKUP),
1817 .sysc_fields = &omap_hwmod_sysc_type1,
1818 };
1819
1820 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1821 .name = "gpio",
1822 .sysc = &omap44xx_gpio_sysc,
1823 .rev = 2,
1824 };
1825
1826 /* gpio dev_attr */
1827 static struct omap_gpio_dev_attr gpio_dev_attr = {
1828 .bank_width = 32,
1829 .dbck_flag = true,
1830 };
1831
1832 /* gpio1 */
1833 static struct omap_hwmod omap44xx_gpio1_hwmod;
1834 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1835 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1836 { .irq = -1 }
1837 };
1838
1839 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1840 {
1841 .pa_start = 0x4a310000,
1842 .pa_end = 0x4a3101ff,
1843 .flags = ADDR_TYPE_RT
1844 },
1845 { }
1846 };
1847
1848 /* l4_wkup -> gpio1 */
1849 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1850 .master = &omap44xx_l4_wkup_hwmod,
1851 .slave = &omap44xx_gpio1_hwmod,
1852 .clk = "l4_wkup_clk_mux_ck",
1853 .addr = omap44xx_gpio1_addrs,
1854 .user = OCP_USER_MPU | OCP_USER_SDMA,
1855 };
1856
1857 /* gpio1 slave ports */
1858 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1859 &omap44xx_l4_wkup__gpio1,
1860 };
1861
1862 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1863 { .role = "dbclk", .clk = "gpio1_dbclk" },
1864 };
1865
1866 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1867 .name = "gpio1",
1868 .class = &omap44xx_gpio_hwmod_class,
1869 .clkdm_name = "l4_wkup_clkdm",
1870 .mpu_irqs = omap44xx_gpio1_irqs,
1871 .main_clk = "gpio1_ick",
1872 .prcm = {
1873 .omap4 = {
1874 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1875 .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1876 .modulemode = MODULEMODE_HWCTRL,
1877 },
1878 },
1879 .opt_clks = gpio1_opt_clks,
1880 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1881 .dev_attr = &gpio_dev_attr,
1882 .slaves = omap44xx_gpio1_slaves,
1883 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
1884 };
1885
1886 /* gpio2 */
1887 static struct omap_hwmod omap44xx_gpio2_hwmod;
1888 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1889 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1890 { .irq = -1 }
1891 };
1892
1893 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1894 {
1895 .pa_start = 0x48055000,
1896 .pa_end = 0x480551ff,
1897 .flags = ADDR_TYPE_RT
1898 },
1899 { }
1900 };
1901
1902 /* l4_per -> gpio2 */
1903 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1904 .master = &omap44xx_l4_per_hwmod,
1905 .slave = &omap44xx_gpio2_hwmod,
1906 .clk = "l4_div_ck",
1907 .addr = omap44xx_gpio2_addrs,
1908 .user = OCP_USER_MPU | OCP_USER_SDMA,
1909 };
1910
1911 /* gpio2 slave ports */
1912 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1913 &omap44xx_l4_per__gpio2,
1914 };
1915
1916 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1917 { .role = "dbclk", .clk = "gpio2_dbclk" },
1918 };
1919
1920 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1921 .name = "gpio2",
1922 .class = &omap44xx_gpio_hwmod_class,
1923 .clkdm_name = "l4_per_clkdm",
1924 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1925 .mpu_irqs = omap44xx_gpio2_irqs,
1926 .main_clk = "gpio2_ick",
1927 .prcm = {
1928 .omap4 = {
1929 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1930 .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1931 .modulemode = MODULEMODE_HWCTRL,
1932 },
1933 },
1934 .opt_clks = gpio2_opt_clks,
1935 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1936 .dev_attr = &gpio_dev_attr,
1937 .slaves = omap44xx_gpio2_slaves,
1938 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
1939 };
1940
1941 /* gpio3 */
1942 static struct omap_hwmod omap44xx_gpio3_hwmod;
1943 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1944 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1945 { .irq = -1 }
1946 };
1947
1948 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1949 {
1950 .pa_start = 0x48057000,
1951 .pa_end = 0x480571ff,
1952 .flags = ADDR_TYPE_RT
1953 },
1954 { }
1955 };
1956
1957 /* l4_per -> gpio3 */
1958 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1959 .master = &omap44xx_l4_per_hwmod,
1960 .slave = &omap44xx_gpio3_hwmod,
1961 .clk = "l4_div_ck",
1962 .addr = omap44xx_gpio3_addrs,
1963 .user = OCP_USER_MPU | OCP_USER_SDMA,
1964 };
1965
1966 /* gpio3 slave ports */
1967 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1968 &omap44xx_l4_per__gpio3,
1969 };
1970
1971 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1972 { .role = "dbclk", .clk = "gpio3_dbclk" },
1973 };
1974
1975 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1976 .name = "gpio3",
1977 .class = &omap44xx_gpio_hwmod_class,
1978 .clkdm_name = "l4_per_clkdm",
1979 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1980 .mpu_irqs = omap44xx_gpio3_irqs,
1981 .main_clk = "gpio3_ick",
1982 .prcm = {
1983 .omap4 = {
1984 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1985 .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1986 .modulemode = MODULEMODE_HWCTRL,
1987 },
1988 },
1989 .opt_clks = gpio3_opt_clks,
1990 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1991 .dev_attr = &gpio_dev_attr,
1992 .slaves = omap44xx_gpio3_slaves,
1993 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
1994 };
1995
1996 /* gpio4 */
1997 static struct omap_hwmod omap44xx_gpio4_hwmod;
1998 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1999 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
2000 { .irq = -1 }
2001 };
2002
2003 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
2004 {
2005 .pa_start = 0x48059000,
2006 .pa_end = 0x480591ff,
2007 .flags = ADDR_TYPE_RT
2008 },
2009 { }
2010 };
2011
2012 /* l4_per -> gpio4 */
2013 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
2014 .master = &omap44xx_l4_per_hwmod,
2015 .slave = &omap44xx_gpio4_hwmod,
2016 .clk = "l4_div_ck",
2017 .addr = omap44xx_gpio4_addrs,
2018 .user = OCP_USER_MPU | OCP_USER_SDMA,
2019 };
2020
2021 /* gpio4 slave ports */
2022 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
2023 &omap44xx_l4_per__gpio4,
2024 };
2025
2026 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2027 { .role = "dbclk", .clk = "gpio4_dbclk" },
2028 };
2029
2030 static struct omap_hwmod omap44xx_gpio4_hwmod = {
2031 .name = "gpio4",
2032 .class = &omap44xx_gpio_hwmod_class,
2033 .clkdm_name = "l4_per_clkdm",
2034 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2035 .mpu_irqs = omap44xx_gpio4_irqs,
2036 .main_clk = "gpio4_ick",
2037 .prcm = {
2038 .omap4 = {
2039 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
2040 .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
2041 .modulemode = MODULEMODE_HWCTRL,
2042 },
2043 },
2044 .opt_clks = gpio4_opt_clks,
2045 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
2046 .dev_attr = &gpio_dev_attr,
2047 .slaves = omap44xx_gpio4_slaves,
2048 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
2049 };
2050
2051 /* gpio5 */
2052 static struct omap_hwmod omap44xx_gpio5_hwmod;
2053 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
2054 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
2055 { .irq = -1 }
2056 };
2057
2058 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
2059 {
2060 .pa_start = 0x4805b000,
2061 .pa_end = 0x4805b1ff,
2062 .flags = ADDR_TYPE_RT
2063 },
2064 { }
2065 };
2066
2067 /* l4_per -> gpio5 */
2068 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
2069 .master = &omap44xx_l4_per_hwmod,
2070 .slave = &omap44xx_gpio5_hwmod,
2071 .clk = "l4_div_ck",
2072 .addr = omap44xx_gpio5_addrs,
2073 .user = OCP_USER_MPU | OCP_USER_SDMA,
2074 };
2075
2076 /* gpio5 slave ports */
2077 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
2078 &omap44xx_l4_per__gpio5,
2079 };
2080
2081 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2082 { .role = "dbclk", .clk = "gpio5_dbclk" },
2083 };
2084
2085 static struct omap_hwmod omap44xx_gpio5_hwmod = {
2086 .name = "gpio5",
2087 .class = &omap44xx_gpio_hwmod_class,
2088 .clkdm_name = "l4_per_clkdm",
2089 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2090 .mpu_irqs = omap44xx_gpio5_irqs,
2091 .main_clk = "gpio5_ick",
2092 .prcm = {
2093 .omap4 = {
2094 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
2095 .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
2096 .modulemode = MODULEMODE_HWCTRL,
2097 },
2098 },
2099 .opt_clks = gpio5_opt_clks,
2100 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2101 .dev_attr = &gpio_dev_attr,
2102 .slaves = omap44xx_gpio5_slaves,
2103 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
2104 };
2105
2106 /* gpio6 */
2107 static struct omap_hwmod omap44xx_gpio6_hwmod;
2108 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2109 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
2110 { .irq = -1 }
2111 };
2112
2113 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
2114 {
2115 .pa_start = 0x4805d000,
2116 .pa_end = 0x4805d1ff,
2117 .flags = ADDR_TYPE_RT
2118 },
2119 { }
2120 };
2121
2122 /* l4_per -> gpio6 */
2123 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2124 .master = &omap44xx_l4_per_hwmod,
2125 .slave = &omap44xx_gpio6_hwmod,
2126 .clk = "l4_div_ck",
2127 .addr = omap44xx_gpio6_addrs,
2128 .user = OCP_USER_MPU | OCP_USER_SDMA,
2129 };
2130
2131 /* gpio6 slave ports */
2132 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2133 &omap44xx_l4_per__gpio6,
2134 };
2135
2136 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2137 { .role = "dbclk", .clk = "gpio6_dbclk" },
2138 };
2139
2140 static struct omap_hwmod omap44xx_gpio6_hwmod = {
2141 .name = "gpio6",
2142 .class = &omap44xx_gpio_hwmod_class,
2143 .clkdm_name = "l4_per_clkdm",
2144 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2145 .mpu_irqs = omap44xx_gpio6_irqs,
2146 .main_clk = "gpio6_ick",
2147 .prcm = {
2148 .omap4 = {
2149 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
2150 .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
2151 .modulemode = MODULEMODE_HWCTRL,
2152 },
2153 },
2154 .opt_clks = gpio6_opt_clks,
2155 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2156 .dev_attr = &gpio_dev_attr,
2157 .slaves = omap44xx_gpio6_slaves,
2158 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
2159 };
2160
2161 /*
2162 * 'hsi' class
2163 * mipi high-speed synchronous serial interface (multichannel and full-duplex
2164 * serial if)
2165 */
2166
2167 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2168 .rev_offs = 0x0000,
2169 .sysc_offs = 0x0010,
2170 .syss_offs = 0x0014,
2171 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2172 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2173 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2174 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2175 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2176 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2177 .sysc_fields = &omap_hwmod_sysc_type1,
2178 };
2179
2180 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2181 .name = "hsi",
2182 .sysc = &omap44xx_hsi_sysc,
2183 };
2184
2185 /* hsi */
2186 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2187 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2188 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2189 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2190 { .irq = -1 }
2191 };
2192
2193 /* hsi master ports */
2194 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2195 &omap44xx_hsi__l3_main_2,
2196 };
2197
2198 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2199 {
2200 .pa_start = 0x4a058000,
2201 .pa_end = 0x4a05bfff,
2202 .flags = ADDR_TYPE_RT
2203 },
2204 { }
2205 };
2206
2207 /* l4_cfg -> hsi */
2208 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2209 .master = &omap44xx_l4_cfg_hwmod,
2210 .slave = &omap44xx_hsi_hwmod,
2211 .clk = "l4_div_ck",
2212 .addr = omap44xx_hsi_addrs,
2213 .user = OCP_USER_MPU | OCP_USER_SDMA,
2214 };
2215
2216 /* hsi slave ports */
2217 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2218 &omap44xx_l4_cfg__hsi,
2219 };
2220
2221 static struct omap_hwmod omap44xx_hsi_hwmod = {
2222 .name = "hsi",
2223 .class = &omap44xx_hsi_hwmod_class,
2224 .clkdm_name = "l3_init_clkdm",
2225 .mpu_irqs = omap44xx_hsi_irqs,
2226 .main_clk = "hsi_fck",
2227 .prcm = {
2228 .omap4 = {
2229 .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
2230 .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
2231 .modulemode = MODULEMODE_HWCTRL,
2232 },
2233 },
2234 .slaves = omap44xx_hsi_slaves,
2235 .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves),
2236 .masters = omap44xx_hsi_masters,
2237 .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters),
2238 };
2239
2240 /*
2241 * 'i2c' class
2242 * multimaster high-speed i2c controller
2243 */
2244
2245 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2246 .sysc_offs = 0x0010,
2247 .syss_offs = 0x0090,
2248 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2249 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2250 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2251 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2252 SIDLE_SMART_WKUP),
2253 .clockact = CLOCKACT_TEST_ICLK,
2254 .sysc_fields = &omap_hwmod_sysc_type1,
2255 };
2256
2257 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2258 .name = "i2c",
2259 .sysc = &omap44xx_i2c_sysc,
2260 .rev = OMAP_I2C_IP_VERSION_2,
2261 .reset = &omap_i2c_reset,
2262 };
2263
2264 static struct omap_i2c_dev_attr i2c_dev_attr = {
2265 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
2266 };
2267
2268 /* i2c1 */
2269 static struct omap_hwmod omap44xx_i2c1_hwmod;
2270 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2271 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2272 { .irq = -1 }
2273 };
2274
2275 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2276 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2277 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2278 { .dma_req = -1 }
2279 };
2280
2281 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2282 {
2283 .pa_start = 0x48070000,
2284 .pa_end = 0x480700ff,
2285 .flags = ADDR_TYPE_RT
2286 },
2287 { }
2288 };
2289
2290 /* l4_per -> i2c1 */
2291 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2292 .master = &omap44xx_l4_per_hwmod,
2293 .slave = &omap44xx_i2c1_hwmod,
2294 .clk = "l4_div_ck",
2295 .addr = omap44xx_i2c1_addrs,
2296 .user = OCP_USER_MPU | OCP_USER_SDMA,
2297 };
2298
2299 /* i2c1 slave ports */
2300 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2301 &omap44xx_l4_per__i2c1,
2302 };
2303
2304 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2305 .name = "i2c1",
2306 .class = &omap44xx_i2c_hwmod_class,
2307 .clkdm_name = "l4_per_clkdm",
2308 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2309 .mpu_irqs = omap44xx_i2c1_irqs,
2310 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
2311 .main_clk = "i2c1_fck",
2312 .prcm = {
2313 .omap4 = {
2314 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
2315 .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
2316 .modulemode = MODULEMODE_SWCTRL,
2317 },
2318 },
2319 .slaves = omap44xx_i2c1_slaves,
2320 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
2321 .dev_attr = &i2c_dev_attr,
2322 };
2323
2324 /* i2c2 */
2325 static struct omap_hwmod omap44xx_i2c2_hwmod;
2326 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2327 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2328 { .irq = -1 }
2329 };
2330
2331 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2332 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2333 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2334 { .dma_req = -1 }
2335 };
2336
2337 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2338 {
2339 .pa_start = 0x48072000,
2340 .pa_end = 0x480720ff,
2341 .flags = ADDR_TYPE_RT
2342 },
2343 { }
2344 };
2345
2346 /* l4_per -> i2c2 */
2347 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2348 .master = &omap44xx_l4_per_hwmod,
2349 .slave = &omap44xx_i2c2_hwmod,
2350 .clk = "l4_div_ck",
2351 .addr = omap44xx_i2c2_addrs,
2352 .user = OCP_USER_MPU | OCP_USER_SDMA,
2353 };
2354
2355 /* i2c2 slave ports */
2356 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2357 &omap44xx_l4_per__i2c2,
2358 };
2359
2360 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2361 .name = "i2c2",
2362 .class = &omap44xx_i2c_hwmod_class,
2363 .clkdm_name = "l4_per_clkdm",
2364 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2365 .mpu_irqs = omap44xx_i2c2_irqs,
2366 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
2367 .main_clk = "i2c2_fck",
2368 .prcm = {
2369 .omap4 = {
2370 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
2371 .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
2372 .modulemode = MODULEMODE_SWCTRL,
2373 },
2374 },
2375 .slaves = omap44xx_i2c2_slaves,
2376 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
2377 .dev_attr = &i2c_dev_attr,
2378 };
2379
2380 /* i2c3 */
2381 static struct omap_hwmod omap44xx_i2c3_hwmod;
2382 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2383 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2384 { .irq = -1 }
2385 };
2386
2387 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2388 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2389 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2390 { .dma_req = -1 }
2391 };
2392
2393 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2394 {
2395 .pa_start = 0x48060000,
2396 .pa_end = 0x480600ff,
2397 .flags = ADDR_TYPE_RT
2398 },
2399 { }
2400 };
2401
2402 /* l4_per -> i2c3 */
2403 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2404 .master = &omap44xx_l4_per_hwmod,
2405 .slave = &omap44xx_i2c3_hwmod,
2406 .clk = "l4_div_ck",
2407 .addr = omap44xx_i2c3_addrs,
2408 .user = OCP_USER_MPU | OCP_USER_SDMA,
2409 };
2410
2411 /* i2c3 slave ports */
2412 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2413 &omap44xx_l4_per__i2c3,
2414 };
2415
2416 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2417 .name = "i2c3",
2418 .class = &omap44xx_i2c_hwmod_class,
2419 .clkdm_name = "l4_per_clkdm",
2420 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2421 .mpu_irqs = omap44xx_i2c3_irqs,
2422 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
2423 .main_clk = "i2c3_fck",
2424 .prcm = {
2425 .omap4 = {
2426 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
2427 .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
2428 .modulemode = MODULEMODE_SWCTRL,
2429 },
2430 },
2431 .slaves = omap44xx_i2c3_slaves,
2432 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
2433 .dev_attr = &i2c_dev_attr,
2434 };
2435
2436 /* i2c4 */
2437 static struct omap_hwmod omap44xx_i2c4_hwmod;
2438 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2439 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2440 { .irq = -1 }
2441 };
2442
2443 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2444 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2445 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2446 { .dma_req = -1 }
2447 };
2448
2449 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2450 {
2451 .pa_start = 0x48350000,
2452 .pa_end = 0x483500ff,
2453 .flags = ADDR_TYPE_RT
2454 },
2455 { }
2456 };
2457
2458 /* l4_per -> i2c4 */
2459 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2460 .master = &omap44xx_l4_per_hwmod,
2461 .slave = &omap44xx_i2c4_hwmod,
2462 .clk = "l4_div_ck",
2463 .addr = omap44xx_i2c4_addrs,
2464 .user = OCP_USER_MPU | OCP_USER_SDMA,
2465 };
2466
2467 /* i2c4 slave ports */
2468 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2469 &omap44xx_l4_per__i2c4,
2470 };
2471
2472 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2473 .name = "i2c4",
2474 .class = &omap44xx_i2c_hwmod_class,
2475 .clkdm_name = "l4_per_clkdm",
2476 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2477 .mpu_irqs = omap44xx_i2c4_irqs,
2478 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
2479 .main_clk = "i2c4_fck",
2480 .prcm = {
2481 .omap4 = {
2482 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
2483 .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
2484 .modulemode = MODULEMODE_SWCTRL,
2485 },
2486 },
2487 .slaves = omap44xx_i2c4_slaves,
2488 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
2489 .dev_attr = &i2c_dev_attr,
2490 };
2491
2492 /*
2493 * 'ipu' class
2494 * imaging processor unit
2495 */
2496
2497 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2498 .name = "ipu",
2499 };
2500
2501 /* ipu */
2502 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2503 { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2504 { .irq = -1 }
2505 };
2506
2507 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2508 { .name = "cpu0", .rst_shift = 0 },
2509 };
2510
2511 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2512 { .name = "cpu1", .rst_shift = 1 },
2513 };
2514
2515 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2516 { .name = "mmu_cache", .rst_shift = 2 },
2517 };
2518
2519 /* ipu master ports */
2520 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2521 &omap44xx_ipu__l3_main_2,
2522 };
2523
2524 /* l3_main_2 -> ipu */
2525 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2526 .master = &omap44xx_l3_main_2_hwmod,
2527 .slave = &omap44xx_ipu_hwmod,
2528 .clk = "l3_div_ck",
2529 .user = OCP_USER_MPU | OCP_USER_SDMA,
2530 };
2531
2532 /* ipu slave ports */
2533 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2534 &omap44xx_l3_main_2__ipu,
2535 };
2536
2537 /* Pseudo hwmod for reset control purpose only */
2538 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2539 .name = "ipu_c0",
2540 .class = &omap44xx_ipu_hwmod_class,
2541 .clkdm_name = "ducati_clkdm",
2542 .flags = HWMOD_INIT_NO_RESET,
2543 .rst_lines = omap44xx_ipu_c0_resets,
2544 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2545 .prcm = {
2546 .omap4 = {
2547 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2548 },
2549 },
2550 };
2551
2552 /* Pseudo hwmod for reset control purpose only */
2553 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2554 .name = "ipu_c1",
2555 .class = &omap44xx_ipu_hwmod_class,
2556 .clkdm_name = "ducati_clkdm",
2557 .flags = HWMOD_INIT_NO_RESET,
2558 .rst_lines = omap44xx_ipu_c1_resets,
2559 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2560 .prcm = {
2561 .omap4 = {
2562 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2563 },
2564 },
2565 };
2566
2567 static struct omap_hwmod omap44xx_ipu_hwmod = {
2568 .name = "ipu",
2569 .class = &omap44xx_ipu_hwmod_class,
2570 .clkdm_name = "ducati_clkdm",
2571 .mpu_irqs = omap44xx_ipu_irqs,
2572 .rst_lines = omap44xx_ipu_resets,
2573 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
2574 .main_clk = "ipu_fck",
2575 .prcm = {
2576 .omap4 = {
2577 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2578 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2579 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2580 .modulemode = MODULEMODE_HWCTRL,
2581 },
2582 },
2583 .slaves = omap44xx_ipu_slaves,
2584 .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves),
2585 .masters = omap44xx_ipu_masters,
2586 .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters),
2587 };
2588
2589 /*
2590 * 'iss' class
2591 * external images sensor pixel data processor
2592 */
2593
2594 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2595 .rev_offs = 0x0000,
2596 .sysc_offs = 0x0010,
2597 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2598 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2599 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2600 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2601 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2602 .sysc_fields = &omap_hwmod_sysc_type2,
2603 };
2604
2605 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2606 .name = "iss",
2607 .sysc = &omap44xx_iss_sysc,
2608 };
2609
2610 /* iss */
2611 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2612 { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2613 { .irq = -1 }
2614 };
2615
2616 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2617 { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2618 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2619 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2620 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2621 { .dma_req = -1 }
2622 };
2623
2624 /* iss master ports */
2625 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2626 &omap44xx_iss__l3_main_2,
2627 };
2628
2629 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2630 {
2631 .pa_start = 0x52000000,
2632 .pa_end = 0x520000ff,
2633 .flags = ADDR_TYPE_RT
2634 },
2635 { }
2636 };
2637
2638 /* l3_main_2 -> iss */
2639 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2640 .master = &omap44xx_l3_main_2_hwmod,
2641 .slave = &omap44xx_iss_hwmod,
2642 .clk = "l3_div_ck",
2643 .addr = omap44xx_iss_addrs,
2644 .user = OCP_USER_MPU | OCP_USER_SDMA,
2645 };
2646
2647 /* iss slave ports */
2648 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2649 &omap44xx_l3_main_2__iss,
2650 };
2651
2652 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2653 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2654 };
2655
2656 static struct omap_hwmod omap44xx_iss_hwmod = {
2657 .name = "iss",
2658 .class = &omap44xx_iss_hwmod_class,
2659 .clkdm_name = "iss_clkdm",
2660 .mpu_irqs = omap44xx_iss_irqs,
2661 .sdma_reqs = omap44xx_iss_sdma_reqs,
2662 .main_clk = "iss_fck",
2663 .prcm = {
2664 .omap4 = {
2665 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
2666 .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
2667 .modulemode = MODULEMODE_SWCTRL,
2668 },
2669 },
2670 .opt_clks = iss_opt_clks,
2671 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
2672 .slaves = omap44xx_iss_slaves,
2673 .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves),
2674 .masters = omap44xx_iss_masters,
2675 .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters),
2676 };
2677
2678 /*
2679 * 'iva' class
2680 * multi-standard video encoder/decoder hardware accelerator
2681 */
2682
2683 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2684 .name = "iva",
2685 };
2686
2687 /* iva */
2688 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2689 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2690 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2691 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2692 { .irq = -1 }
2693 };
2694
2695 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2696 { .name = "logic", .rst_shift = 2 },
2697 };
2698
2699 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2700 { .name = "seq0", .rst_shift = 0 },
2701 };
2702
2703 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2704 { .name = "seq1", .rst_shift = 1 },
2705 };
2706
2707 /* iva master ports */
2708 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2709 &omap44xx_iva__l3_main_2,
2710 &omap44xx_iva__l3_instr,
2711 };
2712
2713 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2714 {
2715 .pa_start = 0x5a000000,
2716 .pa_end = 0x5a07ffff,
2717 .flags = ADDR_TYPE_RT
2718 },
2719 { }
2720 };
2721
2722 /* l3_main_2 -> iva */
2723 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2724 .master = &omap44xx_l3_main_2_hwmod,
2725 .slave = &omap44xx_iva_hwmod,
2726 .clk = "l3_div_ck",
2727 .addr = omap44xx_iva_addrs,
2728 .user = OCP_USER_MPU,
2729 };
2730
2731 /* iva slave ports */
2732 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2733 &omap44xx_dsp__iva,
2734 &omap44xx_l3_main_2__iva,
2735 };
2736
2737 /* Pseudo hwmod for reset control purpose only */
2738 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2739 .name = "iva_seq0",
2740 .class = &omap44xx_iva_hwmod_class,
2741 .clkdm_name = "ivahd_clkdm",
2742 .flags = HWMOD_INIT_NO_RESET,
2743 .rst_lines = omap44xx_iva_seq0_resets,
2744 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2745 .prcm = {
2746 .omap4 = {
2747 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2748 },
2749 },
2750 };
2751
2752 /* Pseudo hwmod for reset control purpose only */
2753 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2754 .name = "iva_seq1",
2755 .class = &omap44xx_iva_hwmod_class,
2756 .clkdm_name = "ivahd_clkdm",
2757 .flags = HWMOD_INIT_NO_RESET,
2758 .rst_lines = omap44xx_iva_seq1_resets,
2759 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2760 .prcm = {
2761 .omap4 = {
2762 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2763 },
2764 },
2765 };
2766
2767 static struct omap_hwmod omap44xx_iva_hwmod = {
2768 .name = "iva",
2769 .class = &omap44xx_iva_hwmod_class,
2770 .clkdm_name = "ivahd_clkdm",
2771 .mpu_irqs = omap44xx_iva_irqs,
2772 .rst_lines = omap44xx_iva_resets,
2773 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
2774 .main_clk = "iva_fck",
2775 .prcm = {
2776 .omap4 = {
2777 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
2778 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2779 .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
2780 .modulemode = MODULEMODE_HWCTRL,
2781 },
2782 },
2783 .slaves = omap44xx_iva_slaves,
2784 .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves),
2785 .masters = omap44xx_iva_masters,
2786 .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters),
2787 };
2788
2789 /*
2790 * 'kbd' class
2791 * keyboard controller
2792 */
2793
2794 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2795 .rev_offs = 0x0000,
2796 .sysc_offs = 0x0010,
2797 .syss_offs = 0x0014,
2798 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2799 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2800 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2801 SYSS_HAS_RESET_STATUS),
2802 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2803 .sysc_fields = &omap_hwmod_sysc_type1,
2804 };
2805
2806 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2807 .name = "kbd",
2808 .sysc = &omap44xx_kbd_sysc,
2809 };
2810
2811 /* kbd */
2812 static struct omap_hwmod omap44xx_kbd_hwmod;
2813 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2814 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2815 { .irq = -1 }
2816 };
2817
2818 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2819 {
2820 .pa_start = 0x4a31c000,
2821 .pa_end = 0x4a31c07f,
2822 .flags = ADDR_TYPE_RT
2823 },
2824 { }
2825 };
2826
2827 /* l4_wkup -> kbd */
2828 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2829 .master = &omap44xx_l4_wkup_hwmod,
2830 .slave = &omap44xx_kbd_hwmod,
2831 .clk = "l4_wkup_clk_mux_ck",
2832 .addr = omap44xx_kbd_addrs,
2833 .user = OCP_USER_MPU | OCP_USER_SDMA,
2834 };
2835
2836 /* kbd slave ports */
2837 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2838 &omap44xx_l4_wkup__kbd,
2839 };
2840
2841 static struct omap_hwmod omap44xx_kbd_hwmod = {
2842 .name = "kbd",
2843 .class = &omap44xx_kbd_hwmod_class,
2844 .clkdm_name = "l4_wkup_clkdm",
2845 .mpu_irqs = omap44xx_kbd_irqs,
2846 .main_clk = "kbd_fck",
2847 .prcm = {
2848 .omap4 = {
2849 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
2850 .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
2851 .modulemode = MODULEMODE_SWCTRL,
2852 },
2853 },
2854 .slaves = omap44xx_kbd_slaves,
2855 .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves),
2856 };
2857
2858 /*
2859 * 'mailbox' class
2860 * mailbox module allowing communication between the on-chip processors using a
2861 * queued mailbox-interrupt mechanism.
2862 */
2863
2864 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2865 .rev_offs = 0x0000,
2866 .sysc_offs = 0x0010,
2867 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2868 SYSC_HAS_SOFTRESET),
2869 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2870 .sysc_fields = &omap_hwmod_sysc_type2,
2871 };
2872
2873 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2874 .name = "mailbox",
2875 .sysc = &omap44xx_mailbox_sysc,
2876 };
2877
2878 /* mailbox */
2879 static struct omap_hwmod omap44xx_mailbox_hwmod;
2880 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2881 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2882 { .irq = -1 }
2883 };
2884
2885 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2886 {
2887 .pa_start = 0x4a0f4000,
2888 .pa_end = 0x4a0f41ff,
2889 .flags = ADDR_TYPE_RT
2890 },
2891 { }
2892 };
2893
2894 /* l4_cfg -> mailbox */
2895 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2896 .master = &omap44xx_l4_cfg_hwmod,
2897 .slave = &omap44xx_mailbox_hwmod,
2898 .clk = "l4_div_ck",
2899 .addr = omap44xx_mailbox_addrs,
2900 .user = OCP_USER_MPU | OCP_USER_SDMA,
2901 };
2902
2903 /* mailbox slave ports */
2904 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2905 &omap44xx_l4_cfg__mailbox,
2906 };
2907
2908 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2909 .name = "mailbox",
2910 .class = &omap44xx_mailbox_hwmod_class,
2911 .clkdm_name = "l4_cfg_clkdm",
2912 .mpu_irqs = omap44xx_mailbox_irqs,
2913 .prcm = {
2914 .omap4 = {
2915 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
2916 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
2917 },
2918 },
2919 .slaves = omap44xx_mailbox_slaves,
2920 .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
2921 };
2922
2923 /*
2924 * 'mcbsp' class
2925 * multi channel buffered serial port controller
2926 */
2927
2928 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2929 .sysc_offs = 0x008c,
2930 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2931 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2932 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2933 .sysc_fields = &omap_hwmod_sysc_type1,
2934 };
2935
2936 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2937 .name = "mcbsp",
2938 .sysc = &omap44xx_mcbsp_sysc,
2939 .rev = MCBSP_CONFIG_TYPE4,
2940 };
2941
2942 /* mcbsp1 */
2943 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2944 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2945 { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2946 { .irq = -1 }
2947 };
2948
2949 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2950 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2951 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2952 { .dma_req = -1 }
2953 };
2954
2955 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2956 {
2957 .name = "mpu",
2958 .pa_start = 0x40122000,
2959 .pa_end = 0x401220ff,
2960 .flags = ADDR_TYPE_RT
2961 },
2962 { }
2963 };
2964
2965 /* l4_abe -> mcbsp1 */
2966 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2967 .master = &omap44xx_l4_abe_hwmod,
2968 .slave = &omap44xx_mcbsp1_hwmod,
2969 .clk = "ocp_abe_iclk",
2970 .addr = omap44xx_mcbsp1_addrs,
2971 .user = OCP_USER_MPU,
2972 };
2973
2974 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2975 {
2976 .name = "dma",
2977 .pa_start = 0x49022000,
2978 .pa_end = 0x490220ff,
2979 .flags = ADDR_TYPE_RT
2980 },
2981 { }
2982 };
2983
2984 /* l4_abe -> mcbsp1 (dma) */
2985 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2986 .master = &omap44xx_l4_abe_hwmod,
2987 .slave = &omap44xx_mcbsp1_hwmod,
2988 .clk = "ocp_abe_iclk",
2989 .addr = omap44xx_mcbsp1_dma_addrs,
2990 .user = OCP_USER_SDMA,
2991 };
2992
2993 /* mcbsp1 slave ports */
2994 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2995 &omap44xx_l4_abe__mcbsp1,
2996 &omap44xx_l4_abe__mcbsp1_dma,
2997 };
2998
2999 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
3000 .name = "mcbsp1",
3001 .class = &omap44xx_mcbsp_hwmod_class,
3002 .clkdm_name = "abe_clkdm",
3003 .mpu_irqs = omap44xx_mcbsp1_irqs,
3004 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
3005 .main_clk = "mcbsp1_fck",
3006 .prcm = {
3007 .omap4 = {
3008 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
3009 .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
3010 .modulemode = MODULEMODE_SWCTRL,
3011 },
3012 },
3013 .slaves = omap44xx_mcbsp1_slaves,
3014 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
3015 };
3016
3017 /* mcbsp2 */
3018 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
3019 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
3020 { .irq = 22 + OMAP44XX_IRQ_GIC_START },
3021 { .irq = -1 }
3022 };
3023
3024 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
3025 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
3026 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
3027 { .dma_req = -1 }
3028 };
3029
3030 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
3031 {
3032 .name = "mpu",
3033 .pa_start = 0x40124000,
3034 .pa_end = 0x401240ff,
3035 .flags = ADDR_TYPE_RT
3036 },
3037 { }
3038 };
3039
3040 /* l4_abe -> mcbsp2 */
3041 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
3042 .master = &omap44xx_l4_abe_hwmod,
3043 .slave = &omap44xx_mcbsp2_hwmod,
3044 .clk = "ocp_abe_iclk",
3045 .addr = omap44xx_mcbsp2_addrs,
3046 .user = OCP_USER_MPU,
3047 };
3048
3049 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
3050 {
3051 .name = "dma",
3052 .pa_start = 0x49024000,
3053 .pa_end = 0x490240ff,
3054 .flags = ADDR_TYPE_RT
3055 },
3056 { }
3057 };
3058
3059 /* l4_abe -> mcbsp2 (dma) */
3060 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
3061 .master = &omap44xx_l4_abe_hwmod,
3062 .slave = &omap44xx_mcbsp2_hwmod,
3063 .clk = "ocp_abe_iclk",
3064 .addr = omap44xx_mcbsp2_dma_addrs,
3065 .user = OCP_USER_SDMA,
3066 };
3067
3068 /* mcbsp2 slave ports */
3069 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
3070 &omap44xx_l4_abe__mcbsp2,
3071 &omap44xx_l4_abe__mcbsp2_dma,
3072 };
3073
3074 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
3075 .name = "mcbsp2",
3076 .class = &omap44xx_mcbsp_hwmod_class,
3077 .clkdm_name = "abe_clkdm",
3078 .mpu_irqs = omap44xx_mcbsp2_irqs,
3079 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
3080 .main_clk = "mcbsp2_fck",
3081 .prcm = {
3082 .omap4 = {
3083 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
3084 .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
3085 .modulemode = MODULEMODE_SWCTRL,
3086 },
3087 },
3088 .slaves = omap44xx_mcbsp2_slaves,
3089 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
3090 };
3091
3092 /* mcbsp3 */
3093 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
3094 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
3095 { .irq = 23 + OMAP44XX_IRQ_GIC_START },
3096 { .irq = -1 }
3097 };
3098
3099 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
3100 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
3101 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
3102 { .dma_req = -1 }
3103 };
3104
3105 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
3106 {
3107 .name = "mpu",
3108 .pa_start = 0x40126000,
3109 .pa_end = 0x401260ff,
3110 .flags = ADDR_TYPE_RT
3111 },
3112 { }
3113 };
3114
3115 /* l4_abe -> mcbsp3 */
3116 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3117 .master = &omap44xx_l4_abe_hwmod,
3118 .slave = &omap44xx_mcbsp3_hwmod,
3119 .clk = "ocp_abe_iclk",
3120 .addr = omap44xx_mcbsp3_addrs,
3121 .user = OCP_USER_MPU,
3122 };
3123
3124 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
3125 {
3126 .name = "dma",
3127 .pa_start = 0x49026000,
3128 .pa_end = 0x490260ff,
3129 .flags = ADDR_TYPE_RT
3130 },
3131 { }
3132 };
3133
3134 /* l4_abe -> mcbsp3 (dma) */
3135 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
3136 .master = &omap44xx_l4_abe_hwmod,
3137 .slave = &omap44xx_mcbsp3_hwmod,
3138 .clk = "ocp_abe_iclk",
3139 .addr = omap44xx_mcbsp3_dma_addrs,
3140 .user = OCP_USER_SDMA,
3141 };
3142
3143 /* mcbsp3 slave ports */
3144 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
3145 &omap44xx_l4_abe__mcbsp3,
3146 &omap44xx_l4_abe__mcbsp3_dma,
3147 };
3148
3149 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3150 .name = "mcbsp3",
3151 .class = &omap44xx_mcbsp_hwmod_class,
3152 .clkdm_name = "abe_clkdm",
3153 .mpu_irqs = omap44xx_mcbsp3_irqs,
3154 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
3155 .main_clk = "mcbsp3_fck",
3156 .prcm = {
3157 .omap4 = {
3158 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
3159 .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
3160 .modulemode = MODULEMODE_SWCTRL,
3161 },
3162 },
3163 .slaves = omap44xx_mcbsp3_slaves,
3164 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3165 };
3166
3167 /* mcbsp4 */
3168 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3169 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3170 { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3171 { .irq = -1 }
3172 };
3173
3174 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3175 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3176 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3177 { .dma_req = -1 }
3178 };
3179
3180 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3181 {
3182 .pa_start = 0x48096000,
3183 .pa_end = 0x480960ff,
3184 .flags = ADDR_TYPE_RT
3185 },
3186 { }
3187 };
3188
3189 /* l4_per -> mcbsp4 */
3190 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3191 .master = &omap44xx_l4_per_hwmod,
3192 .slave = &omap44xx_mcbsp4_hwmod,
3193 .clk = "l4_div_ck",
3194 .addr = omap44xx_mcbsp4_addrs,
3195 .user = OCP_USER_MPU | OCP_USER_SDMA,
3196 };
3197
3198 /* mcbsp4 slave ports */
3199 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3200 &omap44xx_l4_per__mcbsp4,
3201 };
3202
3203 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3204 .name = "mcbsp4",
3205 .class = &omap44xx_mcbsp_hwmod_class,
3206 .clkdm_name = "l4_per_clkdm",
3207 .mpu_irqs = omap44xx_mcbsp4_irqs,
3208 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
3209 .main_clk = "mcbsp4_fck",
3210 .prcm = {
3211 .omap4 = {
3212 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
3213 .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
3214 .modulemode = MODULEMODE_SWCTRL,
3215 },
3216 },
3217 .slaves = omap44xx_mcbsp4_slaves,
3218 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3219 };
3220
3221 /*
3222 * 'mcpdm' class
3223 * multi channel pdm controller (proprietary interface with phoenix power
3224 * ic)
3225 */
3226
3227 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3228 .rev_offs = 0x0000,
3229 .sysc_offs = 0x0010,
3230 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3231 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3232 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3233 SIDLE_SMART_WKUP),
3234 .sysc_fields = &omap_hwmod_sysc_type2,
3235 };
3236
3237 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3238 .name = "mcpdm",
3239 .sysc = &omap44xx_mcpdm_sysc,
3240 };
3241
3242 /* mcpdm */
3243 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3244 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3245 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3246 { .irq = -1 }
3247 };
3248
3249 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3250 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3251 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3252 { .dma_req = -1 }
3253 };
3254
3255 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3256 {
3257 .pa_start = 0x40132000,
3258 .pa_end = 0x4013207f,
3259 .flags = ADDR_TYPE_RT
3260 },
3261 { }
3262 };
3263
3264 /* l4_abe -> mcpdm */
3265 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3266 .master = &omap44xx_l4_abe_hwmod,
3267 .slave = &omap44xx_mcpdm_hwmod,
3268 .clk = "ocp_abe_iclk",
3269 .addr = omap44xx_mcpdm_addrs,
3270 .user = OCP_USER_MPU,
3271 };
3272
3273 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3274 {
3275 .pa_start = 0x49032000,
3276 .pa_end = 0x4903207f,
3277 .flags = ADDR_TYPE_RT
3278 },
3279 { }
3280 };
3281
3282 /* l4_abe -> mcpdm (dma) */
3283 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3284 .master = &omap44xx_l4_abe_hwmod,
3285 .slave = &omap44xx_mcpdm_hwmod,
3286 .clk = "ocp_abe_iclk",
3287 .addr = omap44xx_mcpdm_dma_addrs,
3288 .user = OCP_USER_SDMA,
3289 };
3290
3291 /* mcpdm slave ports */
3292 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3293 &omap44xx_l4_abe__mcpdm,
3294 &omap44xx_l4_abe__mcpdm_dma,
3295 };
3296
3297 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3298 .name = "mcpdm",
3299 .class = &omap44xx_mcpdm_hwmod_class,
3300 .clkdm_name = "abe_clkdm",
3301 .mpu_irqs = omap44xx_mcpdm_irqs,
3302 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
3303 .main_clk = "mcpdm_fck",
3304 .prcm = {
3305 .omap4 = {
3306 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
3307 .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
3308 .modulemode = MODULEMODE_SWCTRL,
3309 },
3310 },
3311 .slaves = omap44xx_mcpdm_slaves,
3312 .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3313 };
3314
3315 /*
3316 * 'mcspi' class
3317 * multichannel serial port interface (mcspi) / master/slave synchronous serial
3318 * bus
3319 */
3320
3321 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3322 .rev_offs = 0x0000,
3323 .sysc_offs = 0x0010,
3324 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3325 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3326 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3327 SIDLE_SMART_WKUP),
3328 .sysc_fields = &omap_hwmod_sysc_type2,
3329 };
3330
3331 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3332 .name = "mcspi",
3333 .sysc = &omap44xx_mcspi_sysc,
3334 .rev = OMAP4_MCSPI_REV,
3335 };
3336
3337 /* mcspi1 */
3338 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3339 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3340 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3341 { .irq = -1 }
3342 };
3343
3344 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3345 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3346 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3347 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3348 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3349 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3350 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3351 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3352 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3353 { .dma_req = -1 }
3354 };
3355
3356 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3357 {
3358 .pa_start = 0x48098000,
3359 .pa_end = 0x480981ff,
3360 .flags = ADDR_TYPE_RT
3361 },
3362 { }
3363 };
3364
3365 /* l4_per -> mcspi1 */
3366 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3367 .master = &omap44xx_l4_per_hwmod,
3368 .slave = &omap44xx_mcspi1_hwmod,
3369 .clk = "l4_div_ck",
3370 .addr = omap44xx_mcspi1_addrs,
3371 .user = OCP_USER_MPU | OCP_USER_SDMA,
3372 };
3373
3374 /* mcspi1 slave ports */
3375 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3376 &omap44xx_l4_per__mcspi1,
3377 };
3378
3379 /* mcspi1 dev_attr */
3380 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3381 .num_chipselect = 4,
3382 };
3383
3384 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3385 .name = "mcspi1",
3386 .class = &omap44xx_mcspi_hwmod_class,
3387 .clkdm_name = "l4_per_clkdm",
3388 .mpu_irqs = omap44xx_mcspi1_irqs,
3389 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
3390 .main_clk = "mcspi1_fck",
3391 .prcm = {
3392 .omap4 = {
3393 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
3394 .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
3395 .modulemode = MODULEMODE_SWCTRL,
3396 },
3397 },
3398 .dev_attr = &mcspi1_dev_attr,
3399 .slaves = omap44xx_mcspi1_slaves,
3400 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3401 };
3402
3403 /* mcspi2 */
3404 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3405 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3406 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3407 { .irq = -1 }
3408 };
3409
3410 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3411 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3412 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3413 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3414 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3415 { .dma_req = -1 }
3416 };
3417
3418 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3419 {
3420 .pa_start = 0x4809a000,
3421 .pa_end = 0x4809a1ff,
3422 .flags = ADDR_TYPE_RT
3423 },
3424 { }
3425 };
3426
3427 /* l4_per -> mcspi2 */
3428 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3429 .master = &omap44xx_l4_per_hwmod,
3430 .slave = &omap44xx_mcspi2_hwmod,
3431 .clk = "l4_div_ck",
3432 .addr = omap44xx_mcspi2_addrs,
3433 .user = OCP_USER_MPU | OCP_USER_SDMA,
3434 };
3435
3436 /* mcspi2 slave ports */
3437 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3438 &omap44xx_l4_per__mcspi2,
3439 };
3440
3441 /* mcspi2 dev_attr */
3442 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3443 .num_chipselect = 2,
3444 };
3445
3446 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3447 .name = "mcspi2",
3448 .class = &omap44xx_mcspi_hwmod_class,
3449 .clkdm_name = "l4_per_clkdm",
3450 .mpu_irqs = omap44xx_mcspi2_irqs,
3451 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
3452 .main_clk = "mcspi2_fck",
3453 .prcm = {
3454 .omap4 = {
3455 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
3456 .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
3457 .modulemode = MODULEMODE_SWCTRL,
3458 },
3459 },
3460 .dev_attr = &mcspi2_dev_attr,
3461 .slaves = omap44xx_mcspi2_slaves,
3462 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3463 };
3464
3465 /* mcspi3 */
3466 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3467 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3468 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3469 { .irq = -1 }
3470 };
3471
3472 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3473 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3474 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3475 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3476 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3477 { .dma_req = -1 }
3478 };
3479
3480 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3481 {
3482 .pa_start = 0x480b8000,
3483 .pa_end = 0x480b81ff,
3484 .flags = ADDR_TYPE_RT
3485 },
3486 { }
3487 };
3488
3489 /* l4_per -> mcspi3 */
3490 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3491 .master = &omap44xx_l4_per_hwmod,
3492 .slave = &omap44xx_mcspi3_hwmod,
3493 .clk = "l4_div_ck",
3494 .addr = omap44xx_mcspi3_addrs,
3495 .user = OCP_USER_MPU | OCP_USER_SDMA,
3496 };
3497
3498 /* mcspi3 slave ports */
3499 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3500 &omap44xx_l4_per__mcspi3,
3501 };
3502
3503 /* mcspi3 dev_attr */
3504 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3505 .num_chipselect = 2,
3506 };
3507
3508 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3509 .name = "mcspi3",
3510 .class = &omap44xx_mcspi_hwmod_class,
3511 .clkdm_name = "l4_per_clkdm",
3512 .mpu_irqs = omap44xx_mcspi3_irqs,
3513 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
3514 .main_clk = "mcspi3_fck",
3515 .prcm = {
3516 .omap4 = {
3517 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
3518 .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
3519 .modulemode = MODULEMODE_SWCTRL,
3520 },
3521 },
3522 .dev_attr = &mcspi3_dev_attr,
3523 .slaves = omap44xx_mcspi3_slaves,
3524 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3525 };
3526
3527 /* mcspi4 */
3528 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3529 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3530 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3531 { .irq = -1 }
3532 };
3533
3534 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3535 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3536 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3537 { .dma_req = -1 }
3538 };
3539
3540 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3541 {
3542 .pa_start = 0x480ba000,
3543 .pa_end = 0x480ba1ff,
3544 .flags = ADDR_TYPE_RT
3545 },
3546 { }
3547 };
3548
3549 /* l4_per -> mcspi4 */
3550 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3551 .master = &omap44xx_l4_per_hwmod,
3552 .slave = &omap44xx_mcspi4_hwmod,
3553 .clk = "l4_div_ck",
3554 .addr = omap44xx_mcspi4_addrs,
3555 .user = OCP_USER_MPU | OCP_USER_SDMA,
3556 };
3557
3558 /* mcspi4 slave ports */
3559 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3560 &omap44xx_l4_per__mcspi4,
3561 };
3562
3563 /* mcspi4 dev_attr */
3564 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3565 .num_chipselect = 1,
3566 };
3567
3568 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3569 .name = "mcspi4",
3570 .class = &omap44xx_mcspi_hwmod_class,
3571 .clkdm_name = "l4_per_clkdm",
3572 .mpu_irqs = omap44xx_mcspi4_irqs,
3573 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
3574 .main_clk = "mcspi4_fck",
3575 .prcm = {
3576 .omap4 = {
3577 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
3578 .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
3579 .modulemode = MODULEMODE_SWCTRL,
3580 },
3581 },
3582 .dev_attr = &mcspi4_dev_attr,
3583 .slaves = omap44xx_mcspi4_slaves,
3584 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3585 };
3586
3587 /*
3588 * 'mmc' class
3589 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3590 */
3591
3592 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3593 .rev_offs = 0x0000,
3594 .sysc_offs = 0x0010,
3595 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3596 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3597 SYSC_HAS_SOFTRESET),
3598 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3599 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3600 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3601 .sysc_fields = &omap_hwmod_sysc_type2,
3602 };
3603
3604 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3605 .name = "mmc",
3606 .sysc = &omap44xx_mmc_sysc,
3607 };
3608
3609 /* mmc1 */
3610 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3611 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3612 { .irq = -1 }
3613 };
3614
3615 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3616 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3617 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3618 { .dma_req = -1 }
3619 };
3620
3621 /* mmc1 master ports */
3622 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3623 &omap44xx_mmc1__l3_main_1,
3624 };
3625
3626 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3627 {
3628 .pa_start = 0x4809c000,
3629 .pa_end = 0x4809c3ff,
3630 .flags = ADDR_TYPE_RT
3631 },
3632 { }
3633 };
3634
3635 /* l4_per -> mmc1 */
3636 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3637 .master = &omap44xx_l4_per_hwmod,
3638 .slave = &omap44xx_mmc1_hwmod,
3639 .clk = "l4_div_ck",
3640 .addr = omap44xx_mmc1_addrs,
3641 .user = OCP_USER_MPU | OCP_USER_SDMA,
3642 };
3643
3644 /* mmc1 slave ports */
3645 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3646 &omap44xx_l4_per__mmc1,
3647 };
3648
3649 /* mmc1 dev_attr */
3650 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3651 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3652 };
3653
3654 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3655 .name = "mmc1",
3656 .class = &omap44xx_mmc_hwmod_class,
3657 .clkdm_name = "l3_init_clkdm",
3658 .mpu_irqs = omap44xx_mmc1_irqs,
3659 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
3660 .main_clk = "mmc1_fck",
3661 .prcm = {
3662 .omap4 = {
3663 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
3664 .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
3665 .modulemode = MODULEMODE_SWCTRL,
3666 },
3667 },
3668 .dev_attr = &mmc1_dev_attr,
3669 .slaves = omap44xx_mmc1_slaves,
3670 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
3671 .masters = omap44xx_mmc1_masters,
3672 .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters),
3673 };
3674
3675 /* mmc2 */
3676 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3677 { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3678 { .irq = -1 }
3679 };
3680
3681 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3682 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3683 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3684 { .dma_req = -1 }
3685 };
3686
3687 /* mmc2 master ports */
3688 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3689 &omap44xx_mmc2__l3_main_1,
3690 };
3691
3692 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3693 {
3694 .pa_start = 0x480b4000,
3695 .pa_end = 0x480b43ff,
3696 .flags = ADDR_TYPE_RT
3697 },
3698 { }
3699 };
3700
3701 /* l4_per -> mmc2 */
3702 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3703 .master = &omap44xx_l4_per_hwmod,
3704 .slave = &omap44xx_mmc2_hwmod,
3705 .clk = "l4_div_ck",
3706 .addr = omap44xx_mmc2_addrs,
3707 .user = OCP_USER_MPU | OCP_USER_SDMA,
3708 };
3709
3710 /* mmc2 slave ports */
3711 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3712 &omap44xx_l4_per__mmc2,
3713 };
3714
3715 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3716 .name = "mmc2",
3717 .class = &omap44xx_mmc_hwmod_class,
3718 .clkdm_name = "l3_init_clkdm",
3719 .mpu_irqs = omap44xx_mmc2_irqs,
3720 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
3721 .main_clk = "mmc2_fck",
3722 .prcm = {
3723 .omap4 = {
3724 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
3725 .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
3726 .modulemode = MODULEMODE_SWCTRL,
3727 },
3728 },
3729 .slaves = omap44xx_mmc2_slaves,
3730 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves),
3731 .masters = omap44xx_mmc2_masters,
3732 .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters),
3733 };
3734
3735 /* mmc3 */
3736 static struct omap_hwmod omap44xx_mmc3_hwmod;
3737 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3738 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3739 { .irq = -1 }
3740 };
3741
3742 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3743 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3744 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3745 { .dma_req = -1 }
3746 };
3747
3748 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3749 {
3750 .pa_start = 0x480ad000,
3751 .pa_end = 0x480ad3ff,
3752 .flags = ADDR_TYPE_RT
3753 },
3754 { }
3755 };
3756
3757 /* l4_per -> mmc3 */
3758 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3759 .master = &omap44xx_l4_per_hwmod,
3760 .slave = &omap44xx_mmc3_hwmod,
3761 .clk = "l4_div_ck",
3762 .addr = omap44xx_mmc3_addrs,
3763 .user = OCP_USER_MPU | OCP_USER_SDMA,
3764 };
3765
3766 /* mmc3 slave ports */
3767 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3768 &omap44xx_l4_per__mmc3,
3769 };
3770
3771 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3772 .name = "mmc3",
3773 .class = &omap44xx_mmc_hwmod_class,
3774 .clkdm_name = "l4_per_clkdm",
3775 .mpu_irqs = omap44xx_mmc3_irqs,
3776 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
3777 .main_clk = "mmc3_fck",
3778 .prcm = {
3779 .omap4 = {
3780 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
3781 .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
3782 .modulemode = MODULEMODE_SWCTRL,
3783 },
3784 },
3785 .slaves = omap44xx_mmc3_slaves,
3786 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves),
3787 };
3788
3789 /* mmc4 */
3790 static struct omap_hwmod omap44xx_mmc4_hwmod;
3791 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3792 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3793 { .irq = -1 }
3794 };
3795
3796 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3797 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3798 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3799 { .dma_req = -1 }
3800 };
3801
3802 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3803 {
3804 .pa_start = 0x480d1000,
3805 .pa_end = 0x480d13ff,
3806 .flags = ADDR_TYPE_RT
3807 },
3808 { }
3809 };
3810
3811 /* l4_per -> mmc4 */
3812 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3813 .master = &omap44xx_l4_per_hwmod,
3814 .slave = &omap44xx_mmc4_hwmod,
3815 .clk = "l4_div_ck",
3816 .addr = omap44xx_mmc4_addrs,
3817 .user = OCP_USER_MPU | OCP_USER_SDMA,
3818 };
3819
3820 /* mmc4 slave ports */
3821 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3822 &omap44xx_l4_per__mmc4,
3823 };
3824
3825 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3826 .name = "mmc4",
3827 .class = &omap44xx_mmc_hwmod_class,
3828 .clkdm_name = "l4_per_clkdm",
3829 .mpu_irqs = omap44xx_mmc4_irqs,
3830
3831 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
3832 .main_clk = "mmc4_fck",
3833 .prcm = {
3834 .omap4 = {
3835 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
3836 .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
3837 .modulemode = MODULEMODE_SWCTRL,
3838 },
3839 },
3840 .slaves = omap44xx_mmc4_slaves,
3841 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves),
3842 };
3843
3844 /* mmc5 */
3845 static struct omap_hwmod omap44xx_mmc5_hwmod;
3846 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3847 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3848 { .irq = -1 }
3849 };
3850
3851 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3852 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3853 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3854 { .dma_req = -1 }
3855 };
3856
3857 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3858 {
3859 .pa_start = 0x480d5000,
3860 .pa_end = 0x480d53ff,
3861 .flags = ADDR_TYPE_RT
3862 },
3863 { }
3864 };
3865
3866 /* l4_per -> mmc5 */
3867 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3868 .master = &omap44xx_l4_per_hwmod,
3869 .slave = &omap44xx_mmc5_hwmod,
3870 .clk = "l4_div_ck",
3871 .addr = omap44xx_mmc5_addrs,
3872 .user = OCP_USER_MPU | OCP_USER_SDMA,
3873 };
3874
3875 /* mmc5 slave ports */
3876 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3877 &omap44xx_l4_per__mmc5,
3878 };
3879
3880 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3881 .name = "mmc5",
3882 .class = &omap44xx_mmc_hwmod_class,
3883 .clkdm_name = "l4_per_clkdm",
3884 .mpu_irqs = omap44xx_mmc5_irqs,
3885 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
3886 .main_clk = "mmc5_fck",
3887 .prcm = {
3888 .omap4 = {
3889 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
3890 .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
3891 .modulemode = MODULEMODE_SWCTRL,
3892 },
3893 },
3894 .slaves = omap44xx_mmc5_slaves,
3895 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves),
3896 };
3897
3898 /*
3899 * 'mpu' class
3900 * mpu sub-system
3901 */
3902
3903 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3904 .name = "mpu",
3905 };
3906
3907 /* mpu */
3908 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3909 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3910 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3911 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3912 { .irq = -1 }
3913 };
3914
3915 /* mpu master ports */
3916 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3917 &omap44xx_mpu__l3_main_1,
3918 &omap44xx_mpu__l4_abe,
3919 &omap44xx_mpu__dmm,
3920 };
3921
3922 static struct omap_hwmod omap44xx_mpu_hwmod = {
3923 .name = "mpu",
3924 .class = &omap44xx_mpu_hwmod_class,
3925 .clkdm_name = "mpuss_clkdm",
3926 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3927 .mpu_irqs = omap44xx_mpu_irqs,
3928 .main_clk = "dpll_mpu_m2_ck",
3929 .prcm = {
3930 .omap4 = {
3931 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
3932 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
3933 },
3934 },
3935 .masters = omap44xx_mpu_masters,
3936 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
3937 };
3938
3939 /*
3940 * 'smartreflex' class
3941 * smartreflex module (monitor silicon performance and outputs a measure of
3942 * performance error)
3943 */
3944
3945 /* The IP is not compliant to type1 / type2 scheme */
3946 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3947 .sidle_shift = 24,
3948 .enwkup_shift = 26,
3949 };
3950
3951 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3952 .sysc_offs = 0x0038,
3953 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3954 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3955 SIDLE_SMART_WKUP),
3956 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
3957 };
3958
3959 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3960 .name = "smartreflex",
3961 .sysc = &omap44xx_smartreflex_sysc,
3962 .rev = 2,
3963 };
3964
3965 /* smartreflex_core */
3966 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3967 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3968 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3969 { .irq = -1 }
3970 };
3971
3972 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3973 {
3974 .pa_start = 0x4a0dd000,
3975 .pa_end = 0x4a0dd03f,
3976 .flags = ADDR_TYPE_RT
3977 },
3978 { }
3979 };
3980
3981 /* l4_cfg -> smartreflex_core */
3982 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3983 .master = &omap44xx_l4_cfg_hwmod,
3984 .slave = &omap44xx_smartreflex_core_hwmod,
3985 .clk = "l4_div_ck",
3986 .addr = omap44xx_smartreflex_core_addrs,
3987 .user = OCP_USER_MPU | OCP_USER_SDMA,
3988 };
3989
3990 /* smartreflex_core slave ports */
3991 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3992 &omap44xx_l4_cfg__smartreflex_core,
3993 };
3994
3995 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3996 .name = "smartreflex_core",
3997 .class = &omap44xx_smartreflex_hwmod_class,
3998 .clkdm_name = "l4_ao_clkdm",
3999 .mpu_irqs = omap44xx_smartreflex_core_irqs,
4000
4001 .main_clk = "smartreflex_core_fck",
4002 .vdd_name = "core",
4003 .prcm = {
4004 .omap4 = {
4005 .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
4006 .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
4007 .modulemode = MODULEMODE_SWCTRL,
4008 },
4009 },
4010 .slaves = omap44xx_smartreflex_core_slaves,
4011 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
4012 };
4013
4014 /* smartreflex_iva */
4015 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
4016 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
4017 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
4018 { .irq = -1 }
4019 };
4020
4021 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4022 {
4023 .pa_start = 0x4a0db000,
4024 .pa_end = 0x4a0db03f,
4025 .flags = ADDR_TYPE_RT
4026 },
4027 { }
4028 };
4029
4030 /* l4_cfg -> smartreflex_iva */
4031 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4032 .master = &omap44xx_l4_cfg_hwmod,
4033 .slave = &omap44xx_smartreflex_iva_hwmod,
4034 .clk = "l4_div_ck",
4035 .addr = omap44xx_smartreflex_iva_addrs,
4036 .user = OCP_USER_MPU | OCP_USER_SDMA,
4037 };
4038
4039 /* smartreflex_iva slave ports */
4040 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
4041 &omap44xx_l4_cfg__smartreflex_iva,
4042 };
4043
4044 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
4045 .name = "smartreflex_iva",
4046 .class = &omap44xx_smartreflex_hwmod_class,
4047 .clkdm_name = "l4_ao_clkdm",
4048 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
4049 .main_clk = "smartreflex_iva_fck",
4050 .vdd_name = "iva",
4051 .prcm = {
4052 .omap4 = {
4053 .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
4054 .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
4055 .modulemode = MODULEMODE_SWCTRL,
4056 },
4057 },
4058 .slaves = omap44xx_smartreflex_iva_slaves,
4059 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
4060 };
4061
4062 /* smartreflex_mpu */
4063 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
4064 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
4065 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
4066 { .irq = -1 }
4067 };
4068
4069 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4070 {
4071 .pa_start = 0x4a0d9000,
4072 .pa_end = 0x4a0d903f,
4073 .flags = ADDR_TYPE_RT
4074 },
4075 { }
4076 };
4077
4078 /* l4_cfg -> smartreflex_mpu */
4079 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4080 .master = &omap44xx_l4_cfg_hwmod,
4081 .slave = &omap44xx_smartreflex_mpu_hwmod,
4082 .clk = "l4_div_ck",
4083 .addr = omap44xx_smartreflex_mpu_addrs,
4084 .user = OCP_USER_MPU | OCP_USER_SDMA,
4085 };
4086
4087 /* smartreflex_mpu slave ports */
4088 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
4089 &omap44xx_l4_cfg__smartreflex_mpu,
4090 };
4091
4092 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
4093 .name = "smartreflex_mpu",
4094 .class = &omap44xx_smartreflex_hwmod_class,
4095 .clkdm_name = "l4_ao_clkdm",
4096 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
4097 .main_clk = "smartreflex_mpu_fck",
4098 .vdd_name = "mpu",
4099 .prcm = {
4100 .omap4 = {
4101 .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
4102 .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
4103 .modulemode = MODULEMODE_SWCTRL,
4104 },
4105 },
4106 .slaves = omap44xx_smartreflex_mpu_slaves,
4107 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
4108 };
4109
4110 /*
4111 * 'spinlock' class
4112 * spinlock provides hardware assistance for synchronizing the processes
4113 * running on multiple processors
4114 */
4115
4116 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
4117 .rev_offs = 0x0000,
4118 .sysc_offs = 0x0010,
4119 .syss_offs = 0x0014,
4120 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4121 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
4122 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4123 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4124 SIDLE_SMART_WKUP),
4125 .sysc_fields = &omap_hwmod_sysc_type1,
4126 };
4127
4128 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
4129 .name = "spinlock",
4130 .sysc = &omap44xx_spinlock_sysc,
4131 };
4132
4133 /* spinlock */
4134 static struct omap_hwmod omap44xx_spinlock_hwmod;
4135 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4136 {
4137 .pa_start = 0x4a0f6000,
4138 .pa_end = 0x4a0f6fff,
4139 .flags = ADDR_TYPE_RT
4140 },
4141 { }
4142 };
4143
4144 /* l4_cfg -> spinlock */
4145 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4146 .master = &omap44xx_l4_cfg_hwmod,
4147 .slave = &omap44xx_spinlock_hwmod,
4148 .clk = "l4_div_ck",
4149 .addr = omap44xx_spinlock_addrs,
4150 .user = OCP_USER_MPU | OCP_USER_SDMA,
4151 };
4152
4153 /* spinlock slave ports */
4154 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
4155 &omap44xx_l4_cfg__spinlock,
4156 };
4157
4158 static struct omap_hwmod omap44xx_spinlock_hwmod = {
4159 .name = "spinlock",
4160 .class = &omap44xx_spinlock_hwmod_class,
4161 .clkdm_name = "l4_cfg_clkdm",
4162 .prcm = {
4163 .omap4 = {
4164 .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
4165 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
4166 },
4167 },
4168 .slaves = omap44xx_spinlock_slaves,
4169 .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves),
4170 };
4171
4172 /*
4173 * 'timer' class
4174 * general purpose timer module with accurate 1ms tick
4175 * This class contains several variants: ['timer_1ms', 'timer']
4176 */
4177
4178 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
4179 .rev_offs = 0x0000,
4180 .sysc_offs = 0x0010,
4181 .syss_offs = 0x0014,
4182 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4183 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
4184 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4185 SYSS_HAS_RESET_STATUS),
4186 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
4187 .sysc_fields = &omap_hwmod_sysc_type1,
4188 };
4189
4190 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
4191 .name = "timer",
4192 .sysc = &omap44xx_timer_1ms_sysc,
4193 };
4194
4195 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4196 .rev_offs = 0x0000,
4197 .sysc_offs = 0x0010,
4198 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4199 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4200 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4201 SIDLE_SMART_WKUP),
4202 .sysc_fields = &omap_hwmod_sysc_type2,
4203 };
4204
4205 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4206 .name = "timer",
4207 .sysc = &omap44xx_timer_sysc,
4208 };
4209
4210 /* always-on timers dev attribute */
4211 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
4212 .timer_capability = OMAP_TIMER_ALWON,
4213 };
4214
4215 /* pwm timers dev attribute */
4216 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
4217 .timer_capability = OMAP_TIMER_HAS_PWM,
4218 };
4219
4220 /* timer1 */
4221 static struct omap_hwmod omap44xx_timer1_hwmod;
4222 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4223 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4224 { .irq = -1 }
4225 };
4226
4227 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4228 {
4229 .pa_start = 0x4a318000,
4230 .pa_end = 0x4a31807f,
4231 .flags = ADDR_TYPE_RT
4232 },
4233 { }
4234 };
4235
4236 /* l4_wkup -> timer1 */
4237 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4238 .master = &omap44xx_l4_wkup_hwmod,
4239 .slave = &omap44xx_timer1_hwmod,
4240 .clk = "l4_wkup_clk_mux_ck",
4241 .addr = omap44xx_timer1_addrs,
4242 .user = OCP_USER_MPU | OCP_USER_SDMA,
4243 };
4244
4245 /* timer1 slave ports */
4246 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4247 &omap44xx_l4_wkup__timer1,
4248 };
4249
4250 static struct omap_hwmod omap44xx_timer1_hwmod = {
4251 .name = "timer1",
4252 .class = &omap44xx_timer_1ms_hwmod_class,
4253 .clkdm_name = "l4_wkup_clkdm",
4254 .mpu_irqs = omap44xx_timer1_irqs,
4255 .main_clk = "timer1_fck",
4256 .prcm = {
4257 .omap4 = {
4258 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
4259 .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
4260 .modulemode = MODULEMODE_SWCTRL,
4261 },
4262 },
4263 .dev_attr = &capability_alwon_dev_attr,
4264 .slaves = omap44xx_timer1_slaves,
4265 .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
4266 };
4267
4268 /* timer2 */
4269 static struct omap_hwmod omap44xx_timer2_hwmod;
4270 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4271 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4272 { .irq = -1 }
4273 };
4274
4275 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4276 {
4277 .pa_start = 0x48032000,
4278 .pa_end = 0x4803207f,
4279 .flags = ADDR_TYPE_RT
4280 },
4281 { }
4282 };
4283
4284 /* l4_per -> timer2 */
4285 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4286 .master = &omap44xx_l4_per_hwmod,
4287 .slave = &omap44xx_timer2_hwmod,
4288 .clk = "l4_div_ck",
4289 .addr = omap44xx_timer2_addrs,
4290 .user = OCP_USER_MPU | OCP_USER_SDMA,
4291 };
4292
4293 /* timer2 slave ports */
4294 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4295 &omap44xx_l4_per__timer2,
4296 };
4297
4298 static struct omap_hwmod omap44xx_timer2_hwmod = {
4299 .name = "timer2",
4300 .class = &omap44xx_timer_1ms_hwmod_class,
4301 .clkdm_name = "l4_per_clkdm",
4302 .mpu_irqs = omap44xx_timer2_irqs,
4303 .main_clk = "timer2_fck",
4304 .prcm = {
4305 .omap4 = {
4306 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
4307 .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
4308 .modulemode = MODULEMODE_SWCTRL,
4309 },
4310 },
4311 .dev_attr = &capability_alwon_dev_attr,
4312 .slaves = omap44xx_timer2_slaves,
4313 .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
4314 };
4315
4316 /* timer3 */
4317 static struct omap_hwmod omap44xx_timer3_hwmod;
4318 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4319 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4320 { .irq = -1 }
4321 };
4322
4323 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4324 {
4325 .pa_start = 0x48034000,
4326 .pa_end = 0x4803407f,
4327 .flags = ADDR_TYPE_RT
4328 },
4329 { }
4330 };
4331
4332 /* l4_per -> timer3 */
4333 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4334 .master = &omap44xx_l4_per_hwmod,
4335 .slave = &omap44xx_timer3_hwmod,
4336 .clk = "l4_div_ck",
4337 .addr = omap44xx_timer3_addrs,
4338 .user = OCP_USER_MPU | OCP_USER_SDMA,
4339 };
4340
4341 /* timer3 slave ports */
4342 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4343 &omap44xx_l4_per__timer3,
4344 };
4345
4346 static struct omap_hwmod omap44xx_timer3_hwmod = {
4347 .name = "timer3",
4348 .class = &omap44xx_timer_hwmod_class,
4349 .clkdm_name = "l4_per_clkdm",
4350 .mpu_irqs = omap44xx_timer3_irqs,
4351 .main_clk = "timer3_fck",
4352 .prcm = {
4353 .omap4 = {
4354 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
4355 .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
4356 .modulemode = MODULEMODE_SWCTRL,
4357 },
4358 },
4359 .dev_attr = &capability_alwon_dev_attr,
4360 .slaves = omap44xx_timer3_slaves,
4361 .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
4362 };
4363
4364 /* timer4 */
4365 static struct omap_hwmod omap44xx_timer4_hwmod;
4366 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4367 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4368 { .irq = -1 }
4369 };
4370
4371 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4372 {
4373 .pa_start = 0x48036000,
4374 .pa_end = 0x4803607f,
4375 .flags = ADDR_TYPE_RT
4376 },
4377 { }
4378 };
4379
4380 /* l4_per -> timer4 */
4381 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4382 .master = &omap44xx_l4_per_hwmod,
4383 .slave = &omap44xx_timer4_hwmod,
4384 .clk = "l4_div_ck",
4385 .addr = omap44xx_timer4_addrs,
4386 .user = OCP_USER_MPU | OCP_USER_SDMA,
4387 };
4388
4389 /* timer4 slave ports */
4390 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4391 &omap44xx_l4_per__timer4,
4392 };
4393
4394 static struct omap_hwmod omap44xx_timer4_hwmod = {
4395 .name = "timer4",
4396 .class = &omap44xx_timer_hwmod_class,
4397 .clkdm_name = "l4_per_clkdm",
4398 .mpu_irqs = omap44xx_timer4_irqs,
4399 .main_clk = "timer4_fck",
4400 .prcm = {
4401 .omap4 = {
4402 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
4403 .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
4404 .modulemode = MODULEMODE_SWCTRL,
4405 },
4406 },
4407 .dev_attr = &capability_alwon_dev_attr,
4408 .slaves = omap44xx_timer4_slaves,
4409 .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
4410 };
4411
4412 /* timer5 */
4413 static struct omap_hwmod omap44xx_timer5_hwmod;
4414 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4415 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4416 { .irq = -1 }
4417 };
4418
4419 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4420 {
4421 .pa_start = 0x40138000,
4422 .pa_end = 0x4013807f,
4423 .flags = ADDR_TYPE_RT
4424 },
4425 { }
4426 };
4427
4428 /* l4_abe -> timer5 */
4429 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4430 .master = &omap44xx_l4_abe_hwmod,
4431 .slave = &omap44xx_timer5_hwmod,
4432 .clk = "ocp_abe_iclk",
4433 .addr = omap44xx_timer5_addrs,
4434 .user = OCP_USER_MPU,
4435 };
4436
4437 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4438 {
4439 .pa_start = 0x49038000,
4440 .pa_end = 0x4903807f,
4441 .flags = ADDR_TYPE_RT
4442 },
4443 { }
4444 };
4445
4446 /* l4_abe -> timer5 (dma) */
4447 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4448 .master = &omap44xx_l4_abe_hwmod,
4449 .slave = &omap44xx_timer5_hwmod,
4450 .clk = "ocp_abe_iclk",
4451 .addr = omap44xx_timer5_dma_addrs,
4452 .user = OCP_USER_SDMA,
4453 };
4454
4455 /* timer5 slave ports */
4456 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4457 &omap44xx_l4_abe__timer5,
4458 &omap44xx_l4_abe__timer5_dma,
4459 };
4460
4461 static struct omap_hwmod omap44xx_timer5_hwmod = {
4462 .name = "timer5",
4463 .class = &omap44xx_timer_hwmod_class,
4464 .clkdm_name = "abe_clkdm",
4465 .mpu_irqs = omap44xx_timer5_irqs,
4466 .main_clk = "timer5_fck",
4467 .prcm = {
4468 .omap4 = {
4469 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
4470 .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
4471 .modulemode = MODULEMODE_SWCTRL,
4472 },
4473 },
4474 .dev_attr = &capability_alwon_dev_attr,
4475 .slaves = omap44xx_timer5_slaves,
4476 .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
4477 };
4478
4479 /* timer6 */
4480 static struct omap_hwmod omap44xx_timer6_hwmod;
4481 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4482 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4483 { .irq = -1 }
4484 };
4485
4486 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4487 {
4488 .pa_start = 0x4013a000,
4489 .pa_end = 0x4013a07f,
4490 .flags = ADDR_TYPE_RT
4491 },
4492 { }
4493 };
4494
4495 /* l4_abe -> timer6 */
4496 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4497 .master = &omap44xx_l4_abe_hwmod,
4498 .slave = &omap44xx_timer6_hwmod,
4499 .clk = "ocp_abe_iclk",
4500 .addr = omap44xx_timer6_addrs,
4501 .user = OCP_USER_MPU,
4502 };
4503
4504 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4505 {
4506 .pa_start = 0x4903a000,
4507 .pa_end = 0x4903a07f,
4508 .flags = ADDR_TYPE_RT
4509 },
4510 { }
4511 };
4512
4513 /* l4_abe -> timer6 (dma) */
4514 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4515 .master = &omap44xx_l4_abe_hwmod,
4516 .slave = &omap44xx_timer6_hwmod,
4517 .clk = "ocp_abe_iclk",
4518 .addr = omap44xx_timer6_dma_addrs,
4519 .user = OCP_USER_SDMA,
4520 };
4521
4522 /* timer6 slave ports */
4523 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4524 &omap44xx_l4_abe__timer6,
4525 &omap44xx_l4_abe__timer6_dma,
4526 };
4527
4528 static struct omap_hwmod omap44xx_timer6_hwmod = {
4529 .name = "timer6",
4530 .class = &omap44xx_timer_hwmod_class,
4531 .clkdm_name = "abe_clkdm",
4532 .mpu_irqs = omap44xx_timer6_irqs,
4533
4534 .main_clk = "timer6_fck",
4535 .prcm = {
4536 .omap4 = {
4537 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
4538 .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
4539 .modulemode = MODULEMODE_SWCTRL,
4540 },
4541 },
4542 .dev_attr = &capability_alwon_dev_attr,
4543 .slaves = omap44xx_timer6_slaves,
4544 .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
4545 };
4546
4547 /* timer7 */
4548 static struct omap_hwmod omap44xx_timer7_hwmod;
4549 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4550 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4551 { .irq = -1 }
4552 };
4553
4554 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4555 {
4556 .pa_start = 0x4013c000,
4557 .pa_end = 0x4013c07f,
4558 .flags = ADDR_TYPE_RT
4559 },
4560 { }
4561 };
4562
4563 /* l4_abe -> timer7 */
4564 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4565 .master = &omap44xx_l4_abe_hwmod,
4566 .slave = &omap44xx_timer7_hwmod,
4567 .clk = "ocp_abe_iclk",
4568 .addr = omap44xx_timer7_addrs,
4569 .user = OCP_USER_MPU,
4570 };
4571
4572 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4573 {
4574 .pa_start = 0x4903c000,
4575 .pa_end = 0x4903c07f,
4576 .flags = ADDR_TYPE_RT
4577 },
4578 { }
4579 };
4580
4581 /* l4_abe -> timer7 (dma) */
4582 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4583 .master = &omap44xx_l4_abe_hwmod,
4584 .slave = &omap44xx_timer7_hwmod,
4585 .clk = "ocp_abe_iclk",
4586 .addr = omap44xx_timer7_dma_addrs,
4587 .user = OCP_USER_SDMA,
4588 };
4589
4590 /* timer7 slave ports */
4591 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4592 &omap44xx_l4_abe__timer7,
4593 &omap44xx_l4_abe__timer7_dma,
4594 };
4595
4596 static struct omap_hwmod omap44xx_timer7_hwmod = {
4597 .name = "timer7",
4598 .class = &omap44xx_timer_hwmod_class,
4599 .clkdm_name = "abe_clkdm",
4600 .mpu_irqs = omap44xx_timer7_irqs,
4601 .main_clk = "timer7_fck",
4602 .prcm = {
4603 .omap4 = {
4604 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
4605 .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
4606 .modulemode = MODULEMODE_SWCTRL,
4607 },
4608 },
4609 .dev_attr = &capability_alwon_dev_attr,
4610 .slaves = omap44xx_timer7_slaves,
4611 .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
4612 };
4613
4614 /* timer8 */
4615 static struct omap_hwmod omap44xx_timer8_hwmod;
4616 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4617 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4618 { .irq = -1 }
4619 };
4620
4621 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4622 {
4623 .pa_start = 0x4013e000,
4624 .pa_end = 0x4013e07f,
4625 .flags = ADDR_TYPE_RT
4626 },
4627 { }
4628 };
4629
4630 /* l4_abe -> timer8 */
4631 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4632 .master = &omap44xx_l4_abe_hwmod,
4633 .slave = &omap44xx_timer8_hwmod,
4634 .clk = "ocp_abe_iclk",
4635 .addr = omap44xx_timer8_addrs,
4636 .user = OCP_USER_MPU,
4637 };
4638
4639 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4640 {
4641 .pa_start = 0x4903e000,
4642 .pa_end = 0x4903e07f,
4643 .flags = ADDR_TYPE_RT
4644 },
4645 { }
4646 };
4647
4648 /* l4_abe -> timer8 (dma) */
4649 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4650 .master = &omap44xx_l4_abe_hwmod,
4651 .slave = &omap44xx_timer8_hwmod,
4652 .clk = "ocp_abe_iclk",
4653 .addr = omap44xx_timer8_dma_addrs,
4654 .user = OCP_USER_SDMA,
4655 };
4656
4657 /* timer8 slave ports */
4658 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4659 &omap44xx_l4_abe__timer8,
4660 &omap44xx_l4_abe__timer8_dma,
4661 };
4662
4663 static struct omap_hwmod omap44xx_timer8_hwmod = {
4664 .name = "timer8",
4665 .class = &omap44xx_timer_hwmod_class,
4666 .clkdm_name = "abe_clkdm",
4667 .mpu_irqs = omap44xx_timer8_irqs,
4668 .main_clk = "timer8_fck",
4669 .prcm = {
4670 .omap4 = {
4671 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
4672 .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
4673 .modulemode = MODULEMODE_SWCTRL,
4674 },
4675 },
4676 .dev_attr = &capability_pwm_dev_attr,
4677 .slaves = omap44xx_timer8_slaves,
4678 .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
4679 };
4680
4681 /* timer9 */
4682 static struct omap_hwmod omap44xx_timer9_hwmod;
4683 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4684 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4685 { .irq = -1 }
4686 };
4687
4688 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4689 {
4690 .pa_start = 0x4803e000,
4691 .pa_end = 0x4803e07f,
4692 .flags = ADDR_TYPE_RT
4693 },
4694 { }
4695 };
4696
4697 /* l4_per -> timer9 */
4698 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4699 .master = &omap44xx_l4_per_hwmod,
4700 .slave = &omap44xx_timer9_hwmod,
4701 .clk = "l4_div_ck",
4702 .addr = omap44xx_timer9_addrs,
4703 .user = OCP_USER_MPU | OCP_USER_SDMA,
4704 };
4705
4706 /* timer9 slave ports */
4707 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4708 &omap44xx_l4_per__timer9,
4709 };
4710
4711 static struct omap_hwmod omap44xx_timer9_hwmod = {
4712 .name = "timer9",
4713 .class = &omap44xx_timer_hwmod_class,
4714 .clkdm_name = "l4_per_clkdm",
4715 .mpu_irqs = omap44xx_timer9_irqs,
4716 .main_clk = "timer9_fck",
4717 .prcm = {
4718 .omap4 = {
4719 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
4720 .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
4721 .modulemode = MODULEMODE_SWCTRL,
4722 },
4723 },
4724 .dev_attr = &capability_pwm_dev_attr,
4725 .slaves = omap44xx_timer9_slaves,
4726 .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
4727 };
4728
4729 /* timer10 */
4730 static struct omap_hwmod omap44xx_timer10_hwmod;
4731 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4732 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4733 { .irq = -1 }
4734 };
4735
4736 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4737 {
4738 .pa_start = 0x48086000,
4739 .pa_end = 0x4808607f,
4740 .flags = ADDR_TYPE_RT
4741 },
4742 { }
4743 };
4744
4745 /* l4_per -> timer10 */
4746 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4747 .master = &omap44xx_l4_per_hwmod,
4748 .slave = &omap44xx_timer10_hwmod,
4749 .clk = "l4_div_ck",
4750 .addr = omap44xx_timer10_addrs,
4751 .user = OCP_USER_MPU | OCP_USER_SDMA,
4752 };
4753
4754 /* timer10 slave ports */
4755 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4756 &omap44xx_l4_per__timer10,
4757 };
4758
4759 static struct omap_hwmod omap44xx_timer10_hwmod = {
4760 .name = "timer10",
4761 .class = &omap44xx_timer_1ms_hwmod_class,
4762 .clkdm_name = "l4_per_clkdm",
4763 .mpu_irqs = omap44xx_timer10_irqs,
4764 .main_clk = "timer10_fck",
4765 .prcm = {
4766 .omap4 = {
4767 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
4768 .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
4769 .modulemode = MODULEMODE_SWCTRL,
4770 },
4771 },
4772 .dev_attr = &capability_pwm_dev_attr,
4773 .slaves = omap44xx_timer10_slaves,
4774 .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
4775 };
4776
4777 /* timer11 */
4778 static struct omap_hwmod omap44xx_timer11_hwmod;
4779 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4780 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4781 { .irq = -1 }
4782 };
4783
4784 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4785 {
4786 .pa_start = 0x48088000,
4787 .pa_end = 0x4808807f,
4788 .flags = ADDR_TYPE_RT
4789 },
4790 { }
4791 };
4792
4793 /* l4_per -> timer11 */
4794 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4795 .master = &omap44xx_l4_per_hwmod,
4796 .slave = &omap44xx_timer11_hwmod,
4797 .clk = "l4_div_ck",
4798 .addr = omap44xx_timer11_addrs,
4799 .user = OCP_USER_MPU | OCP_USER_SDMA,
4800 };
4801
4802 /* timer11 slave ports */
4803 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4804 &omap44xx_l4_per__timer11,
4805 };
4806
4807 static struct omap_hwmod omap44xx_timer11_hwmod = {
4808 .name = "timer11",
4809 .class = &omap44xx_timer_hwmod_class,
4810 .clkdm_name = "l4_per_clkdm",
4811 .mpu_irqs = omap44xx_timer11_irqs,
4812 .main_clk = "timer11_fck",
4813 .prcm = {
4814 .omap4 = {
4815 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
4816 .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
4817 .modulemode = MODULEMODE_SWCTRL,
4818 },
4819 },
4820 .dev_attr = &capability_pwm_dev_attr,
4821 .slaves = omap44xx_timer11_slaves,
4822 .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
4823 };
4824
4825 /*
4826 * 'uart' class
4827 * universal asynchronous receiver/transmitter (uart)
4828 */
4829
4830 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4831 .rev_offs = 0x0050,
4832 .sysc_offs = 0x0054,
4833 .syss_offs = 0x0058,
4834 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4835 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4836 SYSS_HAS_RESET_STATUS),
4837 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4838 SIDLE_SMART_WKUP),
4839 .sysc_fields = &omap_hwmod_sysc_type1,
4840 };
4841
4842 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4843 .name = "uart",
4844 .sysc = &omap44xx_uart_sysc,
4845 };
4846
4847 /* uart1 */
4848 static struct omap_hwmod omap44xx_uart1_hwmod;
4849 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4850 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4851 { .irq = -1 }
4852 };
4853
4854 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4855 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4856 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4857 { .dma_req = -1 }
4858 };
4859
4860 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4861 {
4862 .pa_start = 0x4806a000,
4863 .pa_end = 0x4806a0ff,
4864 .flags = ADDR_TYPE_RT
4865 },
4866 { }
4867 };
4868
4869 /* l4_per -> uart1 */
4870 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4871 .master = &omap44xx_l4_per_hwmod,
4872 .slave = &omap44xx_uart1_hwmod,
4873 .clk = "l4_div_ck",
4874 .addr = omap44xx_uart1_addrs,
4875 .user = OCP_USER_MPU | OCP_USER_SDMA,
4876 };
4877
4878 /* uart1 slave ports */
4879 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4880 &omap44xx_l4_per__uart1,
4881 };
4882
4883 static struct omap_hwmod omap44xx_uart1_hwmod = {
4884 .name = "uart1",
4885 .class = &omap44xx_uart_hwmod_class,
4886 .clkdm_name = "l4_per_clkdm",
4887 .mpu_irqs = omap44xx_uart1_irqs,
4888 .sdma_reqs = omap44xx_uart1_sdma_reqs,
4889 .main_clk = "uart1_fck",
4890 .prcm = {
4891 .omap4 = {
4892 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
4893 .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
4894 .modulemode = MODULEMODE_SWCTRL,
4895 },
4896 },
4897 .slaves = omap44xx_uart1_slaves,
4898 .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
4899 };
4900
4901 /* uart2 */
4902 static struct omap_hwmod omap44xx_uart2_hwmod;
4903 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4904 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4905 { .irq = -1 }
4906 };
4907
4908 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4909 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4910 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4911 { .dma_req = -1 }
4912 };
4913
4914 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4915 {
4916 .pa_start = 0x4806c000,
4917 .pa_end = 0x4806c0ff,
4918 .flags = ADDR_TYPE_RT
4919 },
4920 { }
4921 };
4922
4923 /* l4_per -> uart2 */
4924 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4925 .master = &omap44xx_l4_per_hwmod,
4926 .slave = &omap44xx_uart2_hwmod,
4927 .clk = "l4_div_ck",
4928 .addr = omap44xx_uart2_addrs,
4929 .user = OCP_USER_MPU | OCP_USER_SDMA,
4930 };
4931
4932 /* uart2 slave ports */
4933 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4934 &omap44xx_l4_per__uart2,
4935 };
4936
4937 static struct omap_hwmod omap44xx_uart2_hwmod = {
4938 .name = "uart2",
4939 .class = &omap44xx_uart_hwmod_class,
4940 .clkdm_name = "l4_per_clkdm",
4941 .mpu_irqs = omap44xx_uart2_irqs,
4942 .sdma_reqs = omap44xx_uart2_sdma_reqs,
4943 .main_clk = "uart2_fck",
4944 .prcm = {
4945 .omap4 = {
4946 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
4947 .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
4948 .modulemode = MODULEMODE_SWCTRL,
4949 },
4950 },
4951 .slaves = omap44xx_uart2_slaves,
4952 .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
4953 };
4954
4955 /* uart3 */
4956 static struct omap_hwmod omap44xx_uart3_hwmod;
4957 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4958 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4959 { .irq = -1 }
4960 };
4961
4962 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4963 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4964 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4965 { .dma_req = -1 }
4966 };
4967
4968 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4969 {
4970 .pa_start = 0x48020000,
4971 .pa_end = 0x480200ff,
4972 .flags = ADDR_TYPE_RT
4973 },
4974 { }
4975 };
4976
4977 /* l4_per -> uart3 */
4978 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4979 .master = &omap44xx_l4_per_hwmod,
4980 .slave = &omap44xx_uart3_hwmod,
4981 .clk = "l4_div_ck",
4982 .addr = omap44xx_uart3_addrs,
4983 .user = OCP_USER_MPU | OCP_USER_SDMA,
4984 };
4985
4986 /* uart3 slave ports */
4987 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4988 &omap44xx_l4_per__uart3,
4989 };
4990
4991 static struct omap_hwmod omap44xx_uart3_hwmod = {
4992 .name = "uart3",
4993 .class = &omap44xx_uart_hwmod_class,
4994 .clkdm_name = "l4_per_clkdm",
4995 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
4996 .mpu_irqs = omap44xx_uart3_irqs,
4997 .sdma_reqs = omap44xx_uart3_sdma_reqs,
4998 .main_clk = "uart3_fck",
4999 .prcm = {
5000 .omap4 = {
5001 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
5002 .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
5003 .modulemode = MODULEMODE_SWCTRL,
5004 },
5005 },
5006 .slaves = omap44xx_uart3_slaves,
5007 .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
5008 };
5009
5010 /* uart4 */
5011 static struct omap_hwmod omap44xx_uart4_hwmod;
5012 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
5013 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
5014 { .irq = -1 }
5015 };
5016
5017 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
5018 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
5019 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
5020 { .dma_req = -1 }
5021 };
5022
5023 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5024 {
5025 .pa_start = 0x4806e000,
5026 .pa_end = 0x4806e0ff,
5027 .flags = ADDR_TYPE_RT
5028 },
5029 { }
5030 };
5031
5032 /* l4_per -> uart4 */
5033 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5034 .master = &omap44xx_l4_per_hwmod,
5035 .slave = &omap44xx_uart4_hwmod,
5036 .clk = "l4_div_ck",
5037 .addr = omap44xx_uart4_addrs,
5038 .user = OCP_USER_MPU | OCP_USER_SDMA,
5039 };
5040
5041 /* uart4 slave ports */
5042 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
5043 &omap44xx_l4_per__uart4,
5044 };
5045
5046 static struct omap_hwmod omap44xx_uart4_hwmod = {
5047 .name = "uart4",
5048 .class = &omap44xx_uart_hwmod_class,
5049 .clkdm_name = "l4_per_clkdm",
5050 .mpu_irqs = omap44xx_uart4_irqs,
5051 .sdma_reqs = omap44xx_uart4_sdma_reqs,
5052 .main_clk = "uart4_fck",
5053 .prcm = {
5054 .omap4 = {
5055 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
5056 .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
5057 .modulemode = MODULEMODE_SWCTRL,
5058 },
5059 },
5060 .slaves = omap44xx_uart4_slaves,
5061 .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
5062 };
5063
5064 /*
5065 * 'usb_otg_hs' class
5066 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
5067 */
5068
5069 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
5070 .rev_offs = 0x0400,
5071 .sysc_offs = 0x0404,
5072 .syss_offs = 0x0408,
5073 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
5074 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
5075 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5076 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5077 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5078 MSTANDBY_SMART),
5079 .sysc_fields = &omap_hwmod_sysc_type1,
5080 };
5081
5082 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
5083 .name = "usb_otg_hs",
5084 .sysc = &omap44xx_usb_otg_hs_sysc,
5085 };
5086
5087 /* usb_otg_hs */
5088 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
5089 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
5090 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
5091 { .irq = -1 }
5092 };
5093
5094 /* usb_otg_hs master ports */
5095 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
5096 &omap44xx_usb_otg_hs__l3_main_2,
5097 };
5098
5099 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5100 {
5101 .pa_start = 0x4a0ab000,
5102 .pa_end = 0x4a0ab003,
5103 .flags = ADDR_TYPE_RT
5104 },
5105 { }
5106 };
5107
5108 /* l4_cfg -> usb_otg_hs */
5109 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5110 .master = &omap44xx_l4_cfg_hwmod,
5111 .slave = &omap44xx_usb_otg_hs_hwmod,
5112 .clk = "l4_div_ck",
5113 .addr = omap44xx_usb_otg_hs_addrs,
5114 .user = OCP_USER_MPU | OCP_USER_SDMA,
5115 };
5116
5117 /* usb_otg_hs slave ports */
5118 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
5119 &omap44xx_l4_cfg__usb_otg_hs,
5120 };
5121
5122 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
5123 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
5124 };
5125
5126 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
5127 .name = "usb_otg_hs",
5128 .class = &omap44xx_usb_otg_hs_hwmod_class,
5129 .clkdm_name = "l3_init_clkdm",
5130 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
5131 .mpu_irqs = omap44xx_usb_otg_hs_irqs,
5132 .main_clk = "usb_otg_hs_ick",
5133 .prcm = {
5134 .omap4 = {
5135 .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
5136 .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
5137 .modulemode = MODULEMODE_HWCTRL,
5138 },
5139 },
5140 .opt_clks = usb_otg_hs_opt_clks,
5141 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
5142 .slaves = omap44xx_usb_otg_hs_slaves,
5143 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
5144 .masters = omap44xx_usb_otg_hs_masters,
5145 .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
5146 };
5147
5148 /*
5149 * 'wd_timer' class
5150 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
5151 * overflow condition
5152 */
5153
5154 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
5155 .rev_offs = 0x0000,
5156 .sysc_offs = 0x0010,
5157 .syss_offs = 0x0014,
5158 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
5159 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5160 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5161 SIDLE_SMART_WKUP),
5162 .sysc_fields = &omap_hwmod_sysc_type1,
5163 };
5164
5165 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
5166 .name = "wd_timer",
5167 .sysc = &omap44xx_wd_timer_sysc,
5168 .pre_shutdown = &omap2_wd_timer_disable,
5169 };
5170
5171 /* wd_timer2 */
5172 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
5173 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
5174 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
5175 { .irq = -1 }
5176 };
5177
5178 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5179 {
5180 .pa_start = 0x4a314000,
5181 .pa_end = 0x4a31407f,
5182 .flags = ADDR_TYPE_RT
5183 },
5184 { }
5185 };
5186
5187 /* l4_wkup -> wd_timer2 */
5188 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5189 .master = &omap44xx_l4_wkup_hwmod,
5190 .slave = &omap44xx_wd_timer2_hwmod,
5191 .clk = "l4_wkup_clk_mux_ck",
5192 .addr = omap44xx_wd_timer2_addrs,
5193 .user = OCP_USER_MPU | OCP_USER_SDMA,
5194 };
5195
5196 /* wd_timer2 slave ports */
5197 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
5198 &omap44xx_l4_wkup__wd_timer2,
5199 };
5200
5201 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
5202 .name = "wd_timer2",
5203 .class = &omap44xx_wd_timer_hwmod_class,
5204 .clkdm_name = "l4_wkup_clkdm",
5205 .mpu_irqs = omap44xx_wd_timer2_irqs,
5206 .main_clk = "wd_timer2_fck",
5207 .prcm = {
5208 .omap4 = {
5209 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
5210 .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
5211 .modulemode = MODULEMODE_SWCTRL,
5212 },
5213 },
5214 .slaves = omap44xx_wd_timer2_slaves,
5215 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
5216 };
5217
5218 /* wd_timer3 */
5219 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
5220 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
5221 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
5222 { .irq = -1 }
5223 };
5224
5225 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5226 {
5227 .pa_start = 0x40130000,
5228 .pa_end = 0x4013007f,
5229 .flags = ADDR_TYPE_RT
5230 },
5231 { }
5232 };
5233
5234 /* l4_abe -> wd_timer3 */
5235 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5236 .master = &omap44xx_l4_abe_hwmod,
5237 .slave = &omap44xx_wd_timer3_hwmod,
5238 .clk = "ocp_abe_iclk",
5239 .addr = omap44xx_wd_timer3_addrs,
5240 .user = OCP_USER_MPU,
5241 };
5242
5243 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5244 {
5245 .pa_start = 0x49030000,
5246 .pa_end = 0x4903007f,
5247 .flags = ADDR_TYPE_RT
5248 },
5249 { }
5250 };
5251
5252 /* l4_abe -> wd_timer3 (dma) */
5253 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5254 .master = &omap44xx_l4_abe_hwmod,
5255 .slave = &omap44xx_wd_timer3_hwmod,
5256 .clk = "ocp_abe_iclk",
5257 .addr = omap44xx_wd_timer3_dma_addrs,
5258 .user = OCP_USER_SDMA,
5259 };
5260
5261 /* wd_timer3 slave ports */
5262 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5263 &omap44xx_l4_abe__wd_timer3,
5264 &omap44xx_l4_abe__wd_timer3_dma,
5265 };
5266
5267 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5268 .name = "wd_timer3",
5269 .class = &omap44xx_wd_timer_hwmod_class,
5270 .clkdm_name = "abe_clkdm",
5271 .mpu_irqs = omap44xx_wd_timer3_irqs,
5272 .main_clk = "wd_timer3_fck",
5273 .prcm = {
5274 .omap4 = {
5275 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
5276 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
5277 .modulemode = MODULEMODE_SWCTRL,
5278 },
5279 },
5280 .slaves = omap44xx_wd_timer3_slaves,
5281 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
5282 };
5283
5284 /*
5285 * 'usb_host_hs' class
5286 * high-speed multi-port usb host controller
5287 */
5288 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
5289 .master = &omap44xx_usb_host_hs_hwmod,
5290 .slave = &omap44xx_l3_main_2_hwmod,
5291 .clk = "l3_div_ck",
5292 .user = OCP_USER_MPU | OCP_USER_SDMA,
5293 };
5294
5295 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
5296 .rev_offs = 0x0000,
5297 .sysc_offs = 0x0010,
5298 .syss_offs = 0x0014,
5299 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
5300 SYSC_HAS_SOFTRESET),
5301 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5302 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5303 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
5304 .sysc_fields = &omap_hwmod_sysc_type2,
5305 };
5306
5307 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
5308 .name = "usb_host_hs",
5309 .sysc = &omap44xx_usb_host_hs_sysc,
5310 };
5311
5312 static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = {
5313 &omap44xx_usb_host_hs__l3_main_2,
5314 };
5315
5316 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
5317 {
5318 .name = "uhh",
5319 .pa_start = 0x4a064000,
5320 .pa_end = 0x4a0647ff,
5321 .flags = ADDR_TYPE_RT
5322 },
5323 {
5324 .name = "ohci",
5325 .pa_start = 0x4a064800,
5326 .pa_end = 0x4a064bff,
5327 },
5328 {
5329 .name = "ehci",
5330 .pa_start = 0x4a064c00,
5331 .pa_end = 0x4a064fff,
5332 },
5333 {}
5334 };
5335
5336 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
5337 { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
5338 { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
5339 { .irq = -1 }
5340 };
5341
5342 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5343 .master = &omap44xx_l4_cfg_hwmod,
5344 .slave = &omap44xx_usb_host_hs_hwmod,
5345 .clk = "l4_div_ck",
5346 .addr = omap44xx_usb_host_hs_addrs,
5347 .user = OCP_USER_MPU | OCP_USER_SDMA,
5348 };
5349
5350 static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = {
5351 &omap44xx_l4_cfg__usb_host_hs,
5352 };
5353
5354 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
5355 .name = "usb_host_hs",
5356 .class = &omap44xx_usb_host_hs_hwmod_class,
5357 .clkdm_name = "l3_init_clkdm",
5358 .main_clk = "usb_host_hs_fck",
5359 .prcm = {
5360 .omap4 = {
5361 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
5362 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
5363 .modulemode = MODULEMODE_SWCTRL,
5364 },
5365 },
5366 .mpu_irqs = omap44xx_usb_host_hs_irqs,
5367 .slaves = omap44xx_usb_host_hs_slaves,
5368 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_slaves),
5369 .masters = omap44xx_usb_host_hs_masters,
5370 .masters_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_masters),
5371
5372 /*
5373 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
5374 * id: i660
5375 *
5376 * Description:
5377 * In the following configuration :
5378 * - USBHOST module is set to smart-idle mode
5379 * - PRCM asserts idle_req to the USBHOST module ( This typically
5380 * happens when the system is going to a low power mode : all ports
5381 * have been suspended, the master part of the USBHOST module has
5382 * entered the standby state, and SW has cut the functional clocks)
5383 * - an USBHOST interrupt occurs before the module is able to answer
5384 * idle_ack, typically a remote wakeup IRQ.
5385 * Then the USB HOST module will enter a deadlock situation where it
5386 * is no more accessible nor functional.
5387 *
5388 * Workaround:
5389 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
5390 */
5391
5392 /*
5393 * Errata: USB host EHCI may stall when entering smart-standby mode
5394 * Id: i571
5395 *
5396 * Description:
5397 * When the USBHOST module is set to smart-standby mode, and when it is
5398 * ready to enter the standby state (i.e. all ports are suspended and
5399 * all attached devices are in suspend mode), then it can wrongly assert
5400 * the Mstandby signal too early while there are still some residual OCP
5401 * transactions ongoing. If this condition occurs, the internal state
5402 * machine may go to an undefined state and the USB link may be stuck
5403 * upon the next resume.
5404 *
5405 * Workaround:
5406 * Don't use smart standby; use only force standby,
5407 * hence HWMOD_SWSUP_MSTANDBY
5408 */
5409
5410 /*
5411 * During system boot; If the hwmod framework resets the module
5412 * the module will have smart idle settings; which can lead to deadlock
5413 * (above Errata Id:i660); so, dont reset the module during boot;
5414 * Use HWMOD_INIT_NO_RESET.
5415 */
5416
5417 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
5418 HWMOD_INIT_NO_RESET,
5419 };
5420
5421 /*
5422 * 'usb_tll_hs' class
5423 * usb_tll_hs module is the adapter on the usb_host_hs ports
5424 */
5425 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
5426 .rev_offs = 0x0000,
5427 .sysc_offs = 0x0010,
5428 .syss_offs = 0x0014,
5429 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
5430 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
5431 SYSC_HAS_AUTOIDLE),
5432 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
5433 .sysc_fields = &omap_hwmod_sysc_type1,
5434 };
5435
5436 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
5437 .name = "usb_tll_hs",
5438 .sysc = &omap44xx_usb_tll_hs_sysc,
5439 };
5440
5441 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
5442 { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
5443 { .irq = -1 }
5444 };
5445
5446 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
5447 {
5448 .name = "tll",
5449 .pa_start = 0x4a062000,
5450 .pa_end = 0x4a063fff,
5451 .flags = ADDR_TYPE_RT
5452 },
5453 {}
5454 };
5455
5456 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5457 .master = &omap44xx_l4_cfg_hwmod,
5458 .slave = &omap44xx_usb_tll_hs_hwmod,
5459 .clk = "l4_div_ck",
5460 .addr = omap44xx_usb_tll_hs_addrs,
5461 .user = OCP_USER_MPU | OCP_USER_SDMA,
5462 };
5463
5464 static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = {
5465 &omap44xx_l4_cfg__usb_tll_hs,
5466 };
5467
5468 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
5469 .name = "usb_tll_hs",
5470 .class = &omap44xx_usb_tll_hs_hwmod_class,
5471 .clkdm_name = "l3_init_clkdm",
5472 .main_clk = "usb_tll_hs_ick",
5473 .prcm = {
5474 .omap4 = {
5475 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
5476 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
5477 .modulemode = MODULEMODE_HWCTRL,
5478 },
5479 },
5480 .mpu_irqs = omap44xx_usb_tll_hs_irqs,
5481 .slaves = omap44xx_usb_tll_hs_slaves,
5482 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves),
5483 };
5484
5485 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5486
5487 /* dmm class */
5488 &omap44xx_dmm_hwmod,
5489
5490 /* emif_fw class */
5491 &omap44xx_emif_fw_hwmod,
5492
5493 /* l3 class */
5494 &omap44xx_l3_instr_hwmod,
5495 &omap44xx_l3_main_1_hwmod,
5496 &omap44xx_l3_main_2_hwmod,
5497 &omap44xx_l3_main_3_hwmod,
5498
5499 /* l4 class */
5500 &omap44xx_l4_abe_hwmod,
5501 &omap44xx_l4_cfg_hwmod,
5502 &omap44xx_l4_per_hwmod,
5503 &omap44xx_l4_wkup_hwmod,
5504
5505 /* mpu_bus class */
5506 &omap44xx_mpu_private_hwmod,
5507
5508 /* aess class */
5509 /* &omap44xx_aess_hwmod, */
5510
5511 /* bandgap class */
5512 &omap44xx_bandgap_hwmod,
5513
5514 /* counter class */
5515 /* &omap44xx_counter_32k_hwmod, */
5516
5517 /* dma class */
5518 &omap44xx_dma_system_hwmod,
5519
5520 /* dmic class */
5521 &omap44xx_dmic_hwmod,
5522
5523 /* dsp class */
5524 &omap44xx_dsp_hwmod,
5525 &omap44xx_dsp_c0_hwmod,
5526
5527 /* dss class */
5528 &omap44xx_dss_hwmod,
5529 &omap44xx_dss_dispc_hwmod,
5530 &omap44xx_dss_dsi1_hwmod,
5531 &omap44xx_dss_dsi2_hwmod,
5532 &omap44xx_dss_hdmi_hwmod,
5533 &omap44xx_dss_rfbi_hwmod,
5534 &omap44xx_dss_venc_hwmod,
5535
5536 /* gpio class */
5537 &omap44xx_gpio1_hwmod,
5538 &omap44xx_gpio2_hwmod,
5539 &omap44xx_gpio3_hwmod,
5540 &omap44xx_gpio4_hwmod,
5541 &omap44xx_gpio5_hwmod,
5542 &omap44xx_gpio6_hwmod,
5543
5544 /* hsi class */
5545 /* &omap44xx_hsi_hwmod, */
5546
5547 /* i2c class */
5548 &omap44xx_i2c1_hwmod,
5549 &omap44xx_i2c2_hwmod,
5550 &omap44xx_i2c3_hwmod,
5551 &omap44xx_i2c4_hwmod,
5552
5553 /* ipu class */
5554 &omap44xx_ipu_hwmod,
5555 &omap44xx_ipu_c0_hwmod,
5556 &omap44xx_ipu_c1_hwmod,
5557
5558 /* iss class */
5559 /* &omap44xx_iss_hwmod, */
5560
5561 /* iva class */
5562 &omap44xx_iva_hwmod,
5563 &omap44xx_iva_seq0_hwmod,
5564 &omap44xx_iva_seq1_hwmod,
5565
5566 /* kbd class */
5567 &omap44xx_kbd_hwmod,
5568
5569 /* mailbox class */
5570 &omap44xx_mailbox_hwmod,
5571
5572 /* mcbsp class */
5573 &omap44xx_mcbsp1_hwmod,
5574 &omap44xx_mcbsp2_hwmod,
5575 &omap44xx_mcbsp3_hwmod,
5576 &omap44xx_mcbsp4_hwmod,
5577
5578 /* mcpdm class */
5579 &omap44xx_mcpdm_hwmod,
5580
5581 /* mcspi class */
5582 &omap44xx_mcspi1_hwmod,
5583 &omap44xx_mcspi2_hwmod,
5584 &omap44xx_mcspi3_hwmod,
5585 &omap44xx_mcspi4_hwmod,
5586
5587 /* mmc class */
5588 &omap44xx_mmc1_hwmod,
5589 &omap44xx_mmc2_hwmod,
5590 &omap44xx_mmc3_hwmod,
5591 &omap44xx_mmc4_hwmod,
5592 &omap44xx_mmc5_hwmod,
5593
5594 /* mpu class */
5595 &omap44xx_mpu_hwmod,
5596
5597 /* smartreflex class */
5598 &omap44xx_smartreflex_core_hwmod,
5599 &omap44xx_smartreflex_iva_hwmod,
5600 &omap44xx_smartreflex_mpu_hwmod,
5601
5602 /* spinlock class */
5603 &omap44xx_spinlock_hwmod,
5604
5605 /* timer class */
5606 &omap44xx_timer1_hwmod,
5607 &omap44xx_timer2_hwmod,
5608 &omap44xx_timer3_hwmod,
5609 &omap44xx_timer4_hwmod,
5610 &omap44xx_timer5_hwmod,
5611 &omap44xx_timer6_hwmod,
5612 &omap44xx_timer7_hwmod,
5613 &omap44xx_timer8_hwmod,
5614 &omap44xx_timer9_hwmod,
5615 &omap44xx_timer10_hwmod,
5616 &omap44xx_timer11_hwmod,
5617
5618 /* uart class */
5619 &omap44xx_uart1_hwmod,
5620 &omap44xx_uart2_hwmod,
5621 &omap44xx_uart3_hwmod,
5622 &omap44xx_uart4_hwmod,
5623
5624 /* usb host class */
5625 &omap44xx_usb_host_hs_hwmod,
5626 &omap44xx_usb_tll_hs_hwmod,
5627
5628 /* usb_otg_hs class */
5629 &omap44xx_usb_otg_hs_hwmod,
5630
5631 /* wd_timer class */
5632 &omap44xx_wd_timer2_hwmod,
5633 &omap44xx_wd_timer3_hwmod,
5634 NULL,
5635 };
5636
omap44xx_hwmod_init(void)5637 int __init omap44xx_hwmod_init(void)
5638 {
5639 return omap_hwmod_register(omap44xx_hwmods);
5640 }
5641
5642