1 /*
2 * linux/arch/arm/mach-omap2/irq.c
3 *
4 * Interrupt handler for OMAP2 boards.
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <mach/hardware.h>
18 #include <asm/exception.h>
19 #include <asm/mach/irq.h>
20
21
22 /* selected INTC register offsets */
23
24 #define INTC_REVISION 0x0000
25 #define INTC_SYSCONFIG 0x0010
26 #define INTC_SYSSTATUS 0x0014
27 #define INTC_SIR 0x0040
28 #define INTC_CONTROL 0x0048
29 #define INTC_PROTECTION 0x004C
30 #define INTC_IDLE 0x0050
31 #define INTC_THRESHOLD 0x0068
32 #define INTC_MIR0 0x0084
33 #define INTC_MIR_CLEAR0 0x0088
34 #define INTC_MIR_SET0 0x008c
35 #define INTC_PENDING_IRQ0 0x0098
36 /* Number of IRQ state bits in each MIR register */
37 #define IRQ_BITS_PER_REG 32
38
39 #define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
40 #define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
41 #define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */
42 #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
43
44 /*
45 * OMAP2 has a number of different interrupt controllers, each interrupt
46 * controller is identified as its own "bank". Register definitions are
47 * fairly consistent for each bank, but not all registers are implemented
48 * for each bank.. when in doubt, consult the TRM.
49 */
50 static struct omap_irq_bank {
51 void __iomem *base_reg;
52 unsigned int nr_irqs;
53 } __attribute__ ((aligned(4))) irq_banks[] = {
54 {
55 /* MPU INTC */
56 .nr_irqs = 96,
57 },
58 };
59
60 /* Structure to save interrupt controller context */
61 struct omap3_intc_regs {
62 u32 sysconfig;
63 u32 protection;
64 u32 idle;
65 u32 threshold;
66 u32 ilr[INTCPS_NR_IRQS];
67 u32 mir[INTCPS_NR_MIR_REGS];
68 };
69
70 /* INTC bank register get/set */
71
intc_bank_write_reg(u32 val,struct omap_irq_bank * bank,u16 reg)72 static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
73 {
74 __raw_writel(val, bank->base_reg + reg);
75 }
76
intc_bank_read_reg(struct omap_irq_bank * bank,u16 reg)77 static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
78 {
79 return __raw_readl(bank->base_reg + reg);
80 }
81
82 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
omap_ack_irq(struct irq_data * d)83 static void omap_ack_irq(struct irq_data *d)
84 {
85 intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
86 }
87
omap_mask_ack_irq(struct irq_data * d)88 static void omap_mask_ack_irq(struct irq_data *d)
89 {
90 irq_gc_mask_disable_reg(d);
91 omap_ack_irq(d);
92 }
93
omap_irq_bank_init_one(struct omap_irq_bank * bank)94 static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
95 {
96 unsigned long tmp;
97
98 tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
99 printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
100 "(revision %ld.%ld) with %d interrupts\n",
101 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
102
103 tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
104 tmp |= 1 << 1; /* soft reset */
105 intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
106
107 while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
108 /* Wait for reset to complete */;
109
110 /* Enable autoidle */
111 intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
112 }
113
omap_irq_pending(void)114 int omap_irq_pending(void)
115 {
116 int i;
117
118 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
119 struct omap_irq_bank *bank = irq_banks + i;
120 int irq;
121
122 for (irq = 0; irq < bank->nr_irqs; irq += 32)
123 if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
124 ((irq >> 5) << 5)))
125 return 1;
126 }
127 return 0;
128 }
129
130 static __init void
omap_alloc_gc(void __iomem * base,unsigned int irq_start,unsigned int num)131 omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
132 {
133 struct irq_chip_generic *gc;
134 struct irq_chip_type *ct;
135
136 gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
137 handle_level_irq);
138 ct = gc->chip_types;
139 ct->chip.irq_ack = omap_mask_ack_irq;
140 ct->chip.irq_mask = irq_gc_mask_disable_reg;
141 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
142
143 ct->regs.ack = INTC_CONTROL;
144 ct->regs.enable = INTC_MIR_CLEAR0;
145 ct->regs.disable = INTC_MIR_SET0;
146 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
147 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
148 }
149
omap_init_irq(u32 base,int nr_irqs)150 static void __init omap_init_irq(u32 base, int nr_irqs)
151 {
152 void __iomem *omap_irq_base;
153 unsigned long nr_of_irqs = 0;
154 unsigned int nr_banks = 0;
155 int i, j;
156
157 omap_irq_base = ioremap(base, SZ_4K);
158 if (WARN_ON(!omap_irq_base))
159 return;
160
161 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
162 struct omap_irq_bank *bank = irq_banks + i;
163
164 bank->nr_irqs = nr_irqs;
165
166 /* Static mapping, never released */
167 bank->base_reg = ioremap(base, SZ_4K);
168 if (!bank->base_reg) {
169 printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
170 continue;
171 }
172
173 omap_irq_bank_init_one(bank);
174
175 for (j = 0; j < bank->nr_irqs; j += 32)
176 omap_alloc_gc(bank->base_reg + j, j, 32);
177
178 nr_of_irqs += bank->nr_irqs;
179 nr_banks++;
180 }
181
182 printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
183 nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
184 }
185
omap2_init_irq(void)186 void __init omap2_init_irq(void)
187 {
188 omap_init_irq(OMAP24XX_IC_BASE, 96);
189 }
190
omap3_init_irq(void)191 void __init omap3_init_irq(void)
192 {
193 omap_init_irq(OMAP34XX_IC_BASE, 96);
194 }
195
ti81xx_init_irq(void)196 void __init ti81xx_init_irq(void)
197 {
198 omap_init_irq(OMAP34XX_IC_BASE, 128);
199 }
200
omap_intc_handle_irq(void __iomem * base_addr,struct pt_regs * regs)201 static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
202 {
203 u32 irqnr;
204
205 do {
206 irqnr = readl_relaxed(base_addr + 0x98);
207 if (irqnr)
208 goto out;
209
210 irqnr = readl_relaxed(base_addr + 0xb8);
211 if (irqnr)
212 goto out;
213
214 irqnr = readl_relaxed(base_addr + 0xd8);
215 #ifdef CONFIG_SOC_OMAPTI816X
216 if (irqnr)
217 goto out;
218 irqnr = readl_relaxed(base_addr + 0xf8);
219 #endif
220
221 out:
222 if (!irqnr)
223 break;
224
225 irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
226 irqnr &= ACTIVEIRQ_MASK;
227
228 if (irqnr)
229 handle_IRQ(irqnr, regs);
230 } while (irqnr);
231 }
232
omap2_intc_handle_irq(struct pt_regs * regs)233 asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
234 {
235 void __iomem *base_addr = OMAP2_IRQ_BASE;
236 omap_intc_handle_irq(base_addr, regs);
237 }
238
239 #ifdef CONFIG_ARCH_OMAP3
240 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
241
omap_intc_save_context(void)242 void omap_intc_save_context(void)
243 {
244 int ind = 0, i = 0;
245 for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
246 struct omap_irq_bank *bank = irq_banks + ind;
247 intc_context[ind].sysconfig =
248 intc_bank_read_reg(bank, INTC_SYSCONFIG);
249 intc_context[ind].protection =
250 intc_bank_read_reg(bank, INTC_PROTECTION);
251 intc_context[ind].idle =
252 intc_bank_read_reg(bank, INTC_IDLE);
253 intc_context[ind].threshold =
254 intc_bank_read_reg(bank, INTC_THRESHOLD);
255 for (i = 0; i < INTCPS_NR_IRQS; i++)
256 intc_context[ind].ilr[i] =
257 intc_bank_read_reg(bank, (0x100 + 0x4*i));
258 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
259 intc_context[ind].mir[i] =
260 intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
261 (0x20 * i));
262 }
263 }
264
omap_intc_restore_context(void)265 void omap_intc_restore_context(void)
266 {
267 int ind = 0, i = 0;
268
269 for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
270 struct omap_irq_bank *bank = irq_banks + ind;
271 intc_bank_write_reg(intc_context[ind].sysconfig,
272 bank, INTC_SYSCONFIG);
273 intc_bank_write_reg(intc_context[ind].sysconfig,
274 bank, INTC_SYSCONFIG);
275 intc_bank_write_reg(intc_context[ind].protection,
276 bank, INTC_PROTECTION);
277 intc_bank_write_reg(intc_context[ind].idle,
278 bank, INTC_IDLE);
279 intc_bank_write_reg(intc_context[ind].threshold,
280 bank, INTC_THRESHOLD);
281 for (i = 0; i < INTCPS_NR_IRQS; i++)
282 intc_bank_write_reg(intc_context[ind].ilr[i],
283 bank, (0x100 + 0x4*i));
284 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
285 intc_bank_write_reg(intc_context[ind].mir[i],
286 &irq_banks[0], INTC_MIR0 + (0x20 * i));
287 }
288 /* MIRs are saved and restore with other PRCM registers */
289 }
290
omap3_intc_suspend(void)291 void omap3_intc_suspend(void)
292 {
293 /* A pending interrupt would prevent OMAP from entering suspend */
294 omap_ack_irq(0);
295 }
296
omap3_intc_prepare_idle(void)297 void omap3_intc_prepare_idle(void)
298 {
299 /*
300 * Disable autoidle as it can stall interrupt controller,
301 * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
302 */
303 intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
304 }
305
omap3_intc_resume_idle(void)306 void omap3_intc_resume_idle(void)
307 {
308 /* Re-enable autoidle */
309 intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
310 }
311
omap3_intc_handle_irq(struct pt_regs * regs)312 asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
313 {
314 void __iomem *base_addr = OMAP3_IRQ_BASE;
315 omap_intc_handle_irq(base_addr, regs);
316 }
317 #endif /* CONFIG_ARCH_OMAP3 */
318