1 /*
2 * OMAP2/3/4 DPLL clock functions
3 *
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15 #undef DEBUG
16
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/clk.h>
20 #include <linux/io.h>
21
22 #include <asm/div64.h>
23
24 #include <plat/clock.h>
25
26 #include "clock.h"
27 #include "cm-regbits-24xx.h"
28 #include "cm-regbits-34xx.h"
29
30 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
31 #define DPLL_MIN_MULTIPLIER 2
32 #define DPLL_MIN_DIVIDER 1
33
34 /* Possible error results from _dpll_test_mult */
35 #define DPLL_MULT_UNDERFLOW -1
36
37 /*
38 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
39 * The higher the scale factor, the greater the risk of arithmetic overflow,
40 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
41 * must be a power of DPLL_SCALE_BASE.
42 */
43 #define DPLL_SCALE_FACTOR 64
44 #define DPLL_SCALE_BASE 2
45 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
46 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
47
48 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
49 #define OMAP3430_DPLL_FINT_BAND1_MIN 750000
50 #define OMAP3430_DPLL_FINT_BAND1_MAX 2100000
51 #define OMAP3430_DPLL_FINT_BAND2_MIN 7500000
52 #define OMAP3430_DPLL_FINT_BAND2_MAX 21000000
53
54 /*
55 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
56 * From device data manual section 4.3 "DPLL and DLL Specifications".
57 */
58 #define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000
59 #define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000
60 #define OMAP3PLUS_DPLL_FINT_MIN 32000
61 #define OMAP3PLUS_DPLL_FINT_MAX 52000000
62
63 /* _dpll_test_fint() return codes */
64 #define DPLL_FINT_UNDERFLOW -1
65 #define DPLL_FINT_INVALID -2
66
67 /* Private functions */
68
69 /*
70 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
71 * @clk: DPLL struct clk to test
72 * @n: divider value (N) to test
73 *
74 * Tests whether a particular divider @n will result in a valid DPLL
75 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
76 * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
77 * (assuming that it is counting N upwards), or -2 if the enclosing loop
78 * should skip to the next iteration (again assuming N is increasing).
79 */
_dpll_test_fint(struct clk * clk,u8 n)80 static int _dpll_test_fint(struct clk *clk, u8 n)
81 {
82 struct dpll_data *dd;
83 long fint, fint_min, fint_max;
84 int ret = 0;
85
86 dd = clk->dpll_data;
87
88 /* DPLL divider must result in a valid jitter correction val */
89 fint = clk->parent->rate / n;
90
91 if (cpu_is_omap24xx()) {
92 /* Should not be called for OMAP2, so warn if it is called */
93 WARN(1, "No fint limits available for OMAP2!\n");
94 return DPLL_FINT_INVALID;
95 } else if (cpu_is_omap3430()) {
96 fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
97 fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
98 } else if (dd->flags & DPLL_J_TYPE) {
99 fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
100 fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
101 } else {
102 fint_min = OMAP3PLUS_DPLL_FINT_MIN;
103 fint_max = OMAP3PLUS_DPLL_FINT_MAX;
104 }
105
106 if (fint < fint_min) {
107 pr_debug("rejecting n=%d due to Fint failure, "
108 "lowering max_divider\n", n);
109 dd->max_divider = n;
110 ret = DPLL_FINT_UNDERFLOW;
111 } else if (fint > fint_max) {
112 pr_debug("rejecting n=%d due to Fint failure, "
113 "boosting min_divider\n", n);
114 dd->min_divider = n;
115 ret = DPLL_FINT_INVALID;
116 } else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX &&
117 fint < OMAP3430_DPLL_FINT_BAND2_MIN) {
118 pr_debug("rejecting n=%d due to Fint failure\n", n);
119 ret = DPLL_FINT_INVALID;
120 }
121
122 return ret;
123 }
124
_dpll_compute_new_rate(unsigned long parent_rate,unsigned int m,unsigned int n)125 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
126 unsigned int m, unsigned int n)
127 {
128 unsigned long long num;
129
130 num = (unsigned long long)parent_rate * m;
131 do_div(num, n);
132 return num;
133 }
134
135 /*
136 * _dpll_test_mult - test a DPLL multiplier value
137 * @m: pointer to the DPLL m (multiplier) value under test
138 * @n: current DPLL n (divider) value under test
139 * @new_rate: pointer to storage for the resulting rounded rate
140 * @target_rate: the desired DPLL rate
141 * @parent_rate: the DPLL's parent clock rate
142 *
143 * This code tests a DPLL multiplier value, ensuring that the
144 * resulting rate will not be higher than the target_rate, and that
145 * the multiplier value itself is valid for the DPLL. Initially, the
146 * integer pointed to by the m argument should be prescaled by
147 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
148 * a non-scaled m upon return. This non-scaled m will result in a
149 * new_rate as close as possible to target_rate (but not greater than
150 * target_rate) given the current (parent_rate, n, prescaled m)
151 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
152 * non-scaled m attempted to underflow, which can allow the calling
153 * function to bail out early; or 0 upon success.
154 */
_dpll_test_mult(int * m,int n,unsigned long * new_rate,unsigned long target_rate,unsigned long parent_rate)155 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
156 unsigned long target_rate,
157 unsigned long parent_rate)
158 {
159 int r = 0, carry = 0;
160
161 /* Unscale m and round if necessary */
162 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
163 carry = 1;
164 *m = (*m / DPLL_SCALE_FACTOR) + carry;
165
166 /*
167 * The new rate must be <= the target rate to avoid programming
168 * a rate that is impossible for the hardware to handle
169 */
170 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
171 if (*new_rate > target_rate) {
172 (*m)--;
173 *new_rate = 0;
174 }
175
176 /* Guard against m underflow */
177 if (*m < DPLL_MIN_MULTIPLIER) {
178 *m = DPLL_MIN_MULTIPLIER;
179 *new_rate = 0;
180 r = DPLL_MULT_UNDERFLOW;
181 }
182
183 if (*new_rate == 0)
184 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
185
186 return r;
187 }
188
189 /* Public functions */
190
omap2_init_dpll_parent(struct clk * clk)191 void omap2_init_dpll_parent(struct clk *clk)
192 {
193 u32 v;
194 struct dpll_data *dd;
195
196 dd = clk->dpll_data;
197 if (!dd)
198 return;
199
200 v = __raw_readl(dd->control_reg);
201 v &= dd->enable_mask;
202 v >>= __ffs(dd->enable_mask);
203
204 /* Reparent the struct clk in case the dpll is in bypass */
205 if (cpu_is_omap24xx()) {
206 if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
207 v == OMAP2XXX_EN_DPLL_FRBYPASS)
208 clk_reparent(clk, dd->clk_bypass);
209 } else if (cpu_is_omap34xx()) {
210 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
211 v == OMAP3XXX_EN_DPLL_FRBYPASS)
212 clk_reparent(clk, dd->clk_bypass);
213 } else if (cpu_is_omap44xx()) {
214 if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
215 v == OMAP4XXX_EN_DPLL_FRBYPASS ||
216 v == OMAP4XXX_EN_DPLL_MNBYPASS)
217 clk_reparent(clk, dd->clk_bypass);
218 }
219 return;
220 }
221
222 /**
223 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
224 * @clk: struct clk * of a DPLL
225 *
226 * DPLLs can be locked or bypassed - basically, enabled or disabled.
227 * When locked, the DPLL output depends on the M and N values. When
228 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
229 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
230 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
231 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
232 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
233 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
234 * if the clock @clk is not a DPLL.
235 */
omap2_get_dpll_rate(struct clk * clk)236 u32 omap2_get_dpll_rate(struct clk *clk)
237 {
238 long long dpll_clk;
239 u32 dpll_mult, dpll_div, v;
240 struct dpll_data *dd;
241
242 dd = clk->dpll_data;
243 if (!dd)
244 return 0;
245
246 /* Return bypass rate if DPLL is bypassed */
247 v = __raw_readl(dd->control_reg);
248 v &= dd->enable_mask;
249 v >>= __ffs(dd->enable_mask);
250
251 if (cpu_is_omap24xx()) {
252 if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
253 v == OMAP2XXX_EN_DPLL_FRBYPASS)
254 return dd->clk_bypass->rate;
255 } else if (cpu_is_omap34xx()) {
256 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
257 v == OMAP3XXX_EN_DPLL_FRBYPASS)
258 return dd->clk_bypass->rate;
259 } else if (cpu_is_omap44xx()) {
260 if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
261 v == OMAP4XXX_EN_DPLL_FRBYPASS ||
262 v == OMAP4XXX_EN_DPLL_MNBYPASS)
263 return dd->clk_bypass->rate;
264 }
265
266 v = __raw_readl(dd->mult_div1_reg);
267 dpll_mult = v & dd->mult_mask;
268 dpll_mult >>= __ffs(dd->mult_mask);
269 dpll_div = v & dd->div1_mask;
270 dpll_div >>= __ffs(dd->div1_mask);
271
272 dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
273 do_div(dpll_clk, dpll_div + 1);
274
275 return dpll_clk;
276 }
277
278 /* DPLL rate rounding code */
279
280 /**
281 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
282 * @clk: struct clk * for a DPLL
283 * @target_rate: desired DPLL clock rate
284 *
285 * Given a DPLL and a desired target rate, round the target rate to a
286 * possible, programmable rate for this DPLL. Attempts to select the
287 * minimum possible n. Stores the computed (m, n) in the DPLL's
288 * dpll_data structure so set_rate() will not need to call this
289 * (expensive) function again. Returns ~0 if the target rate cannot
290 * be rounded, or the rounded rate upon success.
291 */
omap2_dpll_round_rate(struct clk * clk,unsigned long target_rate)292 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
293 {
294 int m, n, r, scaled_max_m;
295 unsigned long scaled_rt_rp;
296 unsigned long new_rate = 0;
297 struct dpll_data *dd;
298
299 if (!clk || !clk->dpll_data)
300 return ~0;
301
302 dd = clk->dpll_data;
303
304 pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
305 clk->name, target_rate);
306
307 scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
308 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
309
310 dd->last_rounded_rate = 0;
311
312 for (n = dd->min_divider; n <= dd->max_divider; n++) {
313
314 /* Is the (input clk, divider) pair valid for the DPLL? */
315 r = _dpll_test_fint(clk, n);
316 if (r == DPLL_FINT_UNDERFLOW)
317 break;
318 else if (r == DPLL_FINT_INVALID)
319 continue;
320
321 /* Compute the scaled DPLL multiplier, based on the divider */
322 m = scaled_rt_rp * n;
323
324 /*
325 * Since we're counting n up, a m overflow means we
326 * can bail out completely (since as n increases in
327 * the next iteration, there's no way that m can
328 * increase beyond the current m)
329 */
330 if (m > scaled_max_m)
331 break;
332
333 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
334 dd->clk_ref->rate);
335
336 /* m can't be set low enough for this n - try with a larger n */
337 if (r == DPLL_MULT_UNDERFLOW)
338 continue;
339
340 pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
341 clk->name, m, n, new_rate);
342
343 if (target_rate == new_rate) {
344 dd->last_rounded_m = m;
345 dd->last_rounded_n = n;
346 dd->last_rounded_rate = target_rate;
347 break;
348 }
349 }
350
351 if (target_rate != new_rate) {
352 pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
353 target_rate);
354 return ~0;
355 }
356
357 return target_rate;
358 }
359
360