1 /* Copyright (c) 2010 Code Aurora Forum. All rights reserved. 2 * 3 * This software is licensed under the terms of the GNU General Public 4 * License version 2, as published by the Free Software Foundation, and 5 * may be copied, distributed, and modified under those terms. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 * 12 */ 13 14 #ifndef __ASM_ARCH_MSM_IRQS_8X60_H 15 #define __ASM_ARCH_MSM_IRQS_8X60_H 16 17 /* MSM ACPU Interrupt Numbers */ 18 19 /* 0-15: STI/SGI (software triggered/generated interrupts) 20 * 16-31: PPI (private peripheral interrupts) 21 * 32+: SPI (shared peripheral interrupts) 22 */ 23 24 #define GIC_PPI_START 16 25 #define GIC_SPI_START 32 26 27 #define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 0) 28 #define INT_GP_TIMER_EXP (GIC_PPI_START + 1) 29 #define INT_GP_TIMER2_EXP (GIC_PPI_START + 2) 30 #define WDT0_ACCSCSSNBARK_INT (GIC_PPI_START + 3) 31 #define WDT1_ACCSCSSNBARK_INT (GIC_PPI_START + 4) 32 #define AVS_SVICINT (GIC_PPI_START + 5) 33 #define AVS_SVICINTSWDONE (GIC_PPI_START + 6) 34 #define CPU_DBGCPUXCOMMRXFULL (GIC_PPI_START + 7) 35 #define CPU_DBGCPUXCOMMTXEMPTY (GIC_PPI_START + 8) 36 #define CPU_SICCPUXPERFMONIRPTREQ (GIC_PPI_START + 9) 37 #define SC_AVSCPUXDOWN (GIC_PPI_START + 10) 38 #define SC_AVSCPUXUP (GIC_PPI_START + 11) 39 #define SC_SICCPUXACGIRPTREQ (GIC_PPI_START + 12) 40 /* PPI 13 to 15 are unused */ 41 42 43 #define SC_SICMPUIRPTREQ (GIC_SPI_START + 0) 44 #define SC_SICL2IRPTREQ (GIC_SPI_START + 1) 45 #define SC_SICL2ACGIRPTREQ (GIC_SPI_START + 2) 46 #define NC (GIC_SPI_START + 3) 47 #define TLMM_SCSS_DIR_CONN_IRQ_0 (GIC_SPI_START + 4) 48 #define TLMM_SCSS_DIR_CONN_IRQ_1 (GIC_SPI_START + 5) 49 #define TLMM_SCSS_DIR_CONN_IRQ_2 (GIC_SPI_START + 6) 50 #define TLMM_SCSS_DIR_CONN_IRQ_3 (GIC_SPI_START + 7) 51 #define TLMM_SCSS_DIR_CONN_IRQ_4 (GIC_SPI_START + 8) 52 #define TLMM_SCSS_DIR_CONN_IRQ_5 (GIC_SPI_START + 9) 53 #define TLMM_SCSS_DIR_CONN_IRQ_6 (GIC_SPI_START + 10) 54 #define TLMM_SCSS_DIR_CONN_IRQ_7 (GIC_SPI_START + 11) 55 #define TLMM_SCSS_DIR_CONN_IRQ_8 (GIC_SPI_START + 12) 56 #define TLMM_SCSS_DIR_CONN_IRQ_9 (GIC_SPI_START + 13) 57 #define PM8058_SEC_IRQ_N (GIC_SPI_START + 14) 58 #define PM8901_SEC_IRQ_N (GIC_SPI_START + 15) 59 #define TLMM_SCSS_SUMMARY_IRQ (GIC_SPI_START + 16) 60 #define SPDM_RT_1_IRQ (GIC_SPI_START + 17) 61 #define SPDM_DIAG_IRQ (GIC_SPI_START + 18) 62 #define RPM_SCSS_CPU0_GP_HIGH_IRQ (GIC_SPI_START + 19) 63 #define RPM_SCSS_CPU0_GP_MEDIUM_IRQ (GIC_SPI_START + 20) 64 #define RPM_SCSS_CPU0_GP_LOW_IRQ (GIC_SPI_START + 21) 65 #define RPM_SCSS_CPU0_WAKE_UP_IRQ (GIC_SPI_START + 22) 66 #define RPM_SCSS_CPU1_GP_HIGH_IRQ (GIC_SPI_START + 23) 67 #define RPM_SCSS_CPU1_GP_MEDIUM_IRQ (GIC_SPI_START + 24) 68 #define RPM_SCSS_CPU1_GP_LOW_IRQ (GIC_SPI_START + 25) 69 #define RPM_SCSS_CPU1_WAKE_UP_IRQ (GIC_SPI_START + 26) 70 #define SSBI2_2_SC_CPU0_SECURE_INT (GIC_SPI_START + 27) 71 #define SSBI2_2_SC_CPU0_NON_SECURE_INT (GIC_SPI_START + 28) 72 #define SSBI2_1_SC_CPU0_SECURE_INT (GIC_SPI_START + 29) 73 #define SSBI2_1_SC_CPU0_NON_SECURE_INT (GIC_SPI_START + 30) 74 #define MSMC_SC_SEC_CE_IRQ (GIC_SPI_START + 31) 75 #define MSMC_SC_PRI_CE_IRQ (GIC_SPI_START + 32) 76 #define MARM_FIQ (GIC_SPI_START + 33) 77 #define MARM_IRQ (GIC_SPI_START + 34) 78 #define MARM_L2CC_IRQ (GIC_SPI_START + 35) 79 #define MARM_WDOG_EXPIRED (GIC_SPI_START + 36) 80 #define MARM_SCSS_GP_IRQ_0 (GIC_SPI_START + 37) 81 #define MARM_SCSS_GP_IRQ_1 (GIC_SPI_START + 38) 82 #define MARM_SCSS_GP_IRQ_2 (GIC_SPI_START + 39) 83 #define MARM_SCSS_GP_IRQ_3 (GIC_SPI_START + 40) 84 #define MARM_SCSS_GP_IRQ_4 (GIC_SPI_START + 41) 85 #define MARM_SCSS_GP_IRQ_5 (GIC_SPI_START + 42) 86 #define MARM_SCSS_GP_IRQ_6 (GIC_SPI_START + 43) 87 #define MARM_SCSS_GP_IRQ_7 (GIC_SPI_START + 44) 88 #define MARM_SCSS_GP_IRQ_8 (GIC_SPI_START + 45) 89 #define MARM_SCSS_GP_IRQ_9 (GIC_SPI_START + 46) 90 #define VPE_IRQ (GIC_SPI_START + 47) 91 #define VFE_IRQ (GIC_SPI_START + 48) 92 #define VCODEC_IRQ (GIC_SPI_START + 49) 93 #define TV_ENC_IRQ (GIC_SPI_START + 50) 94 #define SMMU_VPE_CB_SC_SECURE_IRQ (GIC_SPI_START + 51) 95 #define SMMU_VPE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 52) 96 #define SMMU_VFE_CB_SC_SECURE_IRQ (GIC_SPI_START + 53) 97 #define SMMU_VFE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 54) 98 #define SMMU_VCODEC_B_CB_SC_SECURE_IRQ (GIC_SPI_START + 55) 99 #define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 56) 100 #define SMMU_VCODEC_A_CB_SC_SECURE_IRQ (GIC_SPI_START + 57) 101 #define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 58) 102 #define SMMU_ROT_CB_SC_SECURE_IRQ (GIC_SPI_START + 59) 103 #define SMMU_ROT_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 60) 104 #define SMMU_MDP1_CB_SC_SECURE_IRQ (GIC_SPI_START + 61) 105 #define SMMU_MDP1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 62) 106 #define SMMU_MDP0_CB_SC_SECURE_IRQ (GIC_SPI_START + 63) 107 #define SMMU_MDP0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 64) 108 #define SMMU_JPEGD_CB_SC_SECURE_IRQ (GIC_SPI_START + 65) 109 #define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 66) 110 #define SMMU_IJPEG_CB_SC_SECURE_IRQ (GIC_SPI_START + 67) 111 #define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 68) 112 #define SMMU_GFX3D_CB_SC_SECURE_IRQ (GIC_SPI_START + 69) 113 #define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 70) 114 #define SMMU_GFX2D0_CB_SC_SECURE_IRQ (GIC_SPI_START + 71) 115 #define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 72) 116 #define ROT_IRQ (GIC_SPI_START + 73) 117 #define MMSS_FABRIC_IRQ (GIC_SPI_START + 74) 118 #define MDP_IRQ (GIC_SPI_START + 75) 119 #define JPEGD_IRQ (GIC_SPI_START + 76) 120 #define JPEG_IRQ (GIC_SPI_START + 77) 121 #define MMSS_IMEM_IRQ (GIC_SPI_START + 78) 122 #define HDMI_IRQ (GIC_SPI_START + 79) 123 #define GFX3D_IRQ (GIC_SPI_START + 80) 124 #define GFX2D0_IRQ (GIC_SPI_START + 81) 125 #define DSI_IRQ (GIC_SPI_START + 82) 126 #define CSI_1_IRQ (GIC_SPI_START + 83) 127 #define CSI_0_IRQ (GIC_SPI_START + 84) 128 #define LPASS_SCSS_AUDIO_IF_OUT0_IRQ (GIC_SPI_START + 85) 129 #define LPASS_SCSS_MIDI_IRQ (GIC_SPI_START + 86) 130 #define LPASS_Q6SS_WDOG_EXPIRED (GIC_SPI_START + 87) 131 #define LPASS_SCSS_GP_LOW_IRQ (GIC_SPI_START + 88) 132 #define LPASS_SCSS_GP_MEDIUM_IRQ (GIC_SPI_START + 89) 133 #define LPASS_SCSS_GP_HIGH_IRQ (GIC_SPI_START + 90) 134 #define TOP_IMEM_IRQ (GIC_SPI_START + 91) 135 #define FABRIC_SYS_IRQ (GIC_SPI_START + 92) 136 #define FABRIC_APPS_IRQ (GIC_SPI_START + 93) 137 #define USB1_HS_BAM_IRQ (GIC_SPI_START + 94) 138 #define SDC4_BAM_IRQ (GIC_SPI_START + 95) 139 #define SDC3_BAM_IRQ (GIC_SPI_START + 96) 140 #define SDC2_BAM_IRQ (GIC_SPI_START + 97) 141 #define SDC1_BAM_IRQ (GIC_SPI_START + 98) 142 #define FABRIC_SPS_IRQ (GIC_SPI_START + 99) 143 #define USB1_HS_IRQ (GIC_SPI_START + 100) 144 #define SDC4_IRQ_0 (GIC_SPI_START + 101) 145 #define SDC3_IRQ_0 (GIC_SPI_START + 102) 146 #define SDC2_IRQ_0 (GIC_SPI_START + 103) 147 #define SDC1_IRQ_0 (GIC_SPI_START + 104) 148 #define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105) 149 #define SPS_SEC_VIOL_IRQ (GIC_SPI_START + 106) 150 #define SPS_MTI_0 (GIC_SPI_START + 107) 151 #define SPS_MTI_1 (GIC_SPI_START + 108) 152 #define SPS_MTI_2 (GIC_SPI_START + 109) 153 #define SPS_MTI_3 (GIC_SPI_START + 110) 154 #define SPS_MTI_4 (GIC_SPI_START + 111) 155 #define SPS_MTI_5 (GIC_SPI_START + 112) 156 #define SPS_MTI_6 (GIC_SPI_START + 113) 157 #define SPS_MTI_7 (GIC_SPI_START + 114) 158 #define SPS_MTI_8 (GIC_SPI_START + 115) 159 #define SPS_MTI_9 (GIC_SPI_START + 116) 160 #define SPS_MTI_10 (GIC_SPI_START + 117) 161 #define SPS_MTI_11 (GIC_SPI_START + 118) 162 #define SPS_MTI_12 (GIC_SPI_START + 119) 163 #define SPS_MTI_13 (GIC_SPI_START + 120) 164 #define SPS_MTI_14 (GIC_SPI_START + 121) 165 #define SPS_MTI_15 (GIC_SPI_START + 122) 166 #define SPS_MTI_16 (GIC_SPI_START + 123) 167 #define SPS_MTI_17 (GIC_SPI_START + 124) 168 #define SPS_MTI_18 (GIC_SPI_START + 125) 169 #define SPS_MTI_19 (GIC_SPI_START + 126) 170 #define SPS_MTI_20 (GIC_SPI_START + 127) 171 #define SPS_MTI_21 (GIC_SPI_START + 128) 172 #define SPS_MTI_22 (GIC_SPI_START + 129) 173 #define SPS_MTI_23 (GIC_SPI_START + 130) 174 #define SPS_MTI_24 (GIC_SPI_START + 131) 175 #define SPS_MTI_25 (GIC_SPI_START + 132) 176 #define SPS_MTI_26 (GIC_SPI_START + 133) 177 #define SPS_MTI_27 (GIC_SPI_START + 134) 178 #define SPS_MTI_28 (GIC_SPI_START + 135) 179 #define SPS_MTI_29 (GIC_SPI_START + 136) 180 #define SPS_MTI_30 (GIC_SPI_START + 137) 181 #define SPS_MTI_31 (GIC_SPI_START + 138) 182 #define UXMC_EBI2_WR_ER_DONE_IRQ (GIC_SPI_START + 139) 183 #define UXMC_EBI2_OP_DONE_IRQ (GIC_SPI_START + 140) 184 #define USB2_IRQ (GIC_SPI_START + 141) 185 #define USB1_IRQ (GIC_SPI_START + 142) 186 #define TSSC_SSBI_IRQ (GIC_SPI_START + 143) 187 #define TSSC_SAMPLE_IRQ (GIC_SPI_START + 144) 188 #define TSSC_PENUP_IRQ (GIC_SPI_START + 145) 189 #define INT_UART1DM_IRQ (GIC_SPI_START + 146) 190 #define GSBI1_QUP_IRQ (GIC_SPI_START + 147) 191 #define INT_UART2DM_IRQ (GIC_SPI_START + 148) 192 #define GSBI2_QUP_IRQ (GIC_SPI_START + 149) 193 #define INT_UART3DM_IRQ (GIC_SPI_START + 150) 194 #define GSBI3_QUP_IRQ (GIC_SPI_START + 151) 195 #define INT_UART4DM_IRQ (GIC_SPI_START + 152) 196 #define GSBI4_QUP_IRQ (GIC_SPI_START + 153) 197 #define INT_UART5DM_IRQ (GIC_SPI_START + 154) 198 #define GSBI5_QUP_IRQ (GIC_SPI_START + 155) 199 #define INT_UART6DM_IRQ (GIC_SPI_START + 156) 200 #define GSBI6_QUP_IRQ (GIC_SPI_START + 157) 201 #define INT_UART7DM_IRQ (GIC_SPI_START + 158) 202 #define GSBI7_QUP_IRQ (GIC_SPI_START + 159) 203 #define INT_UART8DM_IRQ (GIC_SPI_START + 160) 204 #define GSBI8_QUP_IRQ (GIC_SPI_START + 161) 205 #define TSIF_TSPP_IRQ (GIC_SPI_START + 162) 206 #define TSIF_BAM_IRQ (GIC_SPI_START + 163) 207 #define TSIF2_IRQ (GIC_SPI_START + 164) 208 #define TSIF1_IRQ (GIC_SPI_START + 165) 209 #define INT_ADM1_MASTER (GIC_SPI_START + 166) 210 #define INT_ADM1_AARM (GIC_SPI_START + 167) 211 #define INT_ADM1_SD2 (GIC_SPI_START + 168) 212 #define INT_ADM1_SD3 (GIC_SPI_START + 169) 213 #define INT_ADM0_MASTER (GIC_SPI_START + 170) 214 #define INT_ADM0_AARM (GIC_SPI_START + 171) 215 #define INT_ADM0_SD2 (GIC_SPI_START + 172) 216 #define INT_ADM0_SD3 (GIC_SPI_START + 173) 217 #define CC_SCSS_WDT1CPU1BITEEXPIRED (GIC_SPI_START + 174) 218 #define CC_SCSS_WDT1CPU0BITEEXPIRED (GIC_SPI_START + 175) 219 #define CC_SCSS_WDT0CPU1BITEEXPIRED (GIC_SPI_START + 176) 220 #define CC_SCSS_WDT0CPU0BITEEXPIRED (GIC_SPI_START + 177) 221 #define TSENS_UPPER_LOWER_INT (GIC_SPI_START + 178) 222 #define SSBI2_2_SC_CPU1_SECURE_INT (GIC_SPI_START + 179) 223 #define SSBI2_2_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 180) 224 #define SSBI2_1_SC_CPU1_SECURE_INT (GIC_SPI_START + 181) 225 #define SSBI2_1_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 182) 226 #define XPU_SUMMARY_IRQ (GIC_SPI_START + 183) 227 #define BUS_EXCEPTION_SUMMARY_IRQ (GIC_SPI_START + 184) 228 #define HSDDRX_SMICH0_IRQ (GIC_SPI_START + 185) 229 #define HSDDRX_EBI1_IRQ (GIC_SPI_START + 186) 230 #define SDC5_BAM_IRQ (GIC_SPI_START + 187) 231 #define SDC5_IRQ_0 (GIC_SPI_START + 188) 232 #define INT_UART9DM_IRQ (GIC_SPI_START + 189) 233 #define GSBI9_QUP_IRQ (GIC_SPI_START + 190) 234 #define INT_UART10DM_IRQ (GIC_SPI_START + 191) 235 #define GSBI10_QUP_IRQ (GIC_SPI_START + 192) 236 #define INT_UART11DM_IRQ (GIC_SPI_START + 193) 237 #define GSBI11_QUP_IRQ (GIC_SPI_START + 194) 238 #define INT_UART12DM_IRQ (GIC_SPI_START + 195) 239 #define GSBI12_QUP_IRQ (GIC_SPI_START + 196) 240 241 /*SPI 197 to 209 arent used in 8x60*/ 242 #define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210) 243 #define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211) 244 245 /*SPI 212 to 216 arent used in 8x60*/ 246 #define SMPSS_SPARE_1 (GIC_SPI_START + 217) 247 #define SMPSS_SPARE_2 (GIC_SPI_START + 218) 248 #define SMPSS_SPARE_3 (GIC_SPI_START + 219) 249 #define SMPSS_SPARE_4 (GIC_SPI_START + 220) 250 #define SMPSS_SPARE_5 (GIC_SPI_START + 221) 251 #define SMPSS_SPARE_6 (GIC_SPI_START + 222) 252 #define SMPSS_SPARE_7 (GIC_SPI_START + 223) 253 254 #define NR_GPIO_IRQS 173 255 #define NR_MSM_IRQS 256 256 #define NR_BOARD_IRQS 0 257 258 #endif 259