1 /*
2 * arch/arm/mach-ixp2000/ixdp2x01.c
3 *
4 * Code common to Intel IXDP2401 and IXDP2801 platforms
5 *
6 * Original Author: Andrzej Mialkowski <andrzej.mialkowski@intel.com>
7 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 *
9 * Copyright (C) 2002-2003 Intel Corp.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/mm.h>
21 #include <linux/sched.h>
22 #include <linux/interrupt.h>
23 #include <linux/bitops.h>
24 #include <linux/pci.h>
25 #include <linux/ioport.h>
26 #include <linux/delay.h>
27 #include <linux/serial.h>
28 #include <linux/tty.h>
29 #include <linux/serial_core.h>
30 #include <linux/platform_device.h>
31 #include <linux/serial_8250.h>
32 #include <linux/io.h>
33
34 #include <asm/irq.h>
35 #include <asm/pgtable.h>
36 #include <asm/page.h>
37 #include <asm/system.h>
38 #include <mach/hardware.h>
39 #include <asm/mach-types.h>
40
41 #include <asm/mach/pci.h>
42 #include <asm/mach/map.h>
43 #include <asm/mach/irq.h>
44 #include <asm/mach/time.h>
45 #include <asm/mach/arch.h>
46 #include <asm/mach/flash.h>
47
48 /*************************************************************************
49 * IXDP2x01 IRQ Handling
50 *************************************************************************/
ixdp2x01_irq_mask(struct irq_data * d)51 static void ixdp2x01_irq_mask(struct irq_data *d)
52 {
53 ixp2000_reg_wrb(IXDP2X01_INT_MASK_SET_REG,
54 IXP2000_BOARD_IRQ_MASK(d->irq));
55 }
56
ixdp2x01_irq_unmask(struct irq_data * d)57 static void ixdp2x01_irq_unmask(struct irq_data *d)
58 {
59 ixp2000_reg_write(IXDP2X01_INT_MASK_CLR_REG,
60 IXP2000_BOARD_IRQ_MASK(d->irq));
61 }
62
63 static u32 valid_irq_mask;
64
ixdp2x01_irq_handler(unsigned int irq,struct irq_desc * desc)65 static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc)
66 {
67 u32 ex_interrupt;
68 int i;
69
70 desc->irq_data.chip->irq_mask(&desc->irq_data);
71
72 ex_interrupt = *IXDP2X01_INT_STAT_REG & valid_irq_mask;
73
74 if (!ex_interrupt) {
75 printk(KERN_ERR "Spurious IXDP2X01 CPLD interrupt!\n");
76 return;
77 }
78
79 for (i = 0; i < IXP2000_BOARD_IRQS; i++) {
80 if (ex_interrupt & (1 << i)) {
81 int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
82 generic_handle_irq(cpld_irq);
83 }
84 }
85
86 desc->irq_data.chip->irq_unmask(&desc->irq_data);
87 }
88
89 static struct irq_chip ixdp2x01_irq_chip = {
90 .irq_mask = ixdp2x01_irq_mask,
91 .irq_ack = ixdp2x01_irq_mask,
92 .irq_unmask = ixdp2x01_irq_unmask
93 };
94
95 /*
96 * We only do anything if we are the master NPU on the board.
97 * The slave NPU only has the ethernet chip going directly to
98 * the PCIB interrupt input.
99 */
ixdp2x01_init_irq(void)100 void __init ixdp2x01_init_irq(void)
101 {
102 int irq = 0;
103
104 /* initialize chip specific interrupts */
105 ixp2000_init_irq();
106
107 if (machine_is_ixdp2401())
108 valid_irq_mask = IXDP2401_VALID_IRQ_MASK;
109 else
110 valid_irq_mask = IXDP2801_VALID_IRQ_MASK;
111
112 /* Mask all interrupts from CPLD, disable simulation */
113 ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff);
114 ixp2000_reg_wrb(IXDP2X01_INT_SIM_REG, 0);
115
116 for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
117 if (irq & valid_irq_mask) {
118 irq_set_chip_and_handler(irq, &ixdp2x01_irq_chip,
119 handle_level_irq);
120 set_irq_flags(irq, IRQF_VALID);
121 } else {
122 set_irq_flags(irq, 0);
123 }
124 }
125
126 /* Hook into PCI interrupts */
127 irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler);
128 }
129
130
131 /*************************************************************************
132 * IXDP2x01 memory map
133 *************************************************************************/
134 static struct map_desc ixdp2x01_io_desc __initdata = {
135 .virtual = IXDP2X01_VIRT_CPLD_BASE,
136 .pfn = __phys_to_pfn(IXDP2X01_PHYS_CPLD_BASE),
137 .length = IXDP2X01_CPLD_REGION_SIZE,
138 .type = MT_DEVICE
139 };
140
ixdp2x01_map_io(void)141 static void __init ixdp2x01_map_io(void)
142 {
143 ixp2000_map_io();
144 iotable_init(&ixdp2x01_io_desc, 1);
145 }
146
147
148 /*************************************************************************
149 * IXDP2x01 serial ports
150 *************************************************************************/
151 static struct plat_serial8250_port ixdp2x01_serial_port1[] = {
152 {
153 .mapbase = (unsigned long)IXDP2X01_UART1_PHYS_BASE,
154 .membase = (char *)IXDP2X01_UART1_VIRT_BASE,
155 .irq = IRQ_IXDP2X01_UART1,
156 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
157 .iotype = UPIO_MEM32,
158 .regshift = 2,
159 .uartclk = IXDP2X01_UART_CLK,
160 },
161 { }
162 };
163
164 static struct resource ixdp2x01_uart_resource1 = {
165 .start = IXDP2X01_UART1_PHYS_BASE,
166 .end = IXDP2X01_UART1_PHYS_BASE + 0xffff,
167 .flags = IORESOURCE_MEM,
168 };
169
170 static struct platform_device ixdp2x01_serial_device1 = {
171 .name = "serial8250",
172 .id = PLAT8250_DEV_PLATFORM1,
173 .dev = {
174 .platform_data = ixdp2x01_serial_port1,
175 },
176 .num_resources = 1,
177 .resource = &ixdp2x01_uart_resource1,
178 };
179
180 static struct plat_serial8250_port ixdp2x01_serial_port2[] = {
181 {
182 .mapbase = (unsigned long)IXDP2X01_UART2_PHYS_BASE,
183 .membase = (char *)IXDP2X01_UART2_VIRT_BASE,
184 .irq = IRQ_IXDP2X01_UART2,
185 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
186 .iotype = UPIO_MEM32,
187 .regshift = 2,
188 .uartclk = IXDP2X01_UART_CLK,
189 },
190 { }
191 };
192
193 static struct resource ixdp2x01_uart_resource2 = {
194 .start = IXDP2X01_UART2_PHYS_BASE,
195 .end = IXDP2X01_UART2_PHYS_BASE + 0xffff,
196 .flags = IORESOURCE_MEM,
197 };
198
199 static struct platform_device ixdp2x01_serial_device2 = {
200 .name = "serial8250",
201 .id = PLAT8250_DEV_PLATFORM2,
202 .dev = {
203 .platform_data = ixdp2x01_serial_port2,
204 },
205 .num_resources = 1,
206 .resource = &ixdp2x01_uart_resource2,
207 };
208
ixdp2x01_uart_init(void)209 static void ixdp2x01_uart_init(void)
210 {
211 platform_device_register(&ixdp2x01_serial_device1);
212 platform_device_register(&ixdp2x01_serial_device2);
213 }
214
215
216 /*************************************************************************
217 * IXDP2x01 timer tick configuration
218 *************************************************************************/
219 static unsigned int ixdp2x01_clock;
220
ixdp2x01_clock_setup(char * str)221 static int __init ixdp2x01_clock_setup(char *str)
222 {
223 ixdp2x01_clock = simple_strtoul(str, NULL, 10);
224
225 return 1;
226 }
227
228 __setup("ixdp2x01_clock=", ixdp2x01_clock_setup);
229
ixdp2x01_timer_init(void)230 static void __init ixdp2x01_timer_init(void)
231 {
232 if (!ixdp2x01_clock)
233 ixdp2x01_clock = 50000000;
234
235 ixp2000_init_time(ixdp2x01_clock);
236 }
237
238 static struct sys_timer ixdp2x01_timer = {
239 .init = ixdp2x01_timer_init,
240 .offset = ixp2000_gettimeoffset,
241 };
242
243 /*************************************************************************
244 * IXDP2x01 PCI
245 *************************************************************************/
ixdp2x01_pci_preinit(void)246 void __init ixdp2x01_pci_preinit(void)
247 {
248 ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00000000);
249 ixp2000_pci_preinit();
250 pcibios_setup("firmware");
251 }
252
253 #define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
254
ixdp2x01_pci_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)255 static int __init ixdp2x01_pci_map_irq(const struct pci_dev *dev, u8 slot,
256 u8 pin)
257 {
258 u8 bus = dev->bus->number;
259 u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
260 struct pci_bus *tmp_bus = dev->bus;
261
262 /* Primary bus, no interrupts here */
263 if (bus == 0) {
264 return -1;
265 }
266
267 /* Lookup first leaf in bus tree */
268 while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL)) {
269 tmp_bus = tmp_bus->parent;
270 }
271
272 /* Select between known bridges */
273 switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) {
274 /* Device is located after first MB bridge */
275 case 0x0008:
276 if (tmp_bus == dev->bus) {
277 /* Device is located directly after first MB bridge */
278 switch (devpin) {
279 case DEVPIN(1, 1): /* Onboard 82546 ch 0 */
280 if (machine_is_ixdp2401())
281 return IRQ_IXDP2401_INTA_82546;
282 return -1;
283 case DEVPIN(1, 2): /* Onboard 82546 ch 1 */
284 if (machine_is_ixdp2401())
285 return IRQ_IXDP2401_INTB_82546;
286 return -1;
287 case DEVPIN(0, 1): /* PMC INTA# */
288 return IRQ_IXDP2X01_SPCI_PMC_INTA;
289 case DEVPIN(0, 2): /* PMC INTB# */
290 return IRQ_IXDP2X01_SPCI_PMC_INTB;
291 case DEVPIN(0, 3): /* PMC INTC# */
292 return IRQ_IXDP2X01_SPCI_PMC_INTC;
293 case DEVPIN(0, 4): /* PMC INTD# */
294 return IRQ_IXDP2X01_SPCI_PMC_INTD;
295 }
296 }
297 break;
298 case 0x0010:
299 if (tmp_bus == dev->bus) {
300 /* Device is located directly after second MB bridge */
301 /* Secondary bus of second bridge */
302 switch (devpin) {
303 case DEVPIN(0, 1): /* DB#0 */
304 return IRQ_IXDP2X01_SPCI_DB_0;
305 case DEVPIN(1, 1): /* DB#1 */
306 return IRQ_IXDP2X01_SPCI_DB_1;
307 }
308 } else {
309 /* Device is located indirectly after second MB bridge */
310 /* Not supported now */
311 }
312 break;
313 }
314
315 return -1;
316 }
317
318
ixdp2x01_pci_setup(int nr,struct pci_sys_data * sys)319 static int ixdp2x01_pci_setup(int nr, struct pci_sys_data *sys)
320 {
321 sys->mem_offset = 0xe0000000;
322
323 if (machine_is_ixdp2801() || machine_is_ixdp28x5())
324 sys->mem_offset -= ((*IXP2000_PCI_ADDR_EXT & 0xE000) << 16);
325
326 return ixp2000_pci_setup(nr, sys);
327 }
328
329 struct hw_pci ixdp2x01_pci __initdata = {
330 .nr_controllers = 1,
331 .setup = ixdp2x01_pci_setup,
332 .preinit = ixdp2x01_pci_preinit,
333 .scan = ixp2000_pci_scan_bus,
334 .map_irq = ixdp2x01_pci_map_irq,
335 };
336
ixdp2x01_pci_init(void)337 int __init ixdp2x01_pci_init(void)
338 {
339 if (machine_is_ixdp2401() || machine_is_ixdp2801() ||\
340 machine_is_ixdp28x5())
341 pci_common_init(&ixdp2x01_pci);
342
343 return 0;
344 }
345
346 subsys_initcall(ixdp2x01_pci_init);
347
348 /*************************************************************************
349 * IXDP2x01 Machine Initialization
350 *************************************************************************/
351 static struct flash_platform_data ixdp2x01_flash_platform_data = {
352 .map_name = "cfi_probe",
353 .width = 1,
354 };
355
ixdp2x01_flash_bank_setup(unsigned long ofs)356 static unsigned long ixdp2x01_flash_bank_setup(unsigned long ofs)
357 {
358 ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
359 ((ofs >> IXDP2X01_FLASH_WINDOW_BITS) | IXDP2X01_CPLD_FLASH_INTERN));
360 return (ofs & IXDP2X01_FLASH_WINDOW_MASK);
361 }
362
363 static struct ixp2000_flash_data ixdp2x01_flash_data = {
364 .platform_data = &ixdp2x01_flash_platform_data,
365 .bank_setup = ixdp2x01_flash_bank_setup
366 };
367
368 static struct resource ixdp2x01_flash_resource = {
369 .start = 0xc4000000,
370 .end = 0xc4000000 + 0x01ffffff,
371 .flags = IORESOURCE_MEM,
372 };
373
374 static struct platform_device ixdp2x01_flash = {
375 .name = "IXP2000-Flash",
376 .id = 0,
377 .dev = {
378 .platform_data = &ixdp2x01_flash_data,
379 },
380 .num_resources = 1,
381 .resource = &ixdp2x01_flash_resource,
382 };
383
384 static struct ixp2000_i2c_pins ixdp2x01_i2c_gpio_pins = {
385 .sda_pin = IXDP2X01_GPIO_SDA,
386 .scl_pin = IXDP2X01_GPIO_SCL,
387 };
388
389 static struct platform_device ixdp2x01_i2c_controller = {
390 .name = "IXP2000-I2C",
391 .id = 0,
392 .dev = {
393 .platform_data = &ixdp2x01_i2c_gpio_pins,
394 },
395 .num_resources = 0
396 };
397
398 static struct platform_device *ixdp2x01_devices[] __initdata = {
399 &ixdp2x01_flash,
400 &ixdp2x01_i2c_controller
401 };
402
ixdp2x01_init_machine(void)403 static void __init ixdp2x01_init_machine(void)
404 {
405 ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
406 (IXDP2X01_CPLD_FLASH_BANK_MASK | IXDP2X01_CPLD_FLASH_INTERN));
407
408 ixdp2x01_flash_data.nr_banks =
409 ((*IXDP2X01_CPLD_FLASH_REG & IXDP2X01_CPLD_FLASH_BANK_MASK) + 1);
410
411 platform_add_devices(ixdp2x01_devices, ARRAY_SIZE(ixdp2x01_devices));
412 ixp2000_uart_init();
413 ixdp2x01_uart_init();
414 }
415
ixdp2401_restart(char mode,const char * cmd)416 static void ixdp2401_restart(char mode, const char *cmd)
417 {
418 /*
419 * Reset flash banking register so that we are pointing at
420 * RedBoot bank.
421 */
422 ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG,
423 ((0 >> IXDP2X01_FLASH_WINDOW_BITS)
424 | IXDP2X01_CPLD_FLASH_INTERN));
425 ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff);
426
427 ixp2000_restart(mode, cmd);
428 }
429
ixdp280x_restart(char mode,const char * cmd)430 static void ixdp280x_restart(char mode, const char *cmd)
431 {
432 /*
433 * On IXDP2801 we need to write this magic sequence to the CPLD
434 * to cause a complete reset of the CPU and all external devices
435 * and move the flash bank register back to 0.
436 */
437 unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG;
438
439 reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF);
440 ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg);
441 ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000);
442
443 ixp2000_restart(mode, cmd);
444 }
445
446 #ifdef CONFIG_ARCH_IXDP2401
447 MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform")
448 /* Maintainer: MontaVista Software, Inc. */
449 .atag_offset = 0x100,
450 .map_io = ixdp2x01_map_io,
451 .init_irq = ixdp2x01_init_irq,
452 .timer = &ixdp2x01_timer,
453 .init_machine = ixdp2x01_init_machine,
454 .restart = ixdp2401_restart,
455 MACHINE_END
456 #endif
457
458 #ifdef CONFIG_ARCH_IXDP2801
459 MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform")
460 /* Maintainer: MontaVista Software, Inc. */
461 .atag_offset = 0x100,
462 .map_io = ixdp2x01_map_io,
463 .init_irq = ixdp2x01_init_irq,
464 .timer = &ixdp2x01_timer,
465 .init_machine = ixdp2x01_init_machine,
466 .restart = ixdp280x_restart,
467 MACHINE_END
468
469 /*
470 * IXDP28x5 is basically an IXDP2801 with a different CPU but Intel
471 * changed the machine ID in the bootloader
472 */
473 MACHINE_START(IXDP28X5, "Intel IXDP2805/2855 Development Platform")
474 /* Maintainer: MontaVista Software, Inc. */
475 .atag_offset = 0x100,
476 .map_io = ixdp2x01_map_io,
477 .init_irq = ixdp2x01_init_irq,
478 .timer = &ixdp2x01_timer,
479 .init_machine = ixdp2x01_init_machine,
480 .restart = ixdp280x_restart,
481 MACHINE_END
482 #endif
483
484
485