1 /*
2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 *
11 * Create static mapping between physical to virtual memory.
12 */
13
14 #include <linux/mm.h>
15 #include <linux/init.h>
16 #include <linux/clk.h>
17
18 #include <asm/mach/map.h>
19
20 #include <mach/hardware.h>
21 #include <mach/common.h>
22 #include <mach/devices-common.h>
23 #include <mach/iomux-v3.h>
24
25 static struct clk *gpc_dvfs_clk;
26
imx5_idle(void)27 static void imx5_idle(void)
28 {
29 if (!need_resched()) {
30 /* gpc clock is needed for SRPG */
31 if (gpc_dvfs_clk == NULL) {
32 gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
33 if (IS_ERR(gpc_dvfs_clk))
34 goto err0;
35 }
36 clk_enable(gpc_dvfs_clk);
37 mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
38 if (tzic_enable_wake())
39 goto err1;
40 cpu_do_idle();
41 err1:
42 clk_disable(gpc_dvfs_clk);
43 }
44 err0:
45 local_irq_enable();
46 }
47
48 /*
49 * Define the MX50 memory map.
50 */
51 static struct map_desc mx50_io_desc[] __initdata = {
52 imx_map_entry(MX50, TZIC, MT_DEVICE),
53 imx_map_entry(MX50, SPBA0, MT_DEVICE),
54 imx_map_entry(MX50, AIPS1, MT_DEVICE),
55 imx_map_entry(MX50, AIPS2, MT_DEVICE),
56 };
57
58 /*
59 * Define the MX51 memory map.
60 */
61 static struct map_desc mx51_io_desc[] __initdata = {
62 imx_map_entry(MX51, TZIC, MT_DEVICE),
63 imx_map_entry(MX51, IRAM, MT_DEVICE),
64 imx_map_entry(MX51, AIPS1, MT_DEVICE),
65 imx_map_entry(MX51, SPBA0, MT_DEVICE),
66 imx_map_entry(MX51, AIPS2, MT_DEVICE),
67 };
68
69 /*
70 * Define the MX53 memory map.
71 */
72 static struct map_desc mx53_io_desc[] __initdata = {
73 imx_map_entry(MX53, TZIC, MT_DEVICE),
74 imx_map_entry(MX53, AIPS1, MT_DEVICE),
75 imx_map_entry(MX53, SPBA0, MT_DEVICE),
76 imx_map_entry(MX53, AIPS2, MT_DEVICE),
77 };
78
79 /*
80 * This function initializes the memory map. It is called during the
81 * system startup to create static physical to virtual memory mappings
82 * for the IO modules.
83 */
mx50_map_io(void)84 void __init mx50_map_io(void)
85 {
86 iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
87 }
88
mx51_map_io(void)89 void __init mx51_map_io(void)
90 {
91 iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
92 }
93
mx53_map_io(void)94 void __init mx53_map_io(void)
95 {
96 iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
97 }
98
imx50_init_early(void)99 void __init imx50_init_early(void)
100 {
101 mxc_set_cpu_type(MXC_CPU_MX50);
102 mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
103 mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
104 }
105
imx51_init_early(void)106 void __init imx51_init_early(void)
107 {
108 mxc_set_cpu_type(MXC_CPU_MX51);
109 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
110 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
111 pm_idle = imx5_idle;
112 }
113
imx53_init_early(void)114 void __init imx53_init_early(void)
115 {
116 mxc_set_cpu_type(MXC_CPU_MX53);
117 mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
118 mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
119 }
120
mx50_init_irq(void)121 void __init mx50_init_irq(void)
122 {
123 tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
124 }
125
mx51_init_irq(void)126 void __init mx51_init_irq(void)
127 {
128 tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
129 }
130
mx53_init_irq(void)131 void __init mx53_init_irq(void)
132 {
133 tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR));
134 }
135
136 static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
137 .ap_2_ap_addr = 642,
138 .uart_2_mcu_addr = 817,
139 .mcu_2_app_addr = 747,
140 .mcu_2_shp_addr = 961,
141 .ata_2_mcu_addr = 1473,
142 .mcu_2_ata_addr = 1392,
143 .app_2_per_addr = 1033,
144 .app_2_mcu_addr = 683,
145 .shp_2_per_addr = 1251,
146 .shp_2_mcu_addr = 892,
147 };
148
149 static struct sdma_platform_data imx51_sdma_pdata __initdata = {
150 .fw_name = "sdma-imx51.bin",
151 .script_addrs = &imx51_sdma_script,
152 };
153
154 static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
155 .ap_2_ap_addr = 642,
156 .app_2_mcu_addr = 683,
157 .mcu_2_app_addr = 747,
158 .uart_2_mcu_addr = 817,
159 .shp_2_mcu_addr = 891,
160 .mcu_2_shp_addr = 960,
161 .uartsh_2_mcu_addr = 1032,
162 .spdif_2_mcu_addr = 1100,
163 .mcu_2_spdif_addr = 1134,
164 .firi_2_mcu_addr = 1193,
165 .mcu_2_firi_addr = 1290,
166 };
167
168 static struct sdma_platform_data imx53_sdma_pdata __initdata = {
169 .fw_name = "sdma-imx53.bin",
170 .script_addrs = &imx53_sdma_script,
171 };
172
imx50_soc_init(void)173 void __init imx50_soc_init(void)
174 {
175 /* i.mx50 has the i.mx31 type gpio */
176 mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
177 mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
178 mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
179 mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
180 mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
181 mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
182 }
183
imx51_soc_init(void)184 void __init imx51_soc_init(void)
185 {
186 /* i.mx51 has the i.mx31 type gpio */
187 mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
188 mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
189 mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
190 mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
191
192 /* i.mx51 has the i.mx35 type sdma */
193 imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
194 }
195
imx53_soc_init(void)196 void __init imx53_soc_init(void)
197 {
198 /* i.mx53 has the i.mx31 type gpio */
199 mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
200 mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
201 mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
202 mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
203 mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
204 mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
205 mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
206
207 /* i.mx53 has the i.mx35 type sdma */
208 imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
209 }
210