1 /*
2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/types.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/memory.h>
22 #include <linux/platform_device.h>
23 #include <linux/gpio.h>
24 #include <linux/moduleparam.h>
25 #include <linux/smsc911x.h>
26 #include <linux/mfd/mc13783.h>
27 #include <linux/spi/spi.h>
28 #include <linux/usb/otg.h>
29 #include <linux/usb/ulpi.h>
30 #include <linux/mtd/physmap.h>
31 #include <linux/delay.h>
32
33 #include <asm/mach-types.h>
34 #include <asm/mach/arch.h>
35 #include <asm/mach/time.h>
36 #include <asm/mach/map.h>
37 #include <asm/page.h>
38 #include <asm/setup.h>
39
40 #include <mach/hardware.h>
41 #include <mach/common.h>
42 #include <mach/board-mx31lite.h>
43 #include <mach/iomux-mx3.h>
44 #include <mach/irqs.h>
45 #include <mach/ulpi.h>
46
47 #include "devices-imx31.h"
48
49 /*
50 * This file contains the module-specific initialization routines.
51 */
52
53 static unsigned int mx31lite_pins[] = {
54 /* LAN9117 IRQ pin */
55 IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO),
56 /* SPI 1 */
57 MX31_PIN_CSPI2_SCLK__SCLK,
58 MX31_PIN_CSPI2_MOSI__MOSI,
59 MX31_PIN_CSPI2_MISO__MISO,
60 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
61 MX31_PIN_CSPI2_SS0__SS0,
62 MX31_PIN_CSPI2_SS1__SS1,
63 MX31_PIN_CSPI2_SS2__SS2,
64 };
65
66 static const struct mxc_nand_platform_data
67 mx31lite_nand_board_info __initconst = {
68 .width = 1,
69 .hw_ecc = 1,
70 };
71
72 static struct smsc911x_platform_config smsc911x_config = {
73 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
74 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
75 .flags = SMSC911X_USE_16BIT,
76 };
77
78 static struct resource smsc911x_resources[] = {
79 {
80 .start = MX31_CS4_BASE_ADDR,
81 .end = MX31_CS4_BASE_ADDR + 0x100,
82 .flags = IORESOURCE_MEM,
83 }, {
84 .start = IOMUX_TO_IRQ(MX31_PIN_SFS6),
85 .end = IOMUX_TO_IRQ(MX31_PIN_SFS6),
86 .flags = IORESOURCE_IRQ,
87 },
88 };
89
90 static struct platform_device smsc911x_device = {
91 .name = "smsc911x",
92 .id = -1,
93 .num_resources = ARRAY_SIZE(smsc911x_resources),
94 .resource = smsc911x_resources,
95 .dev = {
96 .platform_data = &smsc911x_config,
97 },
98 };
99
100 /*
101 * SPI
102 *
103 * The MC13783 is the only hard-wired SPI device on the module.
104 */
105
106 static int spi_internal_chipselect[] = {
107 MXC_SPI_CS(0),
108 };
109
110 static const struct spi_imx_master spi1_pdata __initconst = {
111 .chipselect = spi_internal_chipselect,
112 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
113 };
114
115 static struct mc13xxx_platform_data mc13783_pdata __initdata = {
116 .flags = MC13XXX_USE_RTC,
117 };
118
119 static struct spi_board_info mc13783_spi_dev __initdata = {
120 .modalias = "mc13783",
121 .max_speed_hz = 1000000,
122 .bus_num = 1,
123 .chip_select = 0,
124 .platform_data = &mc13783_pdata,
125 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
126 };
127
128 /*
129 * USB
130 */
131
132 #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
133 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
134
usbh2_init(struct platform_device * pdev)135 static int usbh2_init(struct platform_device *pdev)
136 {
137 int pins[] = {
138 MX31_PIN_USBH2_DATA0__USBH2_DATA0,
139 MX31_PIN_USBH2_DATA1__USBH2_DATA1,
140 MX31_PIN_USBH2_CLK__USBH2_CLK,
141 MX31_PIN_USBH2_DIR__USBH2_DIR,
142 MX31_PIN_USBH2_NXT__USBH2_NXT,
143 MX31_PIN_USBH2_STP__USBH2_STP,
144 };
145
146 mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");
147
148 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
149 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
150 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
151 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
152 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
153 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
154 mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
155 mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
156 mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
157 mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
158 mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
159 mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
160
161 mxc_iomux_set_gpr(MUX_PGP_UH2, true);
162
163 /* chip select */
164 mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
165 "USBH2_CS");
166 gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
167 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
168
169 mdelay(10);
170
171 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
172 }
173
174 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
175 .init = usbh2_init,
176 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
177 };
178
179 /*
180 * NOR flash
181 */
182
183 static struct physmap_flash_data nor_flash_data = {
184 .width = 2,
185 };
186
187 static struct resource nor_flash_resource = {
188 .start = 0xa0000000,
189 .end = 0xa1ffffff,
190 .flags = IORESOURCE_MEM,
191 };
192
193 static struct platform_device physmap_flash_device = {
194 .name = "physmap-flash",
195 .id = 0,
196 .dev = {
197 .platform_data = &nor_flash_data,
198 },
199 .resource = &nor_flash_resource,
200 .num_resources = 1,
201 };
202
203
204
205 /*
206 * This structure defines the MX31 memory map.
207 */
208 static struct map_desc mx31lite_io_desc[] __initdata = {
209 {
210 .virtual = MX31_CS4_BASE_ADDR_VIRT,
211 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
212 .length = MX31_CS4_SIZE,
213 .type = MT_DEVICE
214 }
215 };
216
217 /*
218 * Set up static virtual mappings.
219 */
mx31lite_map_io(void)220 void __init mx31lite_map_io(void)
221 {
222 mx31_map_io();
223 iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
224 }
225
226 static int mx31lite_baseboard;
227 core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);
228
mx31lite_init(void)229 static void __init mx31lite_init(void)
230 {
231 int ret;
232
233 imx31_soc_init();
234
235 switch (mx31lite_baseboard) {
236 case MX31LITE_NOBOARD:
237 break;
238 case MX31LITE_DB:
239 mx31lite_db_init();
240 break;
241 default:
242 printk(KERN_ERR "Illegal mx31lite_baseboard type %d\n",
243 mx31lite_baseboard);
244 }
245
246 mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins),
247 "mx31lite");
248
249 /* NOR and NAND flash */
250 platform_device_register(&physmap_flash_device);
251 imx31_add_mxc_nand(&mx31lite_nand_board_info);
252
253 imx31_add_spi_imx1(&spi1_pdata);
254 spi_register_board_info(&mc13783_spi_dev, 1);
255
256 /* USB */
257 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
258 ULPI_OTG_DRVVBUS_EXT);
259 if (usbh2_pdata.otg)
260 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
261
262 /* SMSC9117 IRQ pin */
263 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
264 if (ret)
265 pr_warning("could not get LAN irq gpio\n");
266 else {
267 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
268 platform_device_register(&smsc911x_device);
269 }
270 }
271
mx31lite_timer_init(void)272 static void __init mx31lite_timer_init(void)
273 {
274 mx31_clocks_init(26000000);
275 }
276
277 struct sys_timer mx31lite_timer = {
278 .init = mx31lite_timer_init,
279 };
280
281 MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
282 /* Maintainer: Freescale Semiconductor, Inc. */
283 .atag_offset = 0x100,
284 .map_io = mx31lite_map_io,
285 .init_early = imx31_init_early,
286 .init_irq = mx31_init_irq,
287 .handle_irq = imx31_handle_irq,
288 .timer = &mx31lite_timer,
289 .init_machine = mx31lite_init,
290 .restart = mxc_restart,
291 MACHINE_END
292