1 /*
2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/types.h>
18 #include <linux/init.h>
19 #include <linux/clk.h>
20 #include <linux/serial_8250.h>
21 #include <linux/gpio.h>
22 #include <linux/i2c.h>
23 #include <linux/irq.h>
24
25 #include <asm/mach-types.h>
26 #include <asm/mach/arch.h>
27 #include <asm/mach/time.h>
28 #include <asm/memory.h>
29 #include <asm/mach/map.h>
30 #include <mach/common.h>
31 #include <mach/board-mx31ads.h>
32 #include <mach/iomux-mx3.h>
33
34 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
35 #include <linux/mfd/wm8350/audio.h>
36 #include <linux/mfd/wm8350/core.h>
37 #include <linux/mfd/wm8350/pmic.h>
38 #endif
39
40 #include "devices-imx31.h"
41
42 /* PBC Board interrupt status register */
43 #define PBC_INTSTATUS 0x000016
44
45 /* PBC Board interrupt current status register */
46 #define PBC_INTCURR_STATUS 0x000018
47
48 /* PBC Interrupt mask register set address */
49 #define PBC_INTMASK_SET 0x00001A
50
51 /* PBC Interrupt mask register clear address */
52 #define PBC_INTMASK_CLEAR 0x00001C
53
54 /* External UART A */
55 #define PBC_SC16C652_UARTA 0x010000
56
57 /* External UART B */
58 #define PBC_SC16C652_UARTB 0x010010
59
60 #define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
61 #define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
62 #define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
63 #define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
64
65 #define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
66
67 #define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
68 #define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
69
70 #define MXC_MAX_EXP_IO_LINES 16
71
72 /*
73 * The serial port definition structure.
74 */
75 static struct plat_serial8250_port serial_platform_data[] = {
76 {
77 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
78 .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
79 .irq = EXPIO_INT_XUART_INTA,
80 .uartclk = 14745600,
81 .regshift = 0,
82 .iotype = UPIO_MEM,
83 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
84 }, {
85 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
86 .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
87 .irq = EXPIO_INT_XUART_INTB,
88 .uartclk = 14745600,
89 .regshift = 0,
90 .iotype = UPIO_MEM,
91 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
92 },
93 {},
94 };
95
96 static struct platform_device serial_device = {
97 .name = "serial8250",
98 .id = 0,
99 .dev = {
100 .platform_data = serial_platform_data,
101 },
102 };
103
mxc_init_extuart(void)104 static int __init mxc_init_extuart(void)
105 {
106 return platform_device_register(&serial_device);
107 }
108
109 static const struct imxuart_platform_data uart_pdata __initconst = {
110 .flags = IMXUART_HAVE_RTSCTS,
111 };
112
113 static unsigned int uart_pins[] = {
114 MX31_PIN_CTS1__CTS1,
115 MX31_PIN_RTS1__RTS1,
116 MX31_PIN_TXD1__TXD1,
117 MX31_PIN_RXD1__RXD1
118 };
119
mxc_init_imx_uart(void)120 static inline void mxc_init_imx_uart(void)
121 {
122 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
123 imx31_add_imx_uart0(&uart_pdata);
124 }
125
mx31ads_expio_irq_handler(u32 irq,struct irq_desc * desc)126 static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
127 {
128 u32 imr_val;
129 u32 int_valid;
130 u32 expio_irq;
131
132 imr_val = __raw_readw(PBC_INTMASK_SET_REG);
133 int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
134
135 expio_irq = MXC_EXP_IO_BASE;
136 for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
137 if ((int_valid & 1) == 0)
138 continue;
139
140 generic_handle_irq(expio_irq);
141 }
142 }
143
144 /*
145 * Disable an expio pin's interrupt by setting the bit in the imr.
146 * @param d an expio virtual irq description
147 */
expio_mask_irq(struct irq_data * d)148 static void expio_mask_irq(struct irq_data *d)
149 {
150 u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
151 /* mask the interrupt */
152 __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
153 __raw_readw(PBC_INTMASK_CLEAR_REG);
154 }
155
156 /*
157 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
158 * @param d an expio virtual irq description
159 */
expio_ack_irq(struct irq_data * d)160 static void expio_ack_irq(struct irq_data *d)
161 {
162 u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
163 /* clear the interrupt status */
164 __raw_writew(1 << expio, PBC_INTSTATUS_REG);
165 }
166
167 /*
168 * Enable a expio pin's interrupt by clearing the bit in the imr.
169 * @param d an expio virtual irq description
170 */
expio_unmask_irq(struct irq_data * d)171 static void expio_unmask_irq(struct irq_data *d)
172 {
173 u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
174 /* unmask the interrupt */
175 __raw_writew(1 << expio, PBC_INTMASK_SET_REG);
176 }
177
178 static struct irq_chip expio_irq_chip = {
179 .name = "EXPIO(CPLD)",
180 .irq_ack = expio_ack_irq,
181 .irq_mask = expio_mask_irq,
182 .irq_unmask = expio_unmask_irq,
183 };
184
mx31ads_init_expio(void)185 static void __init mx31ads_init_expio(void)
186 {
187 int i;
188
189 printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
190
191 /*
192 * Configure INT line as GPIO input
193 */
194 mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
195
196 /* disable the interrupt and clear the status */
197 __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
198 __raw_writew(0xFFFF, PBC_INTSTATUS_REG);
199 for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
200 i++) {
201 irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
202 set_irq_flags(i, IRQF_VALID);
203 }
204 irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
205 irq_set_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
206 }
207
208 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
209 /* This section defines setup for the Wolfson Microelectronics
210 * 1133-EV1 PMU/audio board. When other PMU boards are supported the
211 * regulator definitions may be shared with them, but for now they can
212 * only be used with this board so would generate warnings about
213 * unused statics and some of the configuration is specific to this
214 * module.
215 */
216
217 /* CPU */
218 static struct regulator_consumer_supply sw1a_consumers[] = {
219 {
220 .supply = "cpu_vcc",
221 }
222 };
223
224 static struct regulator_init_data sw1a_data = {
225 .constraints = {
226 .name = "SW1A",
227 .min_uV = 1275000,
228 .max_uV = 1600000,
229 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
230 REGULATOR_CHANGE_MODE,
231 .valid_modes_mask = REGULATOR_MODE_NORMAL |
232 REGULATOR_MODE_FAST,
233 .state_mem = {
234 .uV = 1400000,
235 .mode = REGULATOR_MODE_NORMAL,
236 .enabled = 1,
237 },
238 .initial_state = PM_SUSPEND_MEM,
239 .always_on = 1,
240 .boot_on = 1,
241 },
242 .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
243 .consumer_supplies = sw1a_consumers,
244 };
245
246 /* System IO - High */
247 static struct regulator_init_data viohi_data = {
248 .constraints = {
249 .name = "VIOHO",
250 .min_uV = 2800000,
251 .max_uV = 2800000,
252 .state_mem = {
253 .uV = 2800000,
254 .mode = REGULATOR_MODE_NORMAL,
255 .enabled = 1,
256 },
257 .initial_state = PM_SUSPEND_MEM,
258 .always_on = 1,
259 .boot_on = 1,
260 },
261 };
262
263 /* System IO - Low */
264 static struct regulator_init_data violo_data = {
265 .constraints = {
266 .name = "VIOLO",
267 .min_uV = 1800000,
268 .max_uV = 1800000,
269 .state_mem = {
270 .uV = 1800000,
271 .mode = REGULATOR_MODE_NORMAL,
272 .enabled = 1,
273 },
274 .initial_state = PM_SUSPEND_MEM,
275 .always_on = 1,
276 .boot_on = 1,
277 },
278 };
279
280 /* DDR RAM */
281 static struct regulator_init_data sw2a_data = {
282 .constraints = {
283 .name = "SW2A",
284 .min_uV = 1800000,
285 .max_uV = 1800000,
286 .valid_modes_mask = REGULATOR_MODE_NORMAL,
287 .state_mem = {
288 .uV = 1800000,
289 .mode = REGULATOR_MODE_NORMAL,
290 .enabled = 1,
291 },
292 .state_disk = {
293 .mode = REGULATOR_MODE_NORMAL,
294 .enabled = 0,
295 },
296 .always_on = 1,
297 .boot_on = 1,
298 .initial_state = PM_SUSPEND_MEM,
299 },
300 };
301
302 static struct regulator_init_data ldo1_data = {
303 .constraints = {
304 .name = "VCAM/VMMC1/VMMC2",
305 .min_uV = 2800000,
306 .max_uV = 2800000,
307 .valid_modes_mask = REGULATOR_MODE_NORMAL,
308 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
309 .apply_uV = 1,
310 },
311 };
312
313 static struct regulator_consumer_supply ldo2_consumers[] = {
314 { .supply = "AVDD", .dev_name = "1-001a" },
315 { .supply = "HPVDD", .dev_name = "1-001a" },
316 };
317
318 /* CODEC and SIM */
319 static struct regulator_init_data ldo2_data = {
320 .constraints = {
321 .name = "VESIM/VSIM/AVDD",
322 .min_uV = 3300000,
323 .max_uV = 3300000,
324 .valid_modes_mask = REGULATOR_MODE_NORMAL,
325 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
326 .apply_uV = 1,
327 },
328 .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
329 .consumer_supplies = ldo2_consumers,
330 };
331
332 /* General */
333 static struct regulator_init_data vdig_data = {
334 .constraints = {
335 .name = "VDIG",
336 .min_uV = 1500000,
337 .max_uV = 1500000,
338 .valid_modes_mask = REGULATOR_MODE_NORMAL,
339 .apply_uV = 1,
340 .always_on = 1,
341 .boot_on = 1,
342 },
343 };
344
345 /* Tranceivers */
346 static struct regulator_init_data ldo4_data = {
347 .constraints = {
348 .name = "VRF1/CVDD_2.775",
349 .min_uV = 2500000,
350 .max_uV = 2500000,
351 .valid_modes_mask = REGULATOR_MODE_NORMAL,
352 .apply_uV = 1,
353 .always_on = 1,
354 .boot_on = 1,
355 },
356 };
357
358 static struct wm8350_led_platform_data wm8350_led_data = {
359 .name = "wm8350:white",
360 .default_trigger = "heartbeat",
361 .max_uA = 27899,
362 };
363
364 static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
365 .vmid_discharge_msecs = 1000,
366 .drain_msecs = 30,
367 .cap_discharge_msecs = 700,
368 .vmid_charge_msecs = 700,
369 .vmid_s_curve = WM8350_S_CURVE_SLOW,
370 .dis_out4 = WM8350_DISCHARGE_SLOW,
371 .dis_out3 = WM8350_DISCHARGE_SLOW,
372 .dis_out2 = WM8350_DISCHARGE_SLOW,
373 .dis_out1 = WM8350_DISCHARGE_SLOW,
374 .vroi_out4 = WM8350_TIE_OFF_500R,
375 .vroi_out3 = WM8350_TIE_OFF_500R,
376 .vroi_out2 = WM8350_TIE_OFF_500R,
377 .vroi_out1 = WM8350_TIE_OFF_500R,
378 .vroi_enable = 0,
379 .codec_current_on = WM8350_CODEC_ISEL_1_0,
380 .codec_current_standby = WM8350_CODEC_ISEL_0_5,
381 .codec_current_charge = WM8350_CODEC_ISEL_1_5,
382 };
383
mx31_wm8350_init(struct wm8350 * wm8350)384 static int mx31_wm8350_init(struct wm8350 *wm8350)
385 {
386 wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
387 WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
388 WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
389 WM8350_GPIO_DEBOUNCE_ON);
390
391 wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
392 WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
393 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
394 WM8350_GPIO_DEBOUNCE_ON);
395
396 wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
397 WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
398 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
399 WM8350_GPIO_DEBOUNCE_OFF);
400
401 wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
402 WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
403 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
404 WM8350_GPIO_DEBOUNCE_OFF);
405
406 wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
407 WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
408 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
409 WM8350_GPIO_DEBOUNCE_OFF);
410
411 wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
412 WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
413 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
414 WM8350_GPIO_DEBOUNCE_OFF);
415
416 wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
417 WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
418 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
419 WM8350_GPIO_DEBOUNCE_OFF);
420
421 wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
422 wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
423 wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
424 wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
425 wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
426 wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
427 wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
428 wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
429
430 /* LEDs */
431 wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
432 WM8350_DC5_ERRACT_SHUTDOWN_CONV);
433 wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
434 WM8350_ISINK_FLASH_DISABLE,
435 WM8350_ISINK_FLASH_TRIG_BIT,
436 WM8350_ISINK_FLASH_DUR_32MS,
437 WM8350_ISINK_FLASH_ON_INSTANT,
438 WM8350_ISINK_FLASH_OFF_INSTANT,
439 WM8350_ISINK_FLASH_MODE_EN);
440 wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
441 WM8350_ISINK_MODE_BOOST,
442 WM8350_ISINK_ILIM_NORMAL,
443 WM8350_DC5_RMP_20V,
444 WM8350_DC5_FBSRC_ISINKA);
445 wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
446 &wm8350_led_data);
447
448 wm8350->codec.platform_data = &imx32ads_wm8350_setup;
449
450 regulator_has_full_constraints();
451
452 return 0;
453 }
454
455 static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
456 .init = mx31_wm8350_init,
457 .irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
458 };
459 #endif
460
461 static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
462 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
463 {
464 I2C_BOARD_INFO("wm8350", 0x1a),
465 .platform_data = &mx31_wm8350_pdata,
466 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
467 },
468 #endif
469 };
470
mxc_init_i2c(void)471 static void __init mxc_init_i2c(void)
472 {
473 i2c_register_board_info(1, mx31ads_i2c1_devices,
474 ARRAY_SIZE(mx31ads_i2c1_devices));
475
476 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
477 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
478
479 imx31_add_imx_i2c1(NULL);
480 }
481
482 static unsigned int ssi_pins[] = {
483 MX31_PIN_SFS5__SFS5,
484 MX31_PIN_SCK5__SCK5,
485 MX31_PIN_SRXD5__SRXD5,
486 MX31_PIN_STXD5__STXD5,
487 };
488
mxc_init_audio(void)489 static void __init mxc_init_audio(void)
490 {
491 imx31_add_imx_ssi(0, NULL);
492 mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
493 }
494
495 /* static mappings */
496 static struct map_desc mx31ads_io_desc[] __initdata = {
497 {
498 .virtual = MX31_CS4_BASE_ADDR_VIRT,
499 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
500 .length = MX31_CS4_SIZE / 2,
501 .type = MT_DEVICE
502 },
503 };
504
mx31ads_map_io(void)505 static void __init mx31ads_map_io(void)
506 {
507 mx31_map_io();
508 iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
509 }
510
mx31ads_init_irq(void)511 static void __init mx31ads_init_irq(void)
512 {
513 mx31_init_irq();
514 mx31ads_init_expio();
515 }
516
mx31ads_init(void)517 static void __init mx31ads_init(void)
518 {
519 imx31_soc_init();
520
521 mxc_init_extuart();
522 mxc_init_imx_uart();
523 mxc_init_i2c();
524 mxc_init_audio();
525 }
526
mx31ads_timer_init(void)527 static void __init mx31ads_timer_init(void)
528 {
529 mx31_clocks_init(26000000);
530 }
531
532 static struct sys_timer mx31ads_timer = {
533 .init = mx31ads_timer_init,
534 };
535
536 MACHINE_START(MX31ADS, "Freescale MX31ADS")
537 /* Maintainer: Freescale Semiconductor, Inc. */
538 .atag_offset = 0x100,
539 .map_io = mx31ads_map_io,
540 .init_early = imx31_init_early,
541 .init_irq = mx31ads_init_irq,
542 .handle_irq = imx31_handle_irq,
543 .timer = &mx31ads_timer,
544 .init_machine = mx31ads_init,
545 .restart = mxc_restart,
546 MACHINE_END
547