1 /*
2 * KZM-ARM11-01 support
3 * Copyright (C) 2009 Yoichi Yuasa <yuasa@linux-mips.org>
4 *
5 * based on code for MX31ADS,
6 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
8 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21 #include <linux/gpio.h>
22 #include <linux/init.h>
23 #include <linux/platform_device.h>
24 #include <linux/serial_8250.h>
25 #include <linux/smsc911x.h>
26 #include <linux/types.h>
27
28 #include <asm/irq.h>
29 #include <asm/mach-types.h>
30 #include <asm/memory.h>
31 #include <asm/setup.h>
32 #include <asm/mach/arch.h>
33 #include <asm/mach/irq.h>
34 #include <asm/mach/map.h>
35 #include <asm/mach/time.h>
36
37 #include <mach/clock.h>
38 #include <mach/common.h>
39 #include <mach/hardware.h>
40 #include <mach/iomux-mx3.h>
41
42 #include "devices-imx31.h"
43
44 #define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \
45 IMX_IO_P2V_MODULE(x, MX31_CS4) ?: \
46 IMX_IO_P2V_MODULE(x, MX31_CS5)) ?: \
47 MX31_IO_ADDRESS(x))
48
49 /*
50 * KZM-ARM11-01 Board Control Registers on FPGA
51 */
52 #define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000)
53 #define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001)
54 #define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002)
55 #define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004)
56 #define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008)
57 #define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010)
58 #define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020)
59 #define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003)
60
61 /*
62 * External UART for touch panel on FPGA
63 */
64 #define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050)
65
66 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
67 /*
68 * KZM-ARM11-01 has an external UART on FPGA
69 */
70 static struct plat_serial8250_port serial_platform_data[] = {
71 {
72 .membase = KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550),
73 .mapbase = KZM_ARM11_16550,
74 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
75 .irqflags = IRQ_TYPE_EDGE_RISING,
76 .uartclk = 14745600,
77 .regshift = 0,
78 .iotype = UPIO_MEM,
79 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
80 UPF_BUGGY_UART,
81 },
82 {},
83 };
84
85 static struct resource serial8250_resources[] = {
86 {
87 .start = KZM_ARM11_16550,
88 .end = KZM_ARM11_16550 + 0x10,
89 .flags = IORESOURCE_MEM,
90 },
91 {
92 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
93 .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
94 .flags = IORESOURCE_IRQ,
95 },
96 };
97
98 static struct platform_device serial_device = {
99 .name = "serial8250",
100 .id = PLAT8250_DEV_PLATFORM,
101 .dev = {
102 .platform_data = serial_platform_data,
103 },
104 .num_resources = ARRAY_SIZE(serial8250_resources),
105 .resource = serial8250_resources,
106 };
107
kzm_init_ext_uart(void)108 static int __init kzm_init_ext_uart(void)
109 {
110 u8 tmp;
111
112 /*
113 * GPIO 1-1: external UART interrupt line
114 */
115 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO));
116 gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "ext-uart-int");
117 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
118
119 /*
120 * Unmask UART interrupt
121 */
122 tmp = __raw_readb(KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
123 tmp |= 0x2;
124 __raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
125
126 return platform_device_register(&serial_device);
127 }
128 #else
kzm_init_ext_uart(void)129 static inline int kzm_init_ext_uart(void)
130 {
131 return 0;
132 }
133 #endif
134
135 /*
136 * SMSC LAN9118
137 */
138 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
139 static struct smsc911x_platform_config kzm_smsc9118_config = {
140 .phy_interface = PHY_INTERFACE_MODE_MII,
141 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
142 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
143 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
144 };
145
146 static struct resource kzm_smsc9118_resources[] = {
147 {
148 .start = MX31_CS5_BASE_ADDR,
149 .end = MX31_CS5_BASE_ADDR + SZ_128K - 1,
150 .flags = IORESOURCE_MEM,
151 },
152 {
153 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
154 .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
155 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
156 },
157 };
158
159 static struct platform_device kzm_smsc9118_device = {
160 .name = "smsc911x",
161 .id = -1,
162 .num_resources = ARRAY_SIZE(kzm_smsc9118_resources),
163 .resource = kzm_smsc9118_resources,
164 .dev = {
165 .platform_data = &kzm_smsc9118_config,
166 },
167 };
168
kzm_init_smsc9118(void)169 static int __init kzm_init_smsc9118(void)
170 {
171 /*
172 * GPIO 1-2: SMSC9118 interrupt line
173 */
174 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO));
175 gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2), "smsc9118-int");
176 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
177
178 return platform_device_register(&kzm_smsc9118_device);
179 }
180 #else
kzm_init_smsc9118(void)181 static inline int kzm_init_smsc9118(void)
182 {
183 return 0;
184 }
185 #endif
186
187 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
188 static const struct imxuart_platform_data uart_pdata __initconst = {
189 .flags = IMXUART_HAVE_RTSCTS,
190 };
191
kzm_init_imx_uart(void)192 static void __init kzm_init_imx_uart(void)
193 {
194 imx31_add_imx_uart0(&uart_pdata);
195 imx31_add_imx_uart1(&uart_pdata);
196 }
197 #else
kzm_init_imx_uart(void)198 static inline void kzm_init_imx_uart(void)
199 {
200 }
201 #endif
202
203 static int kzm_pins[] __initdata = {
204 MX31_PIN_CTS1__CTS1,
205 MX31_PIN_RTS1__RTS1,
206 MX31_PIN_TXD1__TXD1,
207 MX31_PIN_RXD1__RXD1,
208 MX31_PIN_DCD_DCE1__DCD_DCE1,
209 MX31_PIN_RI_DCE1__RI_DCE1,
210 MX31_PIN_DSR_DCE1__DSR_DCE1,
211 MX31_PIN_DTR_DCE1__DTR_DCE1,
212 MX31_PIN_CTS2__CTS2,
213 MX31_PIN_RTS2__RTS2,
214 MX31_PIN_TXD2__TXD2,
215 MX31_PIN_RXD2__RXD2,
216 MX31_PIN_DCD_DTE1__DCD_DTE2,
217 MX31_PIN_RI_DTE1__RI_DTE2,
218 MX31_PIN_DSR_DTE1__DSR_DTE2,
219 MX31_PIN_DTR_DTE1__DTR_DTE2,
220 };
221
222 /*
223 * Board specific initialization.
224 */
kzm_board_init(void)225 static void __init kzm_board_init(void)
226 {
227 imx31_soc_init();
228
229 mxc_iomux_setup_multiple_pins(kzm_pins,
230 ARRAY_SIZE(kzm_pins), "kzm");
231 kzm_init_ext_uart();
232 kzm_init_smsc9118();
233 kzm_init_imx_uart();
234
235 pr_info("Clock input source is 26MHz\n");
236 }
237
238 /*
239 * This structure defines static mappings for the kzm-arm11-01 board.
240 */
241 static struct map_desc kzm_io_desc[] __initdata = {
242 {
243 .virtual = MX31_CS4_BASE_ADDR_VIRT,
244 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
245 .length = MX31_CS4_SIZE,
246 .type = MT_DEVICE
247 },
248 {
249 .virtual = MX31_CS5_BASE_ADDR_VIRT,
250 .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
251 .length = MX31_CS5_SIZE,
252 .type = MT_DEVICE
253 },
254 };
255
256 /*
257 * Set up static virtual mappings.
258 */
kzm_map_io(void)259 static void __init kzm_map_io(void)
260 {
261 mx31_map_io();
262 iotable_init(kzm_io_desc, ARRAY_SIZE(kzm_io_desc));
263 }
264
kzm_timer_init(void)265 static void __init kzm_timer_init(void)
266 {
267 mx31_clocks_init(26000000);
268 }
269
270 static struct sys_timer kzm_timer = {
271 .init = kzm_timer_init,
272 };
273
274 MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
275 .atag_offset = 0x100,
276 .map_io = kzm_map_io,
277 .init_early = imx31_init_early,
278 .init_irq = mx31_init_irq,
279 .handle_irq = imx31_handle_irq,
280 .timer = &kzm_timer,
281 .init_machine = kzm_board_init,
282 .restart = mxc_restart,
283 MACHINE_END
284