1 /*
2 * linux/arch/arm/mach-exynos4/clock-exynos4212.c
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * EXYNOS4212 - Clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
17 #include <linux/io.h>
18 #include <linux/syscore_ops.h>
19
20 #include <plat/cpu-freq.h>
21 #include <plat/clock.h>
22 #include <plat/cpu.h>
23 #include <plat/pll.h>
24 #include <plat/s5p-clock.h>
25 #include <plat/clock-clksrc.h>
26 #include <plat/pm.h>
27
28 #include <mach/hardware.h>
29 #include <mach/map.h>
30 #include <mach/regs-clock.h>
31 #include <mach/exynos4-clock.h>
32
33 #include "common.h"
34
35 #ifdef CONFIG_PM_SLEEP
36 static struct sleep_save exynos4212_clock_save[] = {
37 SAVE_ITEM(S5P_CLKSRC_IMAGE),
38 SAVE_ITEM(S5P_CLKDIV_IMAGE),
39 SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
40 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
41 };
42 #endif
43
44 static struct clk *clk_src_mpll_user_list[] = {
45 [0] = &clk_fin_mpll,
46 [1] = &clk_mout_mpll.clk,
47 };
48
49 static struct clksrc_sources clk_src_mpll_user = {
50 .sources = clk_src_mpll_user_list,
51 .nr_sources = ARRAY_SIZE(clk_src_mpll_user_list),
52 };
53
54 static struct clksrc_clk clk_mout_mpll_user = {
55 .clk = {
56 .name = "mout_mpll_user",
57 },
58 .sources = &clk_src_mpll_user,
59 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },
60 };
61
62 static struct clksrc_clk *sysclks[] = {
63 &clk_mout_mpll_user,
64 };
65
66 static struct clksrc_clk clksrcs[] = {
67 /* nothing here yet */
68 };
69
70 static struct clk init_clocks_off[] = {
71 /* nothing here yet */
72 };
73
74 #ifdef CONFIG_PM_SLEEP
exynos4212_clock_suspend(void)75 static int exynos4212_clock_suspend(void)
76 {
77 s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
78
79 return 0;
80 }
81
exynos4212_clock_resume(void)82 static void exynos4212_clock_resume(void)
83 {
84 s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
85 }
86
87 #else
88 #define exynos4212_clock_suspend NULL
89 #define exynos4212_clock_resume NULL
90 #endif
91
92 struct syscore_ops exynos4212_clock_syscore_ops = {
93 .suspend = exynos4212_clock_suspend,
94 .resume = exynos4212_clock_resume,
95 };
96
exynos4212_register_clocks(void)97 void __init exynos4212_register_clocks(void)
98 {
99 int ptr;
100
101 /* usbphy1 is removed */
102 clkset_group_list[4] = NULL;
103
104 /* mout_mpll_user is used */
105 clkset_group_list[6] = &clk_mout_mpll_user.clk;
106 clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
107
108 clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;
109 clk_mout_mpll.reg_src.shift = 12;
110 clk_mout_mpll.reg_src.size = 1;
111
112 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
113 s3c_register_clksrc(sysclks[ptr], 1);
114
115 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
116
117 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
118 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
119
120 register_syscore_ops(&exynos4212_clock_syscore_ops);
121 }
122