1 /*
2 * arch/arm/mach-dove/addr-map.c
3 *
4 * Address map functions for Marvell Dove 88AP510 SoC
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/mbus.h>
14 #include <linux/io.h>
15 #include <asm/mach/arch.h>
16 #include <asm/setup.h>
17 #include <plat/addr-map.h>
18 #include "common.h"
19
20 /*
21 * Generic Address Decode Windows bit settings
22 */
23 #define TARGET_DDR 0x0
24 #define TARGET_BOOTROM 0x1
25 #define TARGET_CESA 0x3
26 #define TARGET_PCIE0 0x4
27 #define TARGET_PCIE1 0x8
28 #define TARGET_SCRATCHPAD 0xd
29
30 #define ATTR_CESA 0x01
31 #define ATTR_BOOTROM 0xfd
32 #define ATTR_DEV_SPI0_ROM 0xfe
33 #define ATTR_DEV_SPI1_ROM 0xfb
34 #define ATTR_PCIE_IO 0xe0
35 #define ATTR_PCIE_MEM 0xe8
36 #define ATTR_SCRATCHPAD 0x0
37
ddr_map_sc(int i)38 static inline void __iomem *ddr_map_sc(int i)
39 {
40 return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4));
41 }
42
43 /*
44 * Description of the windows needed by the platform code
45 */
46 static struct __initdata orion_addr_map_cfg addr_map_cfg = {
47 .num_wins = 8,
48 .remappable_wins = 4,
49 .bridge_virt_base = BRIDGE_VIRT_BASE,
50 };
51
52 static const struct __initdata orion_addr_map_info addr_map_info[] = {
53 /*
54 * Windows for PCIe IO+MEM space.
55 */
56 { 0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE,
57 TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE
58 },
59 { 1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE,
60 TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE
61 },
62 { 2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE,
63 TARGET_PCIE0, ATTR_PCIE_MEM, -1
64 },
65 { 3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE,
66 TARGET_PCIE1, ATTR_PCIE_MEM, -1
67 },
68 /*
69 * Window for CESA engine.
70 */
71 { 4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE,
72 TARGET_CESA, ATTR_CESA, -1
73 },
74 /*
75 * Window to the BootROM for Standby and Sleep Resume
76 */
77 { 5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE,
78 TARGET_BOOTROM, ATTR_BOOTROM, -1
79 },
80 /*
81 * Window to the PMU Scratch Pad space
82 */
83 { 6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE,
84 TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1
85 },
86 /* End marker */
87 { -1, 0, 0, 0, 0, 0 }
88 };
89
dove_setup_cpu_mbus(void)90 void __init dove_setup_cpu_mbus(void)
91 {
92 int i;
93 int cs;
94
95 /*
96 * Disable, clear and configure windows.
97 */
98 orion_config_wins(&addr_map_cfg, addr_map_info);
99
100 /*
101 * Setup MBUS dram target info.
102 */
103 orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
104
105 for (i = 0, cs = 0; i < 2; i++) {
106 u32 map = readl(ddr_map_sc(i));
107
108 /*
109 * Chip select enabled?
110 */
111 if (map & 1) {
112 struct mbus_dram_window *w;
113
114 w = &orion_mbus_dram_info.cs[cs++];
115 w->cs_index = i;
116 w->mbus_attr = 0; /* CS address decoding done inside */
117 /* the DDR controller, no need to */
118 /* provide attributes */
119 w->base = map & 0xff800000;
120 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
121 }
122 }
123 orion_mbus_dram_info.num_cs = cs;
124 }
125