1 /*
2 * TI DaVinci DM644x chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11 #include <linux/init.h>
12 #include <linux/clk.h>
13 #include <linux/serial_8250.h>
14 #include <linux/platform_device.h>
15
16 #include <asm/mach/map.h>
17
18 #include <mach/dm644x.h>
19 #include <mach/cputype.h>
20 #include <mach/edma.h>
21 #include <mach/irqs.h>
22 #include <mach/psc.h>
23 #include <mach/mux.h>
24 #include <mach/time.h>
25 #include <mach/serial.h>
26 #include <mach/common.h>
27 #include <mach/asp.h>
28 #include <mach/gpio-davinci.h>
29
30 #include "clock.h"
31 #include "mux.h"
32
33 /*
34 * Device specific clocks
35 */
36 #define DM644X_REF_FREQ 27000000
37
38 static struct pll_data pll1_data = {
39 .num = 1,
40 .phys_base = DAVINCI_PLL1_BASE,
41 };
42
43 static struct pll_data pll2_data = {
44 .num = 2,
45 .phys_base = DAVINCI_PLL2_BASE,
46 };
47
48 static struct clk ref_clk = {
49 .name = "ref_clk",
50 .rate = DM644X_REF_FREQ,
51 };
52
53 static struct clk pll1_clk = {
54 .name = "pll1",
55 .parent = &ref_clk,
56 .pll_data = &pll1_data,
57 .flags = CLK_PLL,
58 };
59
60 static struct clk pll1_sysclk1 = {
61 .name = "pll1_sysclk1",
62 .parent = &pll1_clk,
63 .flags = CLK_PLL,
64 .div_reg = PLLDIV1,
65 };
66
67 static struct clk pll1_sysclk2 = {
68 .name = "pll1_sysclk2",
69 .parent = &pll1_clk,
70 .flags = CLK_PLL,
71 .div_reg = PLLDIV2,
72 };
73
74 static struct clk pll1_sysclk3 = {
75 .name = "pll1_sysclk3",
76 .parent = &pll1_clk,
77 .flags = CLK_PLL,
78 .div_reg = PLLDIV3,
79 };
80
81 static struct clk pll1_sysclk5 = {
82 .name = "pll1_sysclk5",
83 .parent = &pll1_clk,
84 .flags = CLK_PLL,
85 .div_reg = PLLDIV5,
86 };
87
88 static struct clk pll1_aux_clk = {
89 .name = "pll1_aux_clk",
90 .parent = &pll1_clk,
91 .flags = CLK_PLL | PRE_PLL,
92 };
93
94 static struct clk pll1_sysclkbp = {
95 .name = "pll1_sysclkbp",
96 .parent = &pll1_clk,
97 .flags = CLK_PLL | PRE_PLL,
98 .div_reg = BPDIV
99 };
100
101 static struct clk pll2_clk = {
102 .name = "pll2",
103 .parent = &ref_clk,
104 .pll_data = &pll2_data,
105 .flags = CLK_PLL,
106 };
107
108 static struct clk pll2_sysclk1 = {
109 .name = "pll2_sysclk1",
110 .parent = &pll2_clk,
111 .flags = CLK_PLL,
112 .div_reg = PLLDIV1,
113 };
114
115 static struct clk pll2_sysclk2 = {
116 .name = "pll2_sysclk2",
117 .parent = &pll2_clk,
118 .flags = CLK_PLL,
119 .div_reg = PLLDIV2,
120 };
121
122 static struct clk pll2_sysclkbp = {
123 .name = "pll2_sysclkbp",
124 .parent = &pll2_clk,
125 .flags = CLK_PLL | PRE_PLL,
126 .div_reg = BPDIV
127 };
128
129 static struct clk dsp_clk = {
130 .name = "dsp",
131 .parent = &pll1_sysclk1,
132 .lpsc = DAVINCI_LPSC_GEM,
133 .domain = DAVINCI_GPSC_DSPDOMAIN,
134 .usecount = 1, /* REVISIT how to disable? */
135 };
136
137 static struct clk arm_clk = {
138 .name = "arm",
139 .parent = &pll1_sysclk2,
140 .lpsc = DAVINCI_LPSC_ARM,
141 .flags = ALWAYS_ENABLED,
142 };
143
144 static struct clk vicp_clk = {
145 .name = "vicp",
146 .parent = &pll1_sysclk2,
147 .lpsc = DAVINCI_LPSC_IMCOP,
148 .domain = DAVINCI_GPSC_DSPDOMAIN,
149 .usecount = 1, /* REVISIT how to disable? */
150 };
151
152 static struct clk vpss_master_clk = {
153 .name = "vpss_master",
154 .parent = &pll1_sysclk3,
155 .lpsc = DAVINCI_LPSC_VPSSMSTR,
156 .flags = CLK_PSC,
157 };
158
159 static struct clk vpss_slave_clk = {
160 .name = "vpss_slave",
161 .parent = &pll1_sysclk3,
162 .lpsc = DAVINCI_LPSC_VPSSSLV,
163 };
164
165 static struct clk uart0_clk = {
166 .name = "uart0",
167 .parent = &pll1_aux_clk,
168 .lpsc = DAVINCI_LPSC_UART0,
169 };
170
171 static struct clk uart1_clk = {
172 .name = "uart1",
173 .parent = &pll1_aux_clk,
174 .lpsc = DAVINCI_LPSC_UART1,
175 };
176
177 static struct clk uart2_clk = {
178 .name = "uart2",
179 .parent = &pll1_aux_clk,
180 .lpsc = DAVINCI_LPSC_UART2,
181 };
182
183 static struct clk emac_clk = {
184 .name = "emac",
185 .parent = &pll1_sysclk5,
186 .lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
187 };
188
189 static struct clk i2c_clk = {
190 .name = "i2c",
191 .parent = &pll1_aux_clk,
192 .lpsc = DAVINCI_LPSC_I2C,
193 };
194
195 static struct clk ide_clk = {
196 .name = "ide",
197 .parent = &pll1_sysclk5,
198 .lpsc = DAVINCI_LPSC_ATA,
199 };
200
201 static struct clk asp_clk = {
202 .name = "asp0",
203 .parent = &pll1_sysclk5,
204 .lpsc = DAVINCI_LPSC_McBSP,
205 };
206
207 static struct clk mmcsd_clk = {
208 .name = "mmcsd",
209 .parent = &pll1_sysclk5,
210 .lpsc = DAVINCI_LPSC_MMC_SD,
211 };
212
213 static struct clk spi_clk = {
214 .name = "spi",
215 .parent = &pll1_sysclk5,
216 .lpsc = DAVINCI_LPSC_SPI,
217 };
218
219 static struct clk gpio_clk = {
220 .name = "gpio",
221 .parent = &pll1_sysclk5,
222 .lpsc = DAVINCI_LPSC_GPIO,
223 };
224
225 static struct clk usb_clk = {
226 .name = "usb",
227 .parent = &pll1_sysclk5,
228 .lpsc = DAVINCI_LPSC_USB,
229 };
230
231 static struct clk vlynq_clk = {
232 .name = "vlynq",
233 .parent = &pll1_sysclk5,
234 .lpsc = DAVINCI_LPSC_VLYNQ,
235 };
236
237 static struct clk aemif_clk = {
238 .name = "aemif",
239 .parent = &pll1_sysclk5,
240 .lpsc = DAVINCI_LPSC_AEMIF,
241 };
242
243 static struct clk pwm0_clk = {
244 .name = "pwm0",
245 .parent = &pll1_aux_clk,
246 .lpsc = DAVINCI_LPSC_PWM0,
247 };
248
249 static struct clk pwm1_clk = {
250 .name = "pwm1",
251 .parent = &pll1_aux_clk,
252 .lpsc = DAVINCI_LPSC_PWM1,
253 };
254
255 static struct clk pwm2_clk = {
256 .name = "pwm2",
257 .parent = &pll1_aux_clk,
258 .lpsc = DAVINCI_LPSC_PWM2,
259 };
260
261 static struct clk timer0_clk = {
262 .name = "timer0",
263 .parent = &pll1_aux_clk,
264 .lpsc = DAVINCI_LPSC_TIMER0,
265 };
266
267 static struct clk timer1_clk = {
268 .name = "timer1",
269 .parent = &pll1_aux_clk,
270 .lpsc = DAVINCI_LPSC_TIMER1,
271 };
272
273 static struct clk timer2_clk = {
274 .name = "timer2",
275 .parent = &pll1_aux_clk,
276 .lpsc = DAVINCI_LPSC_TIMER2,
277 .usecount = 1, /* REVISIT: why can't this be disabled? */
278 };
279
280 static struct clk_lookup dm644x_clks[] = {
281 CLK(NULL, "ref", &ref_clk),
282 CLK(NULL, "pll1", &pll1_clk),
283 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
284 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
285 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
286 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
287 CLK(NULL, "pll1_aux", &pll1_aux_clk),
288 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
289 CLK(NULL, "pll2", &pll2_clk),
290 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
291 CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
292 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
293 CLK(NULL, "dsp", &dsp_clk),
294 CLK(NULL, "arm", &arm_clk),
295 CLK(NULL, "vicp", &vicp_clk),
296 CLK(NULL, "vpss_master", &vpss_master_clk),
297 CLK(NULL, "vpss_slave", &vpss_slave_clk),
298 CLK(NULL, "arm", &arm_clk),
299 CLK(NULL, "uart0", &uart0_clk),
300 CLK(NULL, "uart1", &uart1_clk),
301 CLK(NULL, "uart2", &uart2_clk),
302 CLK("davinci_emac.1", NULL, &emac_clk),
303 CLK("i2c_davinci.1", NULL, &i2c_clk),
304 CLK("palm_bk3710", NULL, &ide_clk),
305 CLK("davinci-mcbsp", NULL, &asp_clk),
306 CLK("davinci_mmc.0", NULL, &mmcsd_clk),
307 CLK(NULL, "spi", &spi_clk),
308 CLK(NULL, "gpio", &gpio_clk),
309 CLK(NULL, "usb", &usb_clk),
310 CLK(NULL, "vlynq", &vlynq_clk),
311 CLK(NULL, "aemif", &aemif_clk),
312 CLK(NULL, "pwm0", &pwm0_clk),
313 CLK(NULL, "pwm1", &pwm1_clk),
314 CLK(NULL, "pwm2", &pwm2_clk),
315 CLK(NULL, "timer0", &timer0_clk),
316 CLK(NULL, "timer1", &timer1_clk),
317 CLK("watchdog", NULL, &timer2_clk),
318 CLK(NULL, NULL, NULL),
319 };
320
321 static struct emac_platform_data dm644x_emac_pdata = {
322 .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET,
323 .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET,
324 .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET,
325 .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE,
326 .version = EMAC_VERSION_1,
327 };
328
329 static struct resource dm644x_emac_resources[] = {
330 {
331 .start = DM644X_EMAC_BASE,
332 .end = DM644X_EMAC_BASE + SZ_16K - 1,
333 .flags = IORESOURCE_MEM,
334 },
335 {
336 .start = IRQ_EMACINT,
337 .end = IRQ_EMACINT,
338 .flags = IORESOURCE_IRQ,
339 },
340 };
341
342 static struct platform_device dm644x_emac_device = {
343 .name = "davinci_emac",
344 .id = 1,
345 .dev = {
346 .platform_data = &dm644x_emac_pdata,
347 },
348 .num_resources = ARRAY_SIZE(dm644x_emac_resources),
349 .resource = dm644x_emac_resources,
350 };
351
352 static struct resource dm644x_mdio_resources[] = {
353 {
354 .start = DM644X_EMAC_MDIO_BASE,
355 .end = DM644X_EMAC_MDIO_BASE + SZ_4K - 1,
356 .flags = IORESOURCE_MEM,
357 },
358 };
359
360 static struct platform_device dm644x_mdio_device = {
361 .name = "davinci_mdio",
362 .id = 0,
363 .num_resources = ARRAY_SIZE(dm644x_mdio_resources),
364 .resource = dm644x_mdio_resources,
365 };
366
367 /*
368 * Device specific mux setup
369 *
370 * soc description mux mode mode mux dbg
371 * reg offset mask mode
372 */
373 static const struct mux_config dm644x_pins[] = {
374 #ifdef CONFIG_DAVINCI_MUX
375 MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
376 MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
377 MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
378
379 MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
380
381 MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
382 MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true)
383 MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true)
384 MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true)
385 MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true)
386 MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true)
387
388 MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
389
390 MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false)
391
392 MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false)
393
394 MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true)
395 MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true)
396
397 MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false)
398
399 MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false)
400
401 MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false)
402
403 MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false)
404 MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false)
405 MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false)
406
407 MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true)
408
409 MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true)
410
411 MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true)
412 MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false)
413 MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false)
414 MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true)
415
416 MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
417
418 MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
419 MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
420 #endif
421 };
422
423 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
424 static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
425 [IRQ_VDINT0] = 2,
426 [IRQ_VDINT1] = 6,
427 [IRQ_VDINT2] = 6,
428 [IRQ_HISTINT] = 6,
429 [IRQ_H3AINT] = 6,
430 [IRQ_PRVUINT] = 6,
431 [IRQ_RSZINT] = 6,
432 [7] = 7,
433 [IRQ_VENCINT] = 6,
434 [IRQ_ASQINT] = 6,
435 [IRQ_IMXINT] = 6,
436 [IRQ_VLCDINT] = 6,
437 [IRQ_USBINT] = 4,
438 [IRQ_EMACINT] = 4,
439 [14] = 7,
440 [15] = 7,
441 [IRQ_CCINT0] = 5, /* dma */
442 [IRQ_CCERRINT] = 5, /* dma */
443 [IRQ_TCERRINT0] = 5, /* dma */
444 [IRQ_TCERRINT] = 5, /* dma */
445 [IRQ_PSCIN] = 7,
446 [21] = 7,
447 [IRQ_IDE] = 4,
448 [23] = 7,
449 [IRQ_MBXINT] = 7,
450 [IRQ_MBRINT] = 7,
451 [IRQ_MMCINT] = 7,
452 [IRQ_SDIOINT] = 7,
453 [28] = 7,
454 [IRQ_DDRINT] = 7,
455 [IRQ_AEMIFINT] = 7,
456 [IRQ_VLQINT] = 4,
457 [IRQ_TINT0_TINT12] = 2, /* clockevent */
458 [IRQ_TINT0_TINT34] = 2, /* clocksource */
459 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
460 [IRQ_TINT1_TINT34] = 7, /* system tick */
461 [IRQ_PWMINT0] = 7,
462 [IRQ_PWMINT1] = 7,
463 [IRQ_PWMINT2] = 7,
464 [IRQ_I2C] = 3,
465 [IRQ_UARTINT0] = 3,
466 [IRQ_UARTINT1] = 3,
467 [IRQ_UARTINT2] = 3,
468 [IRQ_SPINT0] = 3,
469 [IRQ_SPINT1] = 3,
470 [45] = 7,
471 [IRQ_DSP2ARM0] = 4,
472 [IRQ_DSP2ARM1] = 4,
473 [IRQ_GPIO0] = 7,
474 [IRQ_GPIO1] = 7,
475 [IRQ_GPIO2] = 7,
476 [IRQ_GPIO3] = 7,
477 [IRQ_GPIO4] = 7,
478 [IRQ_GPIO5] = 7,
479 [IRQ_GPIO6] = 7,
480 [IRQ_GPIO7] = 7,
481 [IRQ_GPIOBNK0] = 7,
482 [IRQ_GPIOBNK1] = 7,
483 [IRQ_GPIOBNK2] = 7,
484 [IRQ_GPIOBNK3] = 7,
485 [IRQ_GPIOBNK4] = 7,
486 [IRQ_COMMTX] = 7,
487 [IRQ_COMMRX] = 7,
488 [IRQ_EMUINT] = 7,
489 };
490
491 /*----------------------------------------------------------------------*/
492
493 static const s8
494 queue_tc_mapping[][2] = {
495 /* {event queue no, TC no} */
496 {0, 0},
497 {1, 1},
498 {-1, -1},
499 };
500
501 static const s8
502 queue_priority_mapping[][2] = {
503 /* {event queue no, Priority} */
504 {0, 3},
505 {1, 7},
506 {-1, -1},
507 };
508
509 static struct edma_soc_info edma_cc0_info = {
510 .n_channel = 64,
511 .n_region = 4,
512 .n_slot = 128,
513 .n_tc = 2,
514 .n_cc = 1,
515 .queue_tc_mapping = queue_tc_mapping,
516 .queue_priority_mapping = queue_priority_mapping,
517 .default_queue = EVENTQ_1,
518 };
519
520 static struct edma_soc_info *dm644x_edma_info[EDMA_MAX_CC] = {
521 &edma_cc0_info,
522 };
523
524 static struct resource edma_resources[] = {
525 {
526 .name = "edma_cc0",
527 .start = 0x01c00000,
528 .end = 0x01c00000 + SZ_64K - 1,
529 .flags = IORESOURCE_MEM,
530 },
531 {
532 .name = "edma_tc0",
533 .start = 0x01c10000,
534 .end = 0x01c10000 + SZ_1K - 1,
535 .flags = IORESOURCE_MEM,
536 },
537 {
538 .name = "edma_tc1",
539 .start = 0x01c10400,
540 .end = 0x01c10400 + SZ_1K - 1,
541 .flags = IORESOURCE_MEM,
542 },
543 {
544 .name = "edma0",
545 .start = IRQ_CCINT0,
546 .flags = IORESOURCE_IRQ,
547 },
548 {
549 .name = "edma0_err",
550 .start = IRQ_CCERRINT,
551 .flags = IORESOURCE_IRQ,
552 },
553 /* not using TC*_ERR */
554 };
555
556 static struct platform_device dm644x_edma_device = {
557 .name = "edma",
558 .id = 0,
559 .dev.platform_data = dm644x_edma_info,
560 .num_resources = ARRAY_SIZE(edma_resources),
561 .resource = edma_resources,
562 };
563
564 /* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
565 static struct resource dm644x_asp_resources[] = {
566 {
567 .start = DAVINCI_ASP0_BASE,
568 .end = DAVINCI_ASP0_BASE + SZ_8K - 1,
569 .flags = IORESOURCE_MEM,
570 },
571 {
572 .start = DAVINCI_DMA_ASP0_TX,
573 .end = DAVINCI_DMA_ASP0_TX,
574 .flags = IORESOURCE_DMA,
575 },
576 {
577 .start = DAVINCI_DMA_ASP0_RX,
578 .end = DAVINCI_DMA_ASP0_RX,
579 .flags = IORESOURCE_DMA,
580 },
581 };
582
583 static struct platform_device dm644x_asp_device = {
584 .name = "davinci-mcbsp",
585 .id = -1,
586 .num_resources = ARRAY_SIZE(dm644x_asp_resources),
587 .resource = dm644x_asp_resources,
588 };
589
590 static struct resource dm644x_vpss_resources[] = {
591 {
592 /* VPSS Base address */
593 .name = "vpss",
594 .start = 0x01c73400,
595 .end = 0x01c73400 + 0xff,
596 .flags = IORESOURCE_MEM,
597 },
598 };
599
600 static struct platform_device dm644x_vpss_device = {
601 .name = "vpss",
602 .id = -1,
603 .dev.platform_data = "dm644x_vpss",
604 .num_resources = ARRAY_SIZE(dm644x_vpss_resources),
605 .resource = dm644x_vpss_resources,
606 };
607
608 static struct resource vpfe_resources[] = {
609 {
610 .start = IRQ_VDINT0,
611 .end = IRQ_VDINT0,
612 .flags = IORESOURCE_IRQ,
613 },
614 {
615 .start = IRQ_VDINT1,
616 .end = IRQ_VDINT1,
617 .flags = IORESOURCE_IRQ,
618 },
619 };
620
621 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
622 static struct resource dm644x_ccdc_resource[] = {
623 /* CCDC Base address */
624 {
625 .start = 0x01c70400,
626 .end = 0x01c70400 + 0xff,
627 .flags = IORESOURCE_MEM,
628 },
629 };
630
631 static struct platform_device dm644x_ccdc_dev = {
632 .name = "dm644x_ccdc",
633 .id = -1,
634 .num_resources = ARRAY_SIZE(dm644x_ccdc_resource),
635 .resource = dm644x_ccdc_resource,
636 .dev = {
637 .dma_mask = &vpfe_capture_dma_mask,
638 .coherent_dma_mask = DMA_BIT_MASK(32),
639 },
640 };
641
642 static struct platform_device vpfe_capture_dev = {
643 .name = CAPTURE_DRV_NAME,
644 .id = -1,
645 .num_resources = ARRAY_SIZE(vpfe_resources),
646 .resource = vpfe_resources,
647 .dev = {
648 .dma_mask = &vpfe_capture_dma_mask,
649 .coherent_dma_mask = DMA_BIT_MASK(32),
650 },
651 };
652
dm644x_set_vpfe_config(struct vpfe_config * cfg)653 void dm644x_set_vpfe_config(struct vpfe_config *cfg)
654 {
655 vpfe_capture_dev.dev.platform_data = cfg;
656 }
657
658 /*----------------------------------------------------------------------*/
659
660 static struct map_desc dm644x_io_desc[] = {
661 {
662 .virtual = IO_VIRT,
663 .pfn = __phys_to_pfn(IO_PHYS),
664 .length = IO_SIZE,
665 .type = MT_DEVICE
666 },
667 {
668 .virtual = SRAM_VIRT,
669 .pfn = __phys_to_pfn(0x00008000),
670 .length = SZ_16K,
671 .type = MT_MEMORY_NONCACHED,
672 },
673 };
674
675 /* Contents of JTAG ID register used to identify exact cpu type */
676 static struct davinci_id dm644x_ids[] = {
677 {
678 .variant = 0x0,
679 .part_no = 0xb700,
680 .manufacturer = 0x017,
681 .cpu_id = DAVINCI_CPU_ID_DM6446,
682 .name = "dm6446",
683 },
684 {
685 .variant = 0x1,
686 .part_no = 0xb700,
687 .manufacturer = 0x017,
688 .cpu_id = DAVINCI_CPU_ID_DM6446,
689 .name = "dm6446a",
690 },
691 };
692
693 static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
694
695 /*
696 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
697 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
698 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
699 * T1_TOP: Timer 1, top : <unused>
700 */
701 static struct davinci_timer_info dm644x_timer_info = {
702 .timers = davinci_timer_instance,
703 .clockevent_id = T0_BOT,
704 .clocksource_id = T0_TOP,
705 };
706
707 static struct plat_serial8250_port dm644x_serial_platform_data[] = {
708 {
709 .mapbase = DAVINCI_UART0_BASE,
710 .irq = IRQ_UARTINT0,
711 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
712 UPF_IOREMAP,
713 .iotype = UPIO_MEM,
714 .regshift = 2,
715 },
716 {
717 .mapbase = DAVINCI_UART1_BASE,
718 .irq = IRQ_UARTINT1,
719 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
720 UPF_IOREMAP,
721 .iotype = UPIO_MEM,
722 .regshift = 2,
723 },
724 {
725 .mapbase = DAVINCI_UART2_BASE,
726 .irq = IRQ_UARTINT2,
727 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
728 UPF_IOREMAP,
729 .iotype = UPIO_MEM,
730 .regshift = 2,
731 },
732 {
733 .flags = 0
734 },
735 };
736
737 static struct platform_device dm644x_serial_device = {
738 .name = "serial8250",
739 .id = PLAT8250_DEV_PLATFORM,
740 .dev = {
741 .platform_data = dm644x_serial_platform_data,
742 },
743 };
744
745 static struct davinci_soc_info davinci_soc_info_dm644x = {
746 .io_desc = dm644x_io_desc,
747 .io_desc_num = ARRAY_SIZE(dm644x_io_desc),
748 .jtag_id_reg = 0x01c40028,
749 .ids = dm644x_ids,
750 .ids_num = ARRAY_SIZE(dm644x_ids),
751 .cpu_clks = dm644x_clks,
752 .psc_bases = dm644x_psc_bases,
753 .psc_bases_num = ARRAY_SIZE(dm644x_psc_bases),
754 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
755 .pinmux_pins = dm644x_pins,
756 .pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
757 .intc_base = DAVINCI_ARM_INTC_BASE,
758 .intc_type = DAVINCI_INTC_TYPE_AINTC,
759 .intc_irq_prios = dm644x_default_priorities,
760 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
761 .timer_info = &dm644x_timer_info,
762 .gpio_type = GPIO_TYPE_DAVINCI,
763 .gpio_base = DAVINCI_GPIO_BASE,
764 .gpio_num = 71,
765 .gpio_irq = IRQ_GPIOBNK0,
766 .serial_dev = &dm644x_serial_device,
767 .emac_pdata = &dm644x_emac_pdata,
768 .sram_dma = 0x00008000,
769 .sram_len = SZ_16K,
770 };
771
dm644x_init_asp(struct snd_platform_data * pdata)772 void __init dm644x_init_asp(struct snd_platform_data *pdata)
773 {
774 davinci_cfg_reg(DM644X_MCBSP);
775 dm644x_asp_device.dev.platform_data = pdata;
776 platform_device_register(&dm644x_asp_device);
777 }
778
dm644x_init(void)779 void __init dm644x_init(void)
780 {
781 davinci_common_init(&davinci_soc_info_dm644x);
782 }
783
dm644x_init_devices(void)784 static int __init dm644x_init_devices(void)
785 {
786 if (!cpu_is_davinci_dm644x())
787 return 0;
788
789 /* Add ccdc clock aliases */
790 clk_add_alias("master", dm644x_ccdc_dev.name, "vpss_master", NULL);
791 clk_add_alias("slave", dm644x_ccdc_dev.name, "vpss_slave", NULL);
792 platform_device_register(&dm644x_edma_device);
793
794 platform_device_register(&dm644x_mdio_device);
795 platform_device_register(&dm644x_emac_device);
796 clk_add_alias(NULL, dev_name(&dm644x_mdio_device.dev),
797 NULL, &dm644x_emac_device.dev);
798
799 platform_device_register(&dm644x_vpss_device);
800 platform_device_register(&dm644x_ccdc_dev);
801 platform_device_register(&vpfe_capture_dev);
802
803 return 0;
804 }
805 postcore_initcall(dm644x_init_devices);
806