1 /*
2 * TI DaVinci DM365 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15 #include <linux/init.h>
16 #include <linux/clk.h>
17 #include <linux/serial_8250.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/spi/spi.h>
21
22 #include <asm/mach/map.h>
23
24 #include <mach/dm365.h>
25 #include <mach/cputype.h>
26 #include <mach/edma.h>
27 #include <mach/psc.h>
28 #include <mach/mux.h>
29 #include <mach/irqs.h>
30 #include <mach/time.h>
31 #include <mach/serial.h>
32 #include <mach/common.h>
33 #include <mach/asp.h>
34 #include <mach/keyscan.h>
35 #include <mach/spi.h>
36 #include <mach/gpio-davinci.h>
37
38 #include "clock.h"
39 #include "mux.h"
40
41 #define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
42
43 static struct pll_data pll1_data = {
44 .num = 1,
45 .phys_base = DAVINCI_PLL1_BASE,
46 .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
47 };
48
49 static struct pll_data pll2_data = {
50 .num = 2,
51 .phys_base = DAVINCI_PLL2_BASE,
52 .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
53 };
54
55 static struct clk ref_clk = {
56 .name = "ref_clk",
57 .rate = DM365_REF_FREQ,
58 };
59
60 static struct clk pll1_clk = {
61 .name = "pll1",
62 .parent = &ref_clk,
63 .flags = CLK_PLL,
64 .pll_data = &pll1_data,
65 };
66
67 static struct clk pll1_aux_clk = {
68 .name = "pll1_aux_clk",
69 .parent = &pll1_clk,
70 .flags = CLK_PLL | PRE_PLL,
71 };
72
73 static struct clk pll1_sysclkbp = {
74 .name = "pll1_sysclkbp",
75 .parent = &pll1_clk,
76 .flags = CLK_PLL | PRE_PLL,
77 .div_reg = BPDIV
78 };
79
80 static struct clk clkout0_clk = {
81 .name = "clkout0",
82 .parent = &pll1_clk,
83 .flags = CLK_PLL | PRE_PLL,
84 };
85
86 static struct clk pll1_sysclk1 = {
87 .name = "pll1_sysclk1",
88 .parent = &pll1_clk,
89 .flags = CLK_PLL,
90 .div_reg = PLLDIV1,
91 };
92
93 static struct clk pll1_sysclk2 = {
94 .name = "pll1_sysclk2",
95 .parent = &pll1_clk,
96 .flags = CLK_PLL,
97 .div_reg = PLLDIV2,
98 };
99
100 static struct clk pll1_sysclk3 = {
101 .name = "pll1_sysclk3",
102 .parent = &pll1_clk,
103 .flags = CLK_PLL,
104 .div_reg = PLLDIV3,
105 };
106
107 static struct clk pll1_sysclk4 = {
108 .name = "pll1_sysclk4",
109 .parent = &pll1_clk,
110 .flags = CLK_PLL,
111 .div_reg = PLLDIV4,
112 };
113
114 static struct clk pll1_sysclk5 = {
115 .name = "pll1_sysclk5",
116 .parent = &pll1_clk,
117 .flags = CLK_PLL,
118 .div_reg = PLLDIV5,
119 };
120
121 static struct clk pll1_sysclk6 = {
122 .name = "pll1_sysclk6",
123 .parent = &pll1_clk,
124 .flags = CLK_PLL,
125 .div_reg = PLLDIV6,
126 };
127
128 static struct clk pll1_sysclk7 = {
129 .name = "pll1_sysclk7",
130 .parent = &pll1_clk,
131 .flags = CLK_PLL,
132 .div_reg = PLLDIV7,
133 };
134
135 static struct clk pll1_sysclk8 = {
136 .name = "pll1_sysclk8",
137 .parent = &pll1_clk,
138 .flags = CLK_PLL,
139 .div_reg = PLLDIV8,
140 };
141
142 static struct clk pll1_sysclk9 = {
143 .name = "pll1_sysclk9",
144 .parent = &pll1_clk,
145 .flags = CLK_PLL,
146 .div_reg = PLLDIV9,
147 };
148
149 static struct clk pll2_clk = {
150 .name = "pll2",
151 .parent = &ref_clk,
152 .flags = CLK_PLL,
153 .pll_data = &pll2_data,
154 };
155
156 static struct clk pll2_aux_clk = {
157 .name = "pll2_aux_clk",
158 .parent = &pll2_clk,
159 .flags = CLK_PLL | PRE_PLL,
160 };
161
162 static struct clk clkout1_clk = {
163 .name = "clkout1",
164 .parent = &pll2_clk,
165 .flags = CLK_PLL | PRE_PLL,
166 };
167
168 static struct clk pll2_sysclk1 = {
169 .name = "pll2_sysclk1",
170 .parent = &pll2_clk,
171 .flags = CLK_PLL,
172 .div_reg = PLLDIV1,
173 };
174
175 static struct clk pll2_sysclk2 = {
176 .name = "pll2_sysclk2",
177 .parent = &pll2_clk,
178 .flags = CLK_PLL,
179 .div_reg = PLLDIV2,
180 };
181
182 static struct clk pll2_sysclk3 = {
183 .name = "pll2_sysclk3",
184 .parent = &pll2_clk,
185 .flags = CLK_PLL,
186 .div_reg = PLLDIV3,
187 };
188
189 static struct clk pll2_sysclk4 = {
190 .name = "pll2_sysclk4",
191 .parent = &pll2_clk,
192 .flags = CLK_PLL,
193 .div_reg = PLLDIV4,
194 };
195
196 static struct clk pll2_sysclk5 = {
197 .name = "pll2_sysclk5",
198 .parent = &pll2_clk,
199 .flags = CLK_PLL,
200 .div_reg = PLLDIV5,
201 };
202
203 static struct clk pll2_sysclk6 = {
204 .name = "pll2_sysclk6",
205 .parent = &pll2_clk,
206 .flags = CLK_PLL,
207 .div_reg = PLLDIV6,
208 };
209
210 static struct clk pll2_sysclk7 = {
211 .name = "pll2_sysclk7",
212 .parent = &pll2_clk,
213 .flags = CLK_PLL,
214 .div_reg = PLLDIV7,
215 };
216
217 static struct clk pll2_sysclk8 = {
218 .name = "pll2_sysclk8",
219 .parent = &pll2_clk,
220 .flags = CLK_PLL,
221 .div_reg = PLLDIV8,
222 };
223
224 static struct clk pll2_sysclk9 = {
225 .name = "pll2_sysclk9",
226 .parent = &pll2_clk,
227 .flags = CLK_PLL,
228 .div_reg = PLLDIV9,
229 };
230
231 static struct clk vpss_dac_clk = {
232 .name = "vpss_dac",
233 .parent = &pll1_sysclk3,
234 .lpsc = DM365_LPSC_DAC_CLK,
235 };
236
237 static struct clk vpss_master_clk = {
238 .name = "vpss_master",
239 .parent = &pll1_sysclk5,
240 .lpsc = DM365_LPSC_VPSSMSTR,
241 .flags = CLK_PSC,
242 };
243
244 static struct clk arm_clk = {
245 .name = "arm_clk",
246 .parent = &pll2_sysclk2,
247 .lpsc = DAVINCI_LPSC_ARM,
248 .flags = ALWAYS_ENABLED,
249 };
250
251 static struct clk uart0_clk = {
252 .name = "uart0",
253 .parent = &pll1_aux_clk,
254 .lpsc = DAVINCI_LPSC_UART0,
255 };
256
257 static struct clk uart1_clk = {
258 .name = "uart1",
259 .parent = &pll1_sysclk4,
260 .lpsc = DAVINCI_LPSC_UART1,
261 };
262
263 static struct clk i2c_clk = {
264 .name = "i2c",
265 .parent = &pll1_aux_clk,
266 .lpsc = DAVINCI_LPSC_I2C,
267 };
268
269 static struct clk mmcsd0_clk = {
270 .name = "mmcsd0",
271 .parent = &pll1_sysclk8,
272 .lpsc = DAVINCI_LPSC_MMC_SD,
273 };
274
275 static struct clk mmcsd1_clk = {
276 .name = "mmcsd1",
277 .parent = &pll1_sysclk4,
278 .lpsc = DM365_LPSC_MMC_SD1,
279 };
280
281 static struct clk spi0_clk = {
282 .name = "spi0",
283 .parent = &pll1_sysclk4,
284 .lpsc = DAVINCI_LPSC_SPI,
285 };
286
287 static struct clk spi1_clk = {
288 .name = "spi1",
289 .parent = &pll1_sysclk4,
290 .lpsc = DM365_LPSC_SPI1,
291 };
292
293 static struct clk spi2_clk = {
294 .name = "spi2",
295 .parent = &pll1_sysclk4,
296 .lpsc = DM365_LPSC_SPI2,
297 };
298
299 static struct clk spi3_clk = {
300 .name = "spi3",
301 .parent = &pll1_sysclk4,
302 .lpsc = DM365_LPSC_SPI3,
303 };
304
305 static struct clk spi4_clk = {
306 .name = "spi4",
307 .parent = &pll1_aux_clk,
308 .lpsc = DM365_LPSC_SPI4,
309 };
310
311 static struct clk gpio_clk = {
312 .name = "gpio",
313 .parent = &pll1_sysclk4,
314 .lpsc = DAVINCI_LPSC_GPIO,
315 };
316
317 static struct clk aemif_clk = {
318 .name = "aemif",
319 .parent = &pll1_sysclk4,
320 .lpsc = DAVINCI_LPSC_AEMIF,
321 };
322
323 static struct clk pwm0_clk = {
324 .name = "pwm0",
325 .parent = &pll1_aux_clk,
326 .lpsc = DAVINCI_LPSC_PWM0,
327 };
328
329 static struct clk pwm1_clk = {
330 .name = "pwm1",
331 .parent = &pll1_aux_clk,
332 .lpsc = DAVINCI_LPSC_PWM1,
333 };
334
335 static struct clk pwm2_clk = {
336 .name = "pwm2",
337 .parent = &pll1_aux_clk,
338 .lpsc = DAVINCI_LPSC_PWM2,
339 };
340
341 static struct clk pwm3_clk = {
342 .name = "pwm3",
343 .parent = &ref_clk,
344 .lpsc = DM365_LPSC_PWM3,
345 };
346
347 static struct clk timer0_clk = {
348 .name = "timer0",
349 .parent = &pll1_aux_clk,
350 .lpsc = DAVINCI_LPSC_TIMER0,
351 };
352
353 static struct clk timer1_clk = {
354 .name = "timer1",
355 .parent = &pll1_aux_clk,
356 .lpsc = DAVINCI_LPSC_TIMER1,
357 };
358
359 static struct clk timer2_clk = {
360 .name = "timer2",
361 .parent = &pll1_aux_clk,
362 .lpsc = DAVINCI_LPSC_TIMER2,
363 .usecount = 1,
364 };
365
366 static struct clk timer3_clk = {
367 .name = "timer3",
368 .parent = &pll1_aux_clk,
369 .lpsc = DM365_LPSC_TIMER3,
370 };
371
372 static struct clk usb_clk = {
373 .name = "usb",
374 .parent = &pll1_aux_clk,
375 .lpsc = DAVINCI_LPSC_USB,
376 };
377
378 static struct clk emac_clk = {
379 .name = "emac",
380 .parent = &pll1_sysclk4,
381 .lpsc = DM365_LPSC_EMAC,
382 };
383
384 static struct clk voicecodec_clk = {
385 .name = "voice_codec",
386 .parent = &pll2_sysclk4,
387 .lpsc = DM365_LPSC_VOICE_CODEC,
388 };
389
390 static struct clk asp0_clk = {
391 .name = "asp0",
392 .parent = &pll1_sysclk4,
393 .lpsc = DM365_LPSC_McBSP1,
394 };
395
396 static struct clk rto_clk = {
397 .name = "rto",
398 .parent = &pll1_sysclk4,
399 .lpsc = DM365_LPSC_RTO,
400 };
401
402 static struct clk mjcp_clk = {
403 .name = "mjcp",
404 .parent = &pll1_sysclk3,
405 .lpsc = DM365_LPSC_MJCP,
406 };
407
408 static struct clk_lookup dm365_clks[] = {
409 CLK(NULL, "ref", &ref_clk),
410 CLK(NULL, "pll1", &pll1_clk),
411 CLK(NULL, "pll1_aux", &pll1_aux_clk),
412 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
413 CLK(NULL, "clkout0", &clkout0_clk),
414 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
415 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
416 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
417 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
418 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
419 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
420 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
421 CLK(NULL, "pll1_sysclk8", &pll1_sysclk8),
422 CLK(NULL, "pll1_sysclk9", &pll1_sysclk9),
423 CLK(NULL, "pll2", &pll2_clk),
424 CLK(NULL, "pll2_aux", &pll2_aux_clk),
425 CLK(NULL, "clkout1", &clkout1_clk),
426 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
427 CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
428 CLK(NULL, "pll2_sysclk3", &pll2_sysclk3),
429 CLK(NULL, "pll2_sysclk4", &pll2_sysclk4),
430 CLK(NULL, "pll2_sysclk5", &pll2_sysclk5),
431 CLK(NULL, "pll2_sysclk6", &pll2_sysclk6),
432 CLK(NULL, "pll2_sysclk7", &pll2_sysclk7),
433 CLK(NULL, "pll2_sysclk8", &pll2_sysclk8),
434 CLK(NULL, "pll2_sysclk9", &pll2_sysclk9),
435 CLK(NULL, "vpss_dac", &vpss_dac_clk),
436 CLK(NULL, "vpss_master", &vpss_master_clk),
437 CLK(NULL, "arm", &arm_clk),
438 CLK(NULL, "uart0", &uart0_clk),
439 CLK(NULL, "uart1", &uart1_clk),
440 CLK("i2c_davinci.1", NULL, &i2c_clk),
441 CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
442 CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
443 CLK("spi_davinci.0", NULL, &spi0_clk),
444 CLK("spi_davinci.1", NULL, &spi1_clk),
445 CLK("spi_davinci.2", NULL, &spi2_clk),
446 CLK("spi_davinci.3", NULL, &spi3_clk),
447 CLK("spi_davinci.4", NULL, &spi4_clk),
448 CLK(NULL, "gpio", &gpio_clk),
449 CLK(NULL, "aemif", &aemif_clk),
450 CLK(NULL, "pwm0", &pwm0_clk),
451 CLK(NULL, "pwm1", &pwm1_clk),
452 CLK(NULL, "pwm2", &pwm2_clk),
453 CLK(NULL, "pwm3", &pwm3_clk),
454 CLK(NULL, "timer0", &timer0_clk),
455 CLK(NULL, "timer1", &timer1_clk),
456 CLK("watchdog", NULL, &timer2_clk),
457 CLK(NULL, "timer3", &timer3_clk),
458 CLK(NULL, "usb", &usb_clk),
459 CLK("davinci_emac.1", NULL, &emac_clk),
460 CLK("davinci_voicecodec", NULL, &voicecodec_clk),
461 CLK("davinci-mcbsp", NULL, &asp0_clk),
462 CLK(NULL, "rto", &rto_clk),
463 CLK(NULL, "mjcp", &mjcp_clk),
464 CLK(NULL, NULL, NULL),
465 };
466
467 /*----------------------------------------------------------------------*/
468
469 #define INTMUX 0x18
470 #define EVTMUX 0x1c
471
472
473 static const struct mux_config dm365_pins[] = {
474 #ifdef CONFIG_DAVINCI_MUX
475 MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false)
476
477 MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false)
478 MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false)
479 MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false)
480 MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false)
481 MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false)
482 MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false)
483
484 MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false)
485 MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false)
486
487 MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false)
488 MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false)
489 MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false)
490 MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false)
491 MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false)
492 MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false)
493 MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false)
494 MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false)
495
496 MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false)
497 MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false)
498 MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false)
499 MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false)
500 MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false)
501 MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false)
502
503 MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false)
504 MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false)
505 MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false)
506 MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false)
507 MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false)
508
509 MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false)
510 MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false)
511 MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false)
512 MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false)
513 MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false)
514 MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false)
515
516 MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false)
517 MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false)
518 MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false)
519 MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false)
520 MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false)
521 MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false)
522 MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false)
523 MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false)
524 MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false)
525 MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false)
526 MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false)
527 MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false)
528 MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false)
529 MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false)
530 MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false)
531 MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false)
532 MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false)
533
534 MUX_CFG(DM365, KEYSCAN, 2, 0, 0x3f, 0x3f, false)
535
536 MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false)
537 MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false)
538 MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false)
539 MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false)
540 MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false)
541 MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false)
542 MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false)
543 MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false)
544 MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false)
545 MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false)
546 MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false)
547 MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false)
548
549 MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false)
550 MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false)
551 MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false)
552 MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false)
553 MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false)
554
555 MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false)
556 MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false)
557 MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false)
558 MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false)
559 MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false)
560
561 MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false)
562 MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false)
563 MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false)
564 MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false)
565 MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false)
566
567 MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false)
568 MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false)
569 MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false)
570 MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false)
571 MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false)
572
573 MUX_CFG(DM365, CLKOUT0, 4, 20, 3, 3, false)
574 MUX_CFG(DM365, CLKOUT1, 4, 16, 3, 3, false)
575 MUX_CFG(DM365, CLKOUT2, 4, 8, 3, 3, false)
576
577 MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false)
578 MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false)
579 MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false)
580 MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false)
581 MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false)
582 MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false)
583 MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false)
584
585 MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false)
586 MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false)
587 MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false)
588 MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
589 MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
590 MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false)
591 MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false)
592 MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false)
593 MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false)
594 MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false)
595
596 INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false)
597 INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false)
598 INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false)
599 INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false)
600 INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false)
601 INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false)
602 INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false)
603 INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false)
604 INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false)
605 INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false)
606 INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false)
607 INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false)
608 INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false)
609 INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false)
610 INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false)
611 INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false)
612 INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false)
613 INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
614
615 EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false)
616 EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
617 EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false)
618 EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false)
619 #endif
620 };
621
622 static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
623
624 static struct davinci_spi_platform_data dm365_spi0_pdata = {
625 .version = SPI_VERSION_1,
626 .num_chipselect = 2,
627 .dma_event_q = EVENTQ_3,
628 };
629
630 static struct resource dm365_spi0_resources[] = {
631 {
632 .start = 0x01c66000,
633 .end = 0x01c667ff,
634 .flags = IORESOURCE_MEM,
635 },
636 {
637 .start = IRQ_DM365_SPIINT0_0,
638 .flags = IORESOURCE_IRQ,
639 },
640 {
641 .start = 17,
642 .flags = IORESOURCE_DMA,
643 },
644 {
645 .start = 16,
646 .flags = IORESOURCE_DMA,
647 },
648 };
649
650 static struct platform_device dm365_spi0_device = {
651 .name = "spi_davinci",
652 .id = 0,
653 .dev = {
654 .dma_mask = &dm365_spi0_dma_mask,
655 .coherent_dma_mask = DMA_BIT_MASK(32),
656 .platform_data = &dm365_spi0_pdata,
657 },
658 .num_resources = ARRAY_SIZE(dm365_spi0_resources),
659 .resource = dm365_spi0_resources,
660 };
661
dm365_init_spi0(unsigned chipselect_mask,struct spi_board_info * info,unsigned len)662 void __init dm365_init_spi0(unsigned chipselect_mask,
663 struct spi_board_info *info, unsigned len)
664 {
665 davinci_cfg_reg(DM365_SPI0_SCLK);
666 davinci_cfg_reg(DM365_SPI0_SDI);
667 davinci_cfg_reg(DM365_SPI0_SDO);
668
669 /* not all slaves will be wired up */
670 if (chipselect_mask & BIT(0))
671 davinci_cfg_reg(DM365_SPI0_SDENA0);
672 if (chipselect_mask & BIT(1))
673 davinci_cfg_reg(DM365_SPI0_SDENA1);
674
675 spi_register_board_info(info, len);
676
677 platform_device_register(&dm365_spi0_device);
678 }
679
680 static struct emac_platform_data dm365_emac_pdata = {
681 .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET,
682 .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET,
683 .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET,
684 .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE,
685 .version = EMAC_VERSION_2,
686 };
687
688 static struct resource dm365_emac_resources[] = {
689 {
690 .start = DM365_EMAC_BASE,
691 .end = DM365_EMAC_BASE + SZ_16K - 1,
692 .flags = IORESOURCE_MEM,
693 },
694 {
695 .start = IRQ_DM365_EMAC_RXTHRESH,
696 .end = IRQ_DM365_EMAC_RXTHRESH,
697 .flags = IORESOURCE_IRQ,
698 },
699 {
700 .start = IRQ_DM365_EMAC_RXPULSE,
701 .end = IRQ_DM365_EMAC_RXPULSE,
702 .flags = IORESOURCE_IRQ,
703 },
704 {
705 .start = IRQ_DM365_EMAC_TXPULSE,
706 .end = IRQ_DM365_EMAC_TXPULSE,
707 .flags = IORESOURCE_IRQ,
708 },
709 {
710 .start = IRQ_DM365_EMAC_MISCPULSE,
711 .end = IRQ_DM365_EMAC_MISCPULSE,
712 .flags = IORESOURCE_IRQ,
713 },
714 };
715
716 static struct platform_device dm365_emac_device = {
717 .name = "davinci_emac",
718 .id = 1,
719 .dev = {
720 .platform_data = &dm365_emac_pdata,
721 },
722 .num_resources = ARRAY_SIZE(dm365_emac_resources),
723 .resource = dm365_emac_resources,
724 };
725
726 static struct resource dm365_mdio_resources[] = {
727 {
728 .start = DM365_EMAC_MDIO_BASE,
729 .end = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
730 .flags = IORESOURCE_MEM,
731 },
732 };
733
734 static struct platform_device dm365_mdio_device = {
735 .name = "davinci_mdio",
736 .id = 0,
737 .num_resources = ARRAY_SIZE(dm365_mdio_resources),
738 .resource = dm365_mdio_resources,
739 };
740
741 static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
742 [IRQ_VDINT0] = 2,
743 [IRQ_VDINT1] = 6,
744 [IRQ_VDINT2] = 6,
745 [IRQ_HISTINT] = 6,
746 [IRQ_H3AINT] = 6,
747 [IRQ_PRVUINT] = 6,
748 [IRQ_RSZINT] = 6,
749 [IRQ_DM365_INSFINT] = 7,
750 [IRQ_VENCINT] = 6,
751 [IRQ_ASQINT] = 6,
752 [IRQ_IMXINT] = 6,
753 [IRQ_DM365_IMCOPINT] = 4,
754 [IRQ_USBINT] = 4,
755 [IRQ_DM365_RTOINT] = 7,
756 [IRQ_DM365_TINT5] = 7,
757 [IRQ_DM365_TINT6] = 5,
758 [IRQ_CCINT0] = 5,
759 [IRQ_CCERRINT] = 5,
760 [IRQ_TCERRINT0] = 5,
761 [IRQ_TCERRINT] = 7,
762 [IRQ_PSCIN] = 4,
763 [IRQ_DM365_SPINT2_1] = 7,
764 [IRQ_DM365_TINT7] = 7,
765 [IRQ_DM365_SDIOINT0] = 7,
766 [IRQ_MBXINT] = 7,
767 [IRQ_MBRINT] = 7,
768 [IRQ_MMCINT] = 7,
769 [IRQ_DM365_MMCINT1] = 7,
770 [IRQ_DM365_PWMINT3] = 7,
771 [IRQ_AEMIFINT] = 2,
772 [IRQ_DM365_SDIOINT1] = 2,
773 [IRQ_TINT0_TINT12] = 7,
774 [IRQ_TINT0_TINT34] = 7,
775 [IRQ_TINT1_TINT12] = 7,
776 [IRQ_TINT1_TINT34] = 7,
777 [IRQ_PWMINT0] = 7,
778 [IRQ_PWMINT1] = 3,
779 [IRQ_PWMINT2] = 3,
780 [IRQ_I2C] = 3,
781 [IRQ_UARTINT0] = 3,
782 [IRQ_UARTINT1] = 3,
783 [IRQ_DM365_RTCINT] = 3,
784 [IRQ_DM365_SPIINT0_0] = 3,
785 [IRQ_DM365_SPIINT3_0] = 3,
786 [IRQ_DM365_GPIO0] = 3,
787 [IRQ_DM365_GPIO1] = 7,
788 [IRQ_DM365_GPIO2] = 4,
789 [IRQ_DM365_GPIO3] = 4,
790 [IRQ_DM365_GPIO4] = 7,
791 [IRQ_DM365_GPIO5] = 7,
792 [IRQ_DM365_GPIO6] = 7,
793 [IRQ_DM365_GPIO7] = 7,
794 [IRQ_DM365_EMAC_RXTHRESH] = 7,
795 [IRQ_DM365_EMAC_RXPULSE] = 7,
796 [IRQ_DM365_EMAC_TXPULSE] = 7,
797 [IRQ_DM365_EMAC_MISCPULSE] = 7,
798 [IRQ_DM365_GPIO12] = 7,
799 [IRQ_DM365_GPIO13] = 7,
800 [IRQ_DM365_GPIO14] = 7,
801 [IRQ_DM365_GPIO15] = 7,
802 [IRQ_DM365_KEYINT] = 7,
803 [IRQ_DM365_TCERRINT2] = 7,
804 [IRQ_DM365_TCERRINT3] = 7,
805 [IRQ_DM365_EMUINT] = 7,
806 };
807
808 /* Four Transfer Controllers on DM365 */
809 static const s8
810 dm365_queue_tc_mapping[][2] = {
811 /* {event queue no, TC no} */
812 {0, 0},
813 {1, 1},
814 {2, 2},
815 {3, 3},
816 {-1, -1},
817 };
818
819 static const s8
820 dm365_queue_priority_mapping[][2] = {
821 /* {event queue no, Priority} */
822 {0, 7},
823 {1, 7},
824 {2, 7},
825 {3, 0},
826 {-1, -1},
827 };
828
829 static struct edma_soc_info edma_cc0_info = {
830 .n_channel = 64,
831 .n_region = 4,
832 .n_slot = 256,
833 .n_tc = 4,
834 .n_cc = 1,
835 .queue_tc_mapping = dm365_queue_tc_mapping,
836 .queue_priority_mapping = dm365_queue_priority_mapping,
837 .default_queue = EVENTQ_3,
838 };
839
840 static struct edma_soc_info *dm365_edma_info[EDMA_MAX_CC] = {
841 &edma_cc0_info,
842 };
843
844 static struct resource edma_resources[] = {
845 {
846 .name = "edma_cc0",
847 .start = 0x01c00000,
848 .end = 0x01c00000 + SZ_64K - 1,
849 .flags = IORESOURCE_MEM,
850 },
851 {
852 .name = "edma_tc0",
853 .start = 0x01c10000,
854 .end = 0x01c10000 + SZ_1K - 1,
855 .flags = IORESOURCE_MEM,
856 },
857 {
858 .name = "edma_tc1",
859 .start = 0x01c10400,
860 .end = 0x01c10400 + SZ_1K - 1,
861 .flags = IORESOURCE_MEM,
862 },
863 {
864 .name = "edma_tc2",
865 .start = 0x01c10800,
866 .end = 0x01c10800 + SZ_1K - 1,
867 .flags = IORESOURCE_MEM,
868 },
869 {
870 .name = "edma_tc3",
871 .start = 0x01c10c00,
872 .end = 0x01c10c00 + SZ_1K - 1,
873 .flags = IORESOURCE_MEM,
874 },
875 {
876 .name = "edma0",
877 .start = IRQ_CCINT0,
878 .flags = IORESOURCE_IRQ,
879 },
880 {
881 .name = "edma0_err",
882 .start = IRQ_CCERRINT,
883 .flags = IORESOURCE_IRQ,
884 },
885 /* not using TC*_ERR */
886 };
887
888 static struct platform_device dm365_edma_device = {
889 .name = "edma",
890 .id = 0,
891 .dev.platform_data = dm365_edma_info,
892 .num_resources = ARRAY_SIZE(edma_resources),
893 .resource = edma_resources,
894 };
895
896 static struct resource dm365_asp_resources[] = {
897 {
898 .start = DAVINCI_DM365_ASP0_BASE,
899 .end = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
900 .flags = IORESOURCE_MEM,
901 },
902 {
903 .start = DAVINCI_DMA_ASP0_TX,
904 .end = DAVINCI_DMA_ASP0_TX,
905 .flags = IORESOURCE_DMA,
906 },
907 {
908 .start = DAVINCI_DMA_ASP0_RX,
909 .end = DAVINCI_DMA_ASP0_RX,
910 .flags = IORESOURCE_DMA,
911 },
912 };
913
914 static struct platform_device dm365_asp_device = {
915 .name = "davinci-mcbsp",
916 .id = -1,
917 .num_resources = ARRAY_SIZE(dm365_asp_resources),
918 .resource = dm365_asp_resources,
919 };
920
921 static struct resource dm365_vc_resources[] = {
922 {
923 .start = DAVINCI_DM365_VC_BASE,
924 .end = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
925 .flags = IORESOURCE_MEM,
926 },
927 {
928 .start = DAVINCI_DMA_VC_TX,
929 .end = DAVINCI_DMA_VC_TX,
930 .flags = IORESOURCE_DMA,
931 },
932 {
933 .start = DAVINCI_DMA_VC_RX,
934 .end = DAVINCI_DMA_VC_RX,
935 .flags = IORESOURCE_DMA,
936 },
937 };
938
939 static struct platform_device dm365_vc_device = {
940 .name = "davinci_voicecodec",
941 .id = -1,
942 .num_resources = ARRAY_SIZE(dm365_vc_resources),
943 .resource = dm365_vc_resources,
944 };
945
946 static struct resource dm365_rtc_resources[] = {
947 {
948 .start = DM365_RTC_BASE,
949 .end = DM365_RTC_BASE + SZ_1K - 1,
950 .flags = IORESOURCE_MEM,
951 },
952 {
953 .start = IRQ_DM365_RTCINT,
954 .flags = IORESOURCE_IRQ,
955 },
956 };
957
958 static struct platform_device dm365_rtc_device = {
959 .name = "rtc_davinci",
960 .id = 0,
961 .num_resources = ARRAY_SIZE(dm365_rtc_resources),
962 .resource = dm365_rtc_resources,
963 };
964
965 static struct map_desc dm365_io_desc[] = {
966 {
967 .virtual = IO_VIRT,
968 .pfn = __phys_to_pfn(IO_PHYS),
969 .length = IO_SIZE,
970 .type = MT_DEVICE
971 },
972 {
973 .virtual = SRAM_VIRT,
974 .pfn = __phys_to_pfn(0x00010000),
975 .length = SZ_32K,
976 .type = MT_MEMORY_NONCACHED,
977 },
978 };
979
980 static struct resource dm365_ks_resources[] = {
981 {
982 /* registers */
983 .start = DM365_KEYSCAN_BASE,
984 .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
985 .flags = IORESOURCE_MEM,
986 },
987 {
988 /* interrupt */
989 .start = IRQ_DM365_KEYINT,
990 .end = IRQ_DM365_KEYINT,
991 .flags = IORESOURCE_IRQ,
992 },
993 };
994
995 static struct platform_device dm365_ks_device = {
996 .name = "davinci_keyscan",
997 .id = 0,
998 .num_resources = ARRAY_SIZE(dm365_ks_resources),
999 .resource = dm365_ks_resources,
1000 };
1001
1002 /* Contents of JTAG ID register used to identify exact cpu type */
1003 static struct davinci_id dm365_ids[] = {
1004 {
1005 .variant = 0x0,
1006 .part_no = 0xb83e,
1007 .manufacturer = 0x017,
1008 .cpu_id = DAVINCI_CPU_ID_DM365,
1009 .name = "dm365_rev1.1",
1010 },
1011 {
1012 .variant = 0x8,
1013 .part_no = 0xb83e,
1014 .manufacturer = 0x017,
1015 .cpu_id = DAVINCI_CPU_ID_DM365,
1016 .name = "dm365_rev1.2",
1017 },
1018 };
1019
1020 static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
1021
1022 static struct davinci_timer_info dm365_timer_info = {
1023 .timers = davinci_timer_instance,
1024 .clockevent_id = T0_BOT,
1025 .clocksource_id = T0_TOP,
1026 };
1027
1028 #define DM365_UART1_BASE (IO_PHYS + 0x106000)
1029
1030 static struct plat_serial8250_port dm365_serial_platform_data[] = {
1031 {
1032 .mapbase = DAVINCI_UART0_BASE,
1033 .irq = IRQ_UARTINT0,
1034 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1035 UPF_IOREMAP,
1036 .iotype = UPIO_MEM,
1037 .regshift = 2,
1038 },
1039 {
1040 .mapbase = DM365_UART1_BASE,
1041 .irq = IRQ_UARTINT1,
1042 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1043 UPF_IOREMAP,
1044 .iotype = UPIO_MEM,
1045 .regshift = 2,
1046 },
1047 {
1048 .flags = 0
1049 },
1050 };
1051
1052 static struct platform_device dm365_serial_device = {
1053 .name = "serial8250",
1054 .id = PLAT8250_DEV_PLATFORM,
1055 .dev = {
1056 .platform_data = dm365_serial_platform_data,
1057 },
1058 };
1059
1060 static struct davinci_soc_info davinci_soc_info_dm365 = {
1061 .io_desc = dm365_io_desc,
1062 .io_desc_num = ARRAY_SIZE(dm365_io_desc),
1063 .jtag_id_reg = 0x01c40028,
1064 .ids = dm365_ids,
1065 .ids_num = ARRAY_SIZE(dm365_ids),
1066 .cpu_clks = dm365_clks,
1067 .psc_bases = dm365_psc_bases,
1068 .psc_bases_num = ARRAY_SIZE(dm365_psc_bases),
1069 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
1070 .pinmux_pins = dm365_pins,
1071 .pinmux_pins_num = ARRAY_SIZE(dm365_pins),
1072 .intc_base = DAVINCI_ARM_INTC_BASE,
1073 .intc_type = DAVINCI_INTC_TYPE_AINTC,
1074 .intc_irq_prios = dm365_default_priorities,
1075 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
1076 .timer_info = &dm365_timer_info,
1077 .gpio_type = GPIO_TYPE_DAVINCI,
1078 .gpio_base = DAVINCI_GPIO_BASE,
1079 .gpio_num = 104,
1080 .gpio_irq = IRQ_DM365_GPIO0,
1081 .gpio_unbanked = 8, /* really 16 ... skip muxed GPIOs */
1082 .serial_dev = &dm365_serial_device,
1083 .emac_pdata = &dm365_emac_pdata,
1084 .sram_dma = 0x00010000,
1085 .sram_len = SZ_32K,
1086 };
1087
dm365_init_asp(struct snd_platform_data * pdata)1088 void __init dm365_init_asp(struct snd_platform_data *pdata)
1089 {
1090 davinci_cfg_reg(DM365_MCBSP0_BDX);
1091 davinci_cfg_reg(DM365_MCBSP0_X);
1092 davinci_cfg_reg(DM365_MCBSP0_BFSX);
1093 davinci_cfg_reg(DM365_MCBSP0_BDR);
1094 davinci_cfg_reg(DM365_MCBSP0_R);
1095 davinci_cfg_reg(DM365_MCBSP0_BFSR);
1096 davinci_cfg_reg(DM365_EVT2_ASP_TX);
1097 davinci_cfg_reg(DM365_EVT3_ASP_RX);
1098 dm365_asp_device.dev.platform_data = pdata;
1099 platform_device_register(&dm365_asp_device);
1100 }
1101
dm365_init_vc(struct snd_platform_data * pdata)1102 void __init dm365_init_vc(struct snd_platform_data *pdata)
1103 {
1104 davinci_cfg_reg(DM365_EVT2_VC_TX);
1105 davinci_cfg_reg(DM365_EVT3_VC_RX);
1106 dm365_vc_device.dev.platform_data = pdata;
1107 platform_device_register(&dm365_vc_device);
1108 }
1109
dm365_init_ks(struct davinci_ks_platform_data * pdata)1110 void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
1111 {
1112 dm365_ks_device.dev.platform_data = pdata;
1113 platform_device_register(&dm365_ks_device);
1114 }
1115
dm365_init_rtc(void)1116 void __init dm365_init_rtc(void)
1117 {
1118 davinci_cfg_reg(DM365_INT_PRTCSS);
1119 platform_device_register(&dm365_rtc_device);
1120 }
1121
dm365_init(void)1122 void __init dm365_init(void)
1123 {
1124 davinci_common_init(&davinci_soc_info_dm365);
1125 }
1126
1127 static struct resource dm365_vpss_resources[] = {
1128 {
1129 /* VPSS ISP5 Base address */
1130 .name = "isp5",
1131 .start = 0x01c70000,
1132 .end = 0x01c70000 + 0xff,
1133 .flags = IORESOURCE_MEM,
1134 },
1135 {
1136 /* VPSS CLK Base address */
1137 .name = "vpss",
1138 .start = 0x01c70200,
1139 .end = 0x01c70200 + 0xff,
1140 .flags = IORESOURCE_MEM,
1141 },
1142 };
1143
1144 static struct platform_device dm365_vpss_device = {
1145 .name = "vpss",
1146 .id = -1,
1147 .dev.platform_data = "dm365_vpss",
1148 .num_resources = ARRAY_SIZE(dm365_vpss_resources),
1149 .resource = dm365_vpss_resources,
1150 };
1151
1152 static struct resource vpfe_resources[] = {
1153 {
1154 .start = IRQ_VDINT0,
1155 .end = IRQ_VDINT0,
1156 .flags = IORESOURCE_IRQ,
1157 },
1158 {
1159 .start = IRQ_VDINT1,
1160 .end = IRQ_VDINT1,
1161 .flags = IORESOURCE_IRQ,
1162 },
1163 };
1164
1165 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
1166 static struct platform_device vpfe_capture_dev = {
1167 .name = CAPTURE_DRV_NAME,
1168 .id = -1,
1169 .num_resources = ARRAY_SIZE(vpfe_resources),
1170 .resource = vpfe_resources,
1171 .dev = {
1172 .dma_mask = &vpfe_capture_dma_mask,
1173 .coherent_dma_mask = DMA_BIT_MASK(32),
1174 },
1175 };
1176
dm365_isif_setup_pinmux(void)1177 static void dm365_isif_setup_pinmux(void)
1178 {
1179 davinci_cfg_reg(DM365_VIN_CAM_WEN);
1180 davinci_cfg_reg(DM365_VIN_CAM_VD);
1181 davinci_cfg_reg(DM365_VIN_CAM_HD);
1182 davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
1183 davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
1184 }
1185
1186 static struct resource isif_resource[] = {
1187 /* ISIF Base address */
1188 {
1189 .start = 0x01c71000,
1190 .end = 0x01c71000 + 0x1ff,
1191 .flags = IORESOURCE_MEM,
1192 },
1193 /* ISIF Linearization table 0 */
1194 {
1195 .start = 0x1C7C000,
1196 .end = 0x1C7C000 + 0x2ff,
1197 .flags = IORESOURCE_MEM,
1198 },
1199 /* ISIF Linearization table 1 */
1200 {
1201 .start = 0x1C7C400,
1202 .end = 0x1C7C400 + 0x2ff,
1203 .flags = IORESOURCE_MEM,
1204 },
1205 };
1206 static struct platform_device dm365_isif_dev = {
1207 .name = "isif",
1208 .id = -1,
1209 .num_resources = ARRAY_SIZE(isif_resource),
1210 .resource = isif_resource,
1211 .dev = {
1212 .dma_mask = &vpfe_capture_dma_mask,
1213 .coherent_dma_mask = DMA_BIT_MASK(32),
1214 .platform_data = dm365_isif_setup_pinmux,
1215 },
1216 };
1217
dm365_init_devices(void)1218 static int __init dm365_init_devices(void)
1219 {
1220 if (!cpu_is_davinci_dm365())
1221 return 0;
1222
1223 davinci_cfg_reg(DM365_INT_EDMA_CC);
1224 platform_device_register(&dm365_edma_device);
1225
1226 platform_device_register(&dm365_mdio_device);
1227 platform_device_register(&dm365_emac_device);
1228 clk_add_alias(NULL, dev_name(&dm365_mdio_device.dev),
1229 NULL, &dm365_emac_device.dev);
1230
1231 /* Add isif clock alias */
1232 clk_add_alias("master", dm365_isif_dev.name, "vpss_master", NULL);
1233 platform_device_register(&dm365_vpss_device);
1234 platform_device_register(&dm365_isif_dev);
1235 platform_device_register(&vpfe_capture_dev);
1236 return 0;
1237 }
1238 postcore_initcall(dm365_init_devices);
1239
dm365_set_vpfe_config(struct vpfe_config * cfg)1240 void dm365_set_vpfe_config(struct vpfe_config *cfg)
1241 {
1242 vpfe_capture_dev.dev.platform_data = cfg;
1243 }
1244