1 /*
2 * TI DaVinci DM355 chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11 #include <linux/init.h>
12 #include <linux/clk.h>
13 #include <linux/serial_8250.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16
17 #include <linux/spi/spi.h>
18
19 #include <asm/mach/map.h>
20
21 #include <mach/dm355.h>
22 #include <mach/cputype.h>
23 #include <mach/edma.h>
24 #include <mach/psc.h>
25 #include <mach/mux.h>
26 #include <mach/irqs.h>
27 #include <mach/time.h>
28 #include <mach/serial.h>
29 #include <mach/common.h>
30 #include <mach/asp.h>
31 #include <mach/spi.h>
32 #include <mach/gpio-davinci.h>
33
34 #include "clock.h"
35 #include "mux.h"
36
37 #define DM355_UART2_BASE (IO_PHYS + 0x206000)
38
39 /*
40 * Device specific clocks
41 */
42 #define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
43
44 static struct pll_data pll1_data = {
45 .num = 1,
46 .phys_base = DAVINCI_PLL1_BASE,
47 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
48 };
49
50 static struct pll_data pll2_data = {
51 .num = 2,
52 .phys_base = DAVINCI_PLL2_BASE,
53 .flags = PLL_HAS_PREDIV,
54 };
55
56 static struct clk ref_clk = {
57 .name = "ref_clk",
58 /* FIXME -- crystal rate is board-specific */
59 .rate = DM355_REF_FREQ,
60 };
61
62 static struct clk pll1_clk = {
63 .name = "pll1",
64 .parent = &ref_clk,
65 .flags = CLK_PLL,
66 .pll_data = &pll1_data,
67 };
68
69 static struct clk pll1_aux_clk = {
70 .name = "pll1_aux_clk",
71 .parent = &pll1_clk,
72 .flags = CLK_PLL | PRE_PLL,
73 };
74
75 static struct clk pll1_sysclk1 = {
76 .name = "pll1_sysclk1",
77 .parent = &pll1_clk,
78 .flags = CLK_PLL,
79 .div_reg = PLLDIV1,
80 };
81
82 static struct clk pll1_sysclk2 = {
83 .name = "pll1_sysclk2",
84 .parent = &pll1_clk,
85 .flags = CLK_PLL,
86 .div_reg = PLLDIV2,
87 };
88
89 static struct clk pll1_sysclk3 = {
90 .name = "pll1_sysclk3",
91 .parent = &pll1_clk,
92 .flags = CLK_PLL,
93 .div_reg = PLLDIV3,
94 };
95
96 static struct clk pll1_sysclk4 = {
97 .name = "pll1_sysclk4",
98 .parent = &pll1_clk,
99 .flags = CLK_PLL,
100 .div_reg = PLLDIV4,
101 };
102
103 static struct clk pll1_sysclkbp = {
104 .name = "pll1_sysclkbp",
105 .parent = &pll1_clk,
106 .flags = CLK_PLL | PRE_PLL,
107 .div_reg = BPDIV
108 };
109
110 static struct clk vpss_dac_clk = {
111 .name = "vpss_dac",
112 .parent = &pll1_sysclk3,
113 .lpsc = DM355_LPSC_VPSS_DAC,
114 };
115
116 static struct clk vpss_master_clk = {
117 .name = "vpss_master",
118 .parent = &pll1_sysclk4,
119 .lpsc = DAVINCI_LPSC_VPSSMSTR,
120 .flags = CLK_PSC,
121 };
122
123 static struct clk vpss_slave_clk = {
124 .name = "vpss_slave",
125 .parent = &pll1_sysclk4,
126 .lpsc = DAVINCI_LPSC_VPSSSLV,
127 };
128
129 static struct clk clkout1_clk = {
130 .name = "clkout1",
131 .parent = &pll1_aux_clk,
132 /* NOTE: clkout1 can be externally gated by muxing GPIO-18 */
133 };
134
135 static struct clk clkout2_clk = {
136 .name = "clkout2",
137 .parent = &pll1_sysclkbp,
138 };
139
140 static struct clk pll2_clk = {
141 .name = "pll2",
142 .parent = &ref_clk,
143 .flags = CLK_PLL,
144 .pll_data = &pll2_data,
145 };
146
147 static struct clk pll2_sysclk1 = {
148 .name = "pll2_sysclk1",
149 .parent = &pll2_clk,
150 .flags = CLK_PLL,
151 .div_reg = PLLDIV1,
152 };
153
154 static struct clk pll2_sysclkbp = {
155 .name = "pll2_sysclkbp",
156 .parent = &pll2_clk,
157 .flags = CLK_PLL | PRE_PLL,
158 .div_reg = BPDIV
159 };
160
161 static struct clk clkout3_clk = {
162 .name = "clkout3",
163 .parent = &pll2_sysclkbp,
164 /* NOTE: clkout3 can be externally gated by muxing GPIO-16 */
165 };
166
167 static struct clk arm_clk = {
168 .name = "arm_clk",
169 .parent = &pll1_sysclk1,
170 .lpsc = DAVINCI_LPSC_ARM,
171 .flags = ALWAYS_ENABLED,
172 };
173
174 /*
175 * NOT LISTED below, and not touched by Linux
176 * - in SyncReset state by default
177 * .lpsc = DAVINCI_LPSC_TPCC,
178 * .lpsc = DAVINCI_LPSC_TPTC0,
179 * .lpsc = DAVINCI_LPSC_TPTC1,
180 * .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
181 * .lpsc = DAVINCI_LPSC_MEMSTICK,
182 * - in Enabled state by default
183 * .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
184 * .lpsc = DAVINCI_LPSC_SCR2, // "bus"
185 * .lpsc = DAVINCI_LPSC_SCR3, // "bus"
186 * .lpsc = DAVINCI_LPSC_SCR4, // "bus"
187 * .lpsc = DAVINCI_LPSC_CROSSBAR, // "emulation"
188 * .lpsc = DAVINCI_LPSC_CFG27, // "test"
189 * .lpsc = DAVINCI_LPSC_CFG3, // "test"
190 * .lpsc = DAVINCI_LPSC_CFG5, // "test"
191 */
192
193 static struct clk mjcp_clk = {
194 .name = "mjcp",
195 .parent = &pll1_sysclk1,
196 .lpsc = DAVINCI_LPSC_IMCOP,
197 };
198
199 static struct clk uart0_clk = {
200 .name = "uart0",
201 .parent = &pll1_aux_clk,
202 .lpsc = DAVINCI_LPSC_UART0,
203 };
204
205 static struct clk uart1_clk = {
206 .name = "uart1",
207 .parent = &pll1_aux_clk,
208 .lpsc = DAVINCI_LPSC_UART1,
209 };
210
211 static struct clk uart2_clk = {
212 .name = "uart2",
213 .parent = &pll1_sysclk2,
214 .lpsc = DAVINCI_LPSC_UART2,
215 };
216
217 static struct clk i2c_clk = {
218 .name = "i2c",
219 .parent = &pll1_aux_clk,
220 .lpsc = DAVINCI_LPSC_I2C,
221 };
222
223 static struct clk asp0_clk = {
224 .name = "asp0",
225 .parent = &pll1_sysclk2,
226 .lpsc = DAVINCI_LPSC_McBSP,
227 };
228
229 static struct clk asp1_clk = {
230 .name = "asp1",
231 .parent = &pll1_sysclk2,
232 .lpsc = DM355_LPSC_McBSP1,
233 };
234
235 static struct clk mmcsd0_clk = {
236 .name = "mmcsd0",
237 .parent = &pll1_sysclk2,
238 .lpsc = DAVINCI_LPSC_MMC_SD,
239 };
240
241 static struct clk mmcsd1_clk = {
242 .name = "mmcsd1",
243 .parent = &pll1_sysclk2,
244 .lpsc = DM355_LPSC_MMC_SD1,
245 };
246
247 static struct clk spi0_clk = {
248 .name = "spi0",
249 .parent = &pll1_sysclk2,
250 .lpsc = DAVINCI_LPSC_SPI,
251 };
252
253 static struct clk spi1_clk = {
254 .name = "spi1",
255 .parent = &pll1_sysclk2,
256 .lpsc = DM355_LPSC_SPI1,
257 };
258
259 static struct clk spi2_clk = {
260 .name = "spi2",
261 .parent = &pll1_sysclk2,
262 .lpsc = DM355_LPSC_SPI2,
263 };
264
265 static struct clk gpio_clk = {
266 .name = "gpio",
267 .parent = &pll1_sysclk2,
268 .lpsc = DAVINCI_LPSC_GPIO,
269 };
270
271 static struct clk aemif_clk = {
272 .name = "aemif",
273 .parent = &pll1_sysclk2,
274 .lpsc = DAVINCI_LPSC_AEMIF,
275 };
276
277 static struct clk pwm0_clk = {
278 .name = "pwm0",
279 .parent = &pll1_aux_clk,
280 .lpsc = DAVINCI_LPSC_PWM0,
281 };
282
283 static struct clk pwm1_clk = {
284 .name = "pwm1",
285 .parent = &pll1_aux_clk,
286 .lpsc = DAVINCI_LPSC_PWM1,
287 };
288
289 static struct clk pwm2_clk = {
290 .name = "pwm2",
291 .parent = &pll1_aux_clk,
292 .lpsc = DAVINCI_LPSC_PWM2,
293 };
294
295 static struct clk pwm3_clk = {
296 .name = "pwm3",
297 .parent = &pll1_aux_clk,
298 .lpsc = DM355_LPSC_PWM3,
299 };
300
301 static struct clk timer0_clk = {
302 .name = "timer0",
303 .parent = &pll1_aux_clk,
304 .lpsc = DAVINCI_LPSC_TIMER0,
305 };
306
307 static struct clk timer1_clk = {
308 .name = "timer1",
309 .parent = &pll1_aux_clk,
310 .lpsc = DAVINCI_LPSC_TIMER1,
311 };
312
313 static struct clk timer2_clk = {
314 .name = "timer2",
315 .parent = &pll1_aux_clk,
316 .lpsc = DAVINCI_LPSC_TIMER2,
317 .usecount = 1, /* REVISIT: why can't this be disabled? */
318 };
319
320 static struct clk timer3_clk = {
321 .name = "timer3",
322 .parent = &pll1_aux_clk,
323 .lpsc = DM355_LPSC_TIMER3,
324 };
325
326 static struct clk rto_clk = {
327 .name = "rto",
328 .parent = &pll1_aux_clk,
329 .lpsc = DM355_LPSC_RTO,
330 };
331
332 static struct clk usb_clk = {
333 .name = "usb",
334 .parent = &pll1_sysclk2,
335 .lpsc = DAVINCI_LPSC_USB,
336 };
337
338 static struct clk_lookup dm355_clks[] = {
339 CLK(NULL, "ref", &ref_clk),
340 CLK(NULL, "pll1", &pll1_clk),
341 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
342 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
343 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
344 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
345 CLK(NULL, "pll1_aux", &pll1_aux_clk),
346 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
347 CLK(NULL, "vpss_dac", &vpss_dac_clk),
348 CLK(NULL, "vpss_master", &vpss_master_clk),
349 CLK(NULL, "vpss_slave", &vpss_slave_clk),
350 CLK(NULL, "clkout1", &clkout1_clk),
351 CLK(NULL, "clkout2", &clkout2_clk),
352 CLK(NULL, "pll2", &pll2_clk),
353 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
354 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
355 CLK(NULL, "clkout3", &clkout3_clk),
356 CLK(NULL, "arm", &arm_clk),
357 CLK(NULL, "mjcp", &mjcp_clk),
358 CLK(NULL, "uart0", &uart0_clk),
359 CLK(NULL, "uart1", &uart1_clk),
360 CLK(NULL, "uart2", &uart2_clk),
361 CLK("i2c_davinci.1", NULL, &i2c_clk),
362 CLK("davinci-mcbsp.0", NULL, &asp0_clk),
363 CLK("davinci-mcbsp.1", NULL, &asp1_clk),
364 CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
365 CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
366 CLK("spi_davinci.0", NULL, &spi0_clk),
367 CLK("spi_davinci.1", NULL, &spi1_clk),
368 CLK("spi_davinci.2", NULL, &spi2_clk),
369 CLK(NULL, "gpio", &gpio_clk),
370 CLK(NULL, "aemif", &aemif_clk),
371 CLK(NULL, "pwm0", &pwm0_clk),
372 CLK(NULL, "pwm1", &pwm1_clk),
373 CLK(NULL, "pwm2", &pwm2_clk),
374 CLK(NULL, "pwm3", &pwm3_clk),
375 CLK(NULL, "timer0", &timer0_clk),
376 CLK(NULL, "timer1", &timer1_clk),
377 CLK("watchdog", NULL, &timer2_clk),
378 CLK(NULL, "timer3", &timer3_clk),
379 CLK(NULL, "rto", &rto_clk),
380 CLK(NULL, "usb", &usb_clk),
381 CLK(NULL, NULL, NULL),
382 };
383
384 /*----------------------------------------------------------------------*/
385
386 static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
387
388 static struct resource dm355_spi0_resources[] = {
389 {
390 .start = 0x01c66000,
391 .end = 0x01c667ff,
392 .flags = IORESOURCE_MEM,
393 },
394 {
395 .start = IRQ_DM355_SPINT0_0,
396 .flags = IORESOURCE_IRQ,
397 },
398 {
399 .start = 17,
400 .flags = IORESOURCE_DMA,
401 },
402 {
403 .start = 16,
404 .flags = IORESOURCE_DMA,
405 },
406 };
407
408 static struct davinci_spi_platform_data dm355_spi0_pdata = {
409 .version = SPI_VERSION_1,
410 .num_chipselect = 2,
411 .cshold_bug = true,
412 .dma_event_q = EVENTQ_1,
413 };
414 static struct platform_device dm355_spi0_device = {
415 .name = "spi_davinci",
416 .id = 0,
417 .dev = {
418 .dma_mask = &dm355_spi0_dma_mask,
419 .coherent_dma_mask = DMA_BIT_MASK(32),
420 .platform_data = &dm355_spi0_pdata,
421 },
422 .num_resources = ARRAY_SIZE(dm355_spi0_resources),
423 .resource = dm355_spi0_resources,
424 };
425
dm355_init_spi0(unsigned chipselect_mask,struct spi_board_info * info,unsigned len)426 void __init dm355_init_spi0(unsigned chipselect_mask,
427 struct spi_board_info *info, unsigned len)
428 {
429 /* for now, assume we need MISO */
430 davinci_cfg_reg(DM355_SPI0_SDI);
431
432 /* not all slaves will be wired up */
433 if (chipselect_mask & BIT(0))
434 davinci_cfg_reg(DM355_SPI0_SDENA0);
435 if (chipselect_mask & BIT(1))
436 davinci_cfg_reg(DM355_SPI0_SDENA1);
437
438 spi_register_board_info(info, len);
439
440 platform_device_register(&dm355_spi0_device);
441 }
442
443 /*----------------------------------------------------------------------*/
444
445 #define INTMUX 0x18
446 #define EVTMUX 0x1c
447
448 /*
449 * Device specific mux setup
450 *
451 * soc description mux mode mode mux dbg
452 * reg offset mask mode
453 */
454 static const struct mux_config dm355_pins[] = {
455 #ifdef CONFIG_DAVINCI_MUX
456 MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
457
458 MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
459 MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false)
460 MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false)
461 MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false)
462 MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false)
463 MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false)
464
465 MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false)
466 MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false)
467
468 MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
469 MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false)
470 MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false)
471 MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false)
472 MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false)
473 MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false)
474
475 MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
476 MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
477 MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false)
478
479 INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false)
480 INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false)
481 INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
482
483 EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
484 EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
485 EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
486
487 MUX_CFG(DM355, VOUT_FIELD, 1, 18, 3, 1, false)
488 MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false)
489 MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false)
490 MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
491 MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
492
493 MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false)
494 MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false)
495 MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false)
496 MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false)
497 MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false)
498 MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false)
499 MUX_CFG(DM355, VIN_CINH_EN, 0, 8, 3, 3, false)
500 #endif
501 };
502
503 static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
504 [IRQ_DM355_CCDC_VDINT0] = 2,
505 [IRQ_DM355_CCDC_VDINT1] = 6,
506 [IRQ_DM355_CCDC_VDINT2] = 6,
507 [IRQ_DM355_IPIPE_HST] = 6,
508 [IRQ_DM355_H3AINT] = 6,
509 [IRQ_DM355_IPIPE_SDR] = 6,
510 [IRQ_DM355_IPIPEIFINT] = 6,
511 [IRQ_DM355_OSDINT] = 7,
512 [IRQ_DM355_VENCINT] = 6,
513 [IRQ_ASQINT] = 6,
514 [IRQ_IMXINT] = 6,
515 [IRQ_USBINT] = 4,
516 [IRQ_DM355_RTOINT] = 4,
517 [IRQ_DM355_UARTINT2] = 7,
518 [IRQ_DM355_TINT6] = 7,
519 [IRQ_CCINT0] = 5, /* dma */
520 [IRQ_CCERRINT] = 5, /* dma */
521 [IRQ_TCERRINT0] = 5, /* dma */
522 [IRQ_TCERRINT] = 5, /* dma */
523 [IRQ_DM355_SPINT2_1] = 7,
524 [IRQ_DM355_TINT7] = 4,
525 [IRQ_DM355_SDIOINT0] = 7,
526 [IRQ_MBXINT] = 7,
527 [IRQ_MBRINT] = 7,
528 [IRQ_MMCINT] = 7,
529 [IRQ_DM355_MMCINT1] = 7,
530 [IRQ_DM355_PWMINT3] = 7,
531 [IRQ_DDRINT] = 7,
532 [IRQ_AEMIFINT] = 7,
533 [IRQ_DM355_SDIOINT1] = 4,
534 [IRQ_TINT0_TINT12] = 2, /* clockevent */
535 [IRQ_TINT0_TINT34] = 2, /* clocksource */
536 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
537 [IRQ_TINT1_TINT34] = 7, /* system tick */
538 [IRQ_PWMINT0] = 7,
539 [IRQ_PWMINT1] = 7,
540 [IRQ_PWMINT2] = 7,
541 [IRQ_I2C] = 3,
542 [IRQ_UARTINT0] = 3,
543 [IRQ_UARTINT1] = 3,
544 [IRQ_DM355_SPINT0_0] = 3,
545 [IRQ_DM355_SPINT0_1] = 3,
546 [IRQ_DM355_GPIO0] = 3,
547 [IRQ_DM355_GPIO1] = 7,
548 [IRQ_DM355_GPIO2] = 4,
549 [IRQ_DM355_GPIO3] = 4,
550 [IRQ_DM355_GPIO4] = 7,
551 [IRQ_DM355_GPIO5] = 7,
552 [IRQ_DM355_GPIO6] = 7,
553 [IRQ_DM355_GPIO7] = 7,
554 [IRQ_DM355_GPIO8] = 7,
555 [IRQ_DM355_GPIO9] = 7,
556 [IRQ_DM355_GPIOBNK0] = 7,
557 [IRQ_DM355_GPIOBNK1] = 7,
558 [IRQ_DM355_GPIOBNK2] = 7,
559 [IRQ_DM355_GPIOBNK3] = 7,
560 [IRQ_DM355_GPIOBNK4] = 7,
561 [IRQ_DM355_GPIOBNK5] = 7,
562 [IRQ_DM355_GPIOBNK6] = 7,
563 [IRQ_COMMTX] = 7,
564 [IRQ_COMMRX] = 7,
565 [IRQ_EMUINT] = 7,
566 };
567
568 /*----------------------------------------------------------------------*/
569
570 static const s8
571 queue_tc_mapping[][2] = {
572 /* {event queue no, TC no} */
573 {0, 0},
574 {1, 1},
575 {-1, -1},
576 };
577
578 static const s8
579 queue_priority_mapping[][2] = {
580 /* {event queue no, Priority} */
581 {0, 3},
582 {1, 7},
583 {-1, -1},
584 };
585
586 static struct edma_soc_info edma_cc0_info = {
587 .n_channel = 64,
588 .n_region = 4,
589 .n_slot = 128,
590 .n_tc = 2,
591 .n_cc = 1,
592 .queue_tc_mapping = queue_tc_mapping,
593 .queue_priority_mapping = queue_priority_mapping,
594 .default_queue = EVENTQ_1,
595 };
596
597 static struct edma_soc_info *dm355_edma_info[EDMA_MAX_CC] = {
598 &edma_cc0_info,
599 };
600
601 static struct resource edma_resources[] = {
602 {
603 .name = "edma_cc0",
604 .start = 0x01c00000,
605 .end = 0x01c00000 + SZ_64K - 1,
606 .flags = IORESOURCE_MEM,
607 },
608 {
609 .name = "edma_tc0",
610 .start = 0x01c10000,
611 .end = 0x01c10000 + SZ_1K - 1,
612 .flags = IORESOURCE_MEM,
613 },
614 {
615 .name = "edma_tc1",
616 .start = 0x01c10400,
617 .end = 0x01c10400 + SZ_1K - 1,
618 .flags = IORESOURCE_MEM,
619 },
620 {
621 .name = "edma0",
622 .start = IRQ_CCINT0,
623 .flags = IORESOURCE_IRQ,
624 },
625 {
626 .name = "edma0_err",
627 .start = IRQ_CCERRINT,
628 .flags = IORESOURCE_IRQ,
629 },
630 /* not using (or muxing) TC*_ERR */
631 };
632
633 static struct platform_device dm355_edma_device = {
634 .name = "edma",
635 .id = 0,
636 .dev.platform_data = dm355_edma_info,
637 .num_resources = ARRAY_SIZE(edma_resources),
638 .resource = edma_resources,
639 };
640
641 static struct resource dm355_asp1_resources[] = {
642 {
643 .start = DAVINCI_ASP1_BASE,
644 .end = DAVINCI_ASP1_BASE + SZ_8K - 1,
645 .flags = IORESOURCE_MEM,
646 },
647 {
648 .start = DAVINCI_DMA_ASP1_TX,
649 .end = DAVINCI_DMA_ASP1_TX,
650 .flags = IORESOURCE_DMA,
651 },
652 {
653 .start = DAVINCI_DMA_ASP1_RX,
654 .end = DAVINCI_DMA_ASP1_RX,
655 .flags = IORESOURCE_DMA,
656 },
657 };
658
659 static struct platform_device dm355_asp1_device = {
660 .name = "davinci-mcbsp",
661 .id = 1,
662 .num_resources = ARRAY_SIZE(dm355_asp1_resources),
663 .resource = dm355_asp1_resources,
664 };
665
dm355_ccdc_setup_pinmux(void)666 static void dm355_ccdc_setup_pinmux(void)
667 {
668 davinci_cfg_reg(DM355_VIN_PCLK);
669 davinci_cfg_reg(DM355_VIN_CAM_WEN);
670 davinci_cfg_reg(DM355_VIN_CAM_VD);
671 davinci_cfg_reg(DM355_VIN_CAM_HD);
672 davinci_cfg_reg(DM355_VIN_YIN_EN);
673 davinci_cfg_reg(DM355_VIN_CINL_EN);
674 davinci_cfg_reg(DM355_VIN_CINH_EN);
675 }
676
677 static struct resource dm355_vpss_resources[] = {
678 {
679 /* VPSS BL Base address */
680 .name = "vpss",
681 .start = 0x01c70800,
682 .end = 0x01c70800 + 0xff,
683 .flags = IORESOURCE_MEM,
684 },
685 {
686 /* VPSS CLK Base address */
687 .name = "vpss",
688 .start = 0x01c70000,
689 .end = 0x01c70000 + 0xf,
690 .flags = IORESOURCE_MEM,
691 },
692 };
693
694 static struct platform_device dm355_vpss_device = {
695 .name = "vpss",
696 .id = -1,
697 .dev.platform_data = "dm355_vpss",
698 .num_resources = ARRAY_SIZE(dm355_vpss_resources),
699 .resource = dm355_vpss_resources,
700 };
701
702 static struct resource vpfe_resources[] = {
703 {
704 .start = IRQ_VDINT0,
705 .end = IRQ_VDINT0,
706 .flags = IORESOURCE_IRQ,
707 },
708 {
709 .start = IRQ_VDINT1,
710 .end = IRQ_VDINT1,
711 .flags = IORESOURCE_IRQ,
712 },
713 };
714
715 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
716 static struct resource dm355_ccdc_resource[] = {
717 /* CCDC Base address */
718 {
719 .flags = IORESOURCE_MEM,
720 .start = 0x01c70600,
721 .end = 0x01c70600 + 0x1ff,
722 },
723 };
724 static struct platform_device dm355_ccdc_dev = {
725 .name = "dm355_ccdc",
726 .id = -1,
727 .num_resources = ARRAY_SIZE(dm355_ccdc_resource),
728 .resource = dm355_ccdc_resource,
729 .dev = {
730 .dma_mask = &vpfe_capture_dma_mask,
731 .coherent_dma_mask = DMA_BIT_MASK(32),
732 .platform_data = dm355_ccdc_setup_pinmux,
733 },
734 };
735
736 static struct platform_device vpfe_capture_dev = {
737 .name = CAPTURE_DRV_NAME,
738 .id = -1,
739 .num_resources = ARRAY_SIZE(vpfe_resources),
740 .resource = vpfe_resources,
741 .dev = {
742 .dma_mask = &vpfe_capture_dma_mask,
743 .coherent_dma_mask = DMA_BIT_MASK(32),
744 },
745 };
746
dm355_set_vpfe_config(struct vpfe_config * cfg)747 void dm355_set_vpfe_config(struct vpfe_config *cfg)
748 {
749 vpfe_capture_dev.dev.platform_data = cfg;
750 }
751
752 /*----------------------------------------------------------------------*/
753
754 static struct map_desc dm355_io_desc[] = {
755 {
756 .virtual = IO_VIRT,
757 .pfn = __phys_to_pfn(IO_PHYS),
758 .length = IO_SIZE,
759 .type = MT_DEVICE
760 },
761 {
762 .virtual = SRAM_VIRT,
763 .pfn = __phys_to_pfn(0x00010000),
764 .length = SZ_32K,
765 .type = MT_MEMORY_NONCACHED,
766 },
767 };
768
769 /* Contents of JTAG ID register used to identify exact cpu type */
770 static struct davinci_id dm355_ids[] = {
771 {
772 .variant = 0x0,
773 .part_no = 0xb73b,
774 .manufacturer = 0x00f,
775 .cpu_id = DAVINCI_CPU_ID_DM355,
776 .name = "dm355",
777 },
778 };
779
780 static u32 dm355_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
781
782 /*
783 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
784 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
785 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
786 * T1_TOP: Timer 1, top : <unused>
787 */
788 static struct davinci_timer_info dm355_timer_info = {
789 .timers = davinci_timer_instance,
790 .clockevent_id = T0_BOT,
791 .clocksource_id = T0_TOP,
792 };
793
794 static struct plat_serial8250_port dm355_serial_platform_data[] = {
795 {
796 .mapbase = DAVINCI_UART0_BASE,
797 .irq = IRQ_UARTINT0,
798 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
799 UPF_IOREMAP,
800 .iotype = UPIO_MEM,
801 .regshift = 2,
802 },
803 {
804 .mapbase = DAVINCI_UART1_BASE,
805 .irq = IRQ_UARTINT1,
806 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
807 UPF_IOREMAP,
808 .iotype = UPIO_MEM,
809 .regshift = 2,
810 },
811 {
812 .mapbase = DM355_UART2_BASE,
813 .irq = IRQ_DM355_UARTINT2,
814 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
815 UPF_IOREMAP,
816 .iotype = UPIO_MEM,
817 .regshift = 2,
818 },
819 {
820 .flags = 0
821 },
822 };
823
824 static struct platform_device dm355_serial_device = {
825 .name = "serial8250",
826 .id = PLAT8250_DEV_PLATFORM,
827 .dev = {
828 .platform_data = dm355_serial_platform_data,
829 },
830 };
831
832 static struct davinci_soc_info davinci_soc_info_dm355 = {
833 .io_desc = dm355_io_desc,
834 .io_desc_num = ARRAY_SIZE(dm355_io_desc),
835 .jtag_id_reg = 0x01c40028,
836 .ids = dm355_ids,
837 .ids_num = ARRAY_SIZE(dm355_ids),
838 .cpu_clks = dm355_clks,
839 .psc_bases = dm355_psc_bases,
840 .psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
841 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
842 .pinmux_pins = dm355_pins,
843 .pinmux_pins_num = ARRAY_SIZE(dm355_pins),
844 .intc_base = DAVINCI_ARM_INTC_BASE,
845 .intc_type = DAVINCI_INTC_TYPE_AINTC,
846 .intc_irq_prios = dm355_default_priorities,
847 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
848 .timer_info = &dm355_timer_info,
849 .gpio_type = GPIO_TYPE_DAVINCI,
850 .gpio_base = DAVINCI_GPIO_BASE,
851 .gpio_num = 104,
852 .gpio_irq = IRQ_DM355_GPIOBNK0,
853 .serial_dev = &dm355_serial_device,
854 .sram_dma = 0x00010000,
855 .sram_len = SZ_32K,
856 };
857
dm355_init_asp1(u32 evt_enable,struct snd_platform_data * pdata)858 void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
859 {
860 /* we don't use ASP1 IRQs, or we'd need to mux them ... */
861 if (evt_enable & ASP1_TX_EVT_EN)
862 davinci_cfg_reg(DM355_EVT8_ASP1_TX);
863
864 if (evt_enable & ASP1_RX_EVT_EN)
865 davinci_cfg_reg(DM355_EVT9_ASP1_RX);
866
867 dm355_asp1_device.dev.platform_data = pdata;
868 platform_device_register(&dm355_asp1_device);
869 }
870
dm355_init(void)871 void __init dm355_init(void)
872 {
873 davinci_common_init(&davinci_soc_info_dm355);
874 }
875
dm355_init_devices(void)876 static int __init dm355_init_devices(void)
877 {
878 if (!cpu_is_davinci_dm355())
879 return 0;
880
881 /* Add ccdc clock aliases */
882 clk_add_alias("master", dm355_ccdc_dev.name, "vpss_master", NULL);
883 clk_add_alias("slave", dm355_ccdc_dev.name, "vpss_master", NULL);
884 davinci_cfg_reg(DM355_INT_EDMA_CC);
885 platform_device_register(&dm355_edma_device);
886 platform_device_register(&dm355_vpss_device);
887 platform_device_register(&dm355_ccdc_dev);
888 platform_device_register(&vpfe_capture_dev);
889
890 return 0;
891 }
892 postcore_initcall(dm355_init_devices);
893