1 /* 2 * arch/arm/mach-at91/include/mach/at91cap9.h 3 * 4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com> 5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com> 6 * Copyright (C) 2007 Atmel Corporation. 7 * 8 * Common definitions. 9 * Based on AT91CAP9 datasheet revision B (Preliminary). 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #ifndef AT91CAP9_H 18 #define AT91CAP9_H 19 20 /* 21 * Peripheral identifiers/interrupts. 22 */ 23 #define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */ 24 #define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */ 25 #define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */ 26 #define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */ 27 #define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */ 28 #define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */ 29 #define AT91CAP9_ID_US0 8 /* USART 0 */ 30 #define AT91CAP9_ID_US1 9 /* USART 1 */ 31 #define AT91CAP9_ID_US2 10 /* USART 2 */ 32 #define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */ 33 #define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */ 34 #define AT91CAP9_ID_CAN 13 /* CAN */ 35 #define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */ 36 #define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */ 37 #define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */ 38 #define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */ 39 #define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */ 40 #define AT91CAP9_ID_AC97C 19 /* AC97 Controller */ 41 #define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */ 42 #define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */ 43 #define AT91CAP9_ID_EMAC 22 /* Ethernet */ 44 #define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */ 45 #define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */ 46 #define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */ 47 #define AT91CAP9_ID_LCDC 26 /* LCD Controller */ 48 #define AT91CAP9_ID_DMA 27 /* DMA Controller */ 49 #define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */ 50 #define AT91CAP9_ID_UHP 29 /* USB Host Port */ 51 #define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ 52 #define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ 53 54 /* 55 * User Peripheral physical base addresses. 56 */ 57 #define AT91CAP9_BASE_UDPHS 0xfff78000 58 #define AT91CAP9_BASE_TCB0 0xfff7c000 59 #define AT91CAP9_BASE_TC0 0xfff7c000 60 #define AT91CAP9_BASE_TC1 0xfff7c040 61 #define AT91CAP9_BASE_TC2 0xfff7c080 62 #define AT91CAP9_BASE_MCI0 0xfff80000 63 #define AT91CAP9_BASE_MCI1 0xfff84000 64 #define AT91CAP9_BASE_TWI 0xfff88000 65 #define AT91CAP9_BASE_US0 0xfff8c000 66 #define AT91CAP9_BASE_US1 0xfff90000 67 #define AT91CAP9_BASE_US2 0xfff94000 68 #define AT91CAP9_BASE_SSC0 0xfff98000 69 #define AT91CAP9_BASE_SSC1 0xfff9c000 70 #define AT91CAP9_BASE_AC97C 0xfffa0000 71 #define AT91CAP9_BASE_SPI0 0xfffa4000 72 #define AT91CAP9_BASE_SPI1 0xfffa8000 73 #define AT91CAP9_BASE_CAN 0xfffac000 74 #define AT91CAP9_BASE_PWMC 0xfffb8000 75 #define AT91CAP9_BASE_EMAC 0xfffbc000 76 #define AT91CAP9_BASE_ADC 0xfffc0000 77 #define AT91CAP9_BASE_ISI 0xfffc4000 78 79 /* 80 * System Peripherals (offset from AT91_BASE_SYS) 81 */ 82 #define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS) 83 #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) 84 #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) 85 #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 86 #define AT91_GPBR (cpu_is_at91cap9_revB() ? \ 87 (0xfffffd50 - AT91_BASE_SYS) : \ 88 (0xfffffd60 - AT91_BASE_SYS)) 89 90 #define AT91CAP9_BASE_ECC 0xffffe200 91 #define AT91CAP9_BASE_DMA 0xffffec00 92 #define AT91CAP9_BASE_SMC 0xffffe800 93 #define AT91CAP9_BASE_DBGU AT91_BASE_DBGU1 94 #define AT91CAP9_BASE_PIOA 0xfffff200 95 #define AT91CAP9_BASE_PIOB 0xfffff400 96 #define AT91CAP9_BASE_PIOC 0xfffff600 97 #define AT91CAP9_BASE_PIOD 0xfffff800 98 #define AT91CAP9_BASE_RSTC 0xfffffd00 99 #define AT91CAP9_BASE_SHDWC 0xfffffd10 100 #define AT91CAP9_BASE_RTT 0xfffffd20 101 #define AT91CAP9_BASE_PIT 0xfffffd30 102 #define AT91CAP9_BASE_WDT 0xfffffd40 103 104 #define AT91_USART0 AT91CAP9_BASE_US0 105 #define AT91_USART1 AT91CAP9_BASE_US1 106 #define AT91_USART2 AT91CAP9_BASE_US2 107 108 109 /* 110 * Internal Memory. 111 */ 112 #define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */ 113 #define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */ 114 115 #define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */ 116 #define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */ 117 118 #define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */ 119 #define AT91CAP9_UDPHS_FIFO 0x00600000 /* USB High Speed Device Port */ 120 #define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */ 121 122 #endif 123