1 /* 2 * arch/arm/mach-at91/include/mach/at91_spi.h 3 * 4 * Copyright (C) 2005 Ivan Kokshaysky 5 * Copyright (C) SAN People 6 * 7 * Serial Peripheral Interface (SPI) registers. 8 * Based on AT91RM9200 datasheet revision E. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 */ 15 16 #ifndef AT91_SPI_H 17 #define AT91_SPI_H 18 19 #define AT91_SPI_CR 0x00 /* Control Register */ 20 #define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ 21 #define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */ 22 #define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */ 23 #define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ 24 25 #define AT91_SPI_MR 0x04 /* Mode Register */ 26 #define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */ 27 #define AT91_SPI_PS (1 << 1) /* Peripheral Select */ 28 #define AT91_SPI_PS_FIXED (0 << 1) 29 #define AT91_SPI_PS_VARIABLE (1 << 1) 30 #define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */ 31 #define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */ 32 #define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */ 33 #define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */ 34 #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ 35 #define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */ 36 37 #define AT91_SPI_RDR 0x08 /* Receive Data Register */ 38 #define AT91_SPI_RD (0xffff << 0) /* Receive Data */ 39 #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ 40 41 #define AT91_SPI_TDR 0x0c /* Transmit Data Register */ 42 #define AT91_SPI_TD (0xffff << 0) /* Transmit Data */ 43 #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ 44 #define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ 45 46 #define AT91_SPI_SR 0x10 /* Status Register */ 47 #define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */ 48 #define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */ 49 #define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */ 50 #define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */ 51 #define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */ 52 #define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */ 53 #define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */ 54 #define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */ 55 #define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */ 56 #define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */ 57 #define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */ 58 59 #define AT91_SPI_IER 0x14 /* Interrupt Enable Register */ 60 #define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */ 61 #define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */ 62 63 #define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */ 64 #define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */ 65 #define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */ 66 #define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */ 67 #define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */ 68 #define AT91_SPI_BITS_8 (0 << 4) 69 #define AT91_SPI_BITS_9 (1 << 4) 70 #define AT91_SPI_BITS_10 (2 << 4) 71 #define AT91_SPI_BITS_11 (3 << 4) 72 #define AT91_SPI_BITS_12 (4 << 4) 73 #define AT91_SPI_BITS_13 (5 << 4) 74 #define AT91_SPI_BITS_14 (6 << 4) 75 #define AT91_SPI_BITS_15 (7 << 4) 76 #define AT91_SPI_BITS_16 (8 << 4) 77 #define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */ 78 #define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */ 79 #define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */ 80 81 #endif 82