1 /*
2 * linux/arch/arm/mach-at91/clock.c
3 *
4 * Copyright (C) 2005 David Brownell
5 * Copyright (C) 2005 Ivan Kokshaysky
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/fs.h>
17 #include <linux/debugfs.h>
18 #include <linux/seq_file.h>
19 #include <linux/list.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/spinlock.h>
23 #include <linux/delay.h>
24 #include <linux/clk.h>
25 #include <linux/io.h>
26
27 #include <mach/hardware.h>
28 #include <mach/at91_pmc.h>
29 #include <mach/cpu.h>
30
31 #include "clock.h"
32 #include "generic.h"
33
34
35 /*
36 * There's a lot more which can be done with clocks, including cpufreq
37 * integration, slow clock mode support (for system suspend), letting
38 * PLLB be used at other rates (on boards that don't need USB), etc.
39 */
40
41 #define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
42 #define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
43 #define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
44 #define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM)
45
46
47 /*
48 * Chips have some kind of clocks : group them by functionality
49 */
50 #define cpu_has_utmi() ( cpu_is_at91cap9() \
51 || cpu_is_at91sam9rl() \
52 || cpu_is_at91sam9g45())
53
54 #define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
55 || cpu_is_at91sam9g45())
56
57 #define cpu_has_300M_plla() (cpu_is_at91sam9g10())
58
59 #define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
60 || cpu_is_at91sam9g45()))
61
62 #define cpu_has_upll() (cpu_is_at91sam9g45())
63
64 /* USB host HS & FS */
65 #define cpu_has_uhp() (!cpu_is_at91sam9rl())
66
67 /* USB device FS only */
68 #define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
69 || cpu_is_at91sam9g45()))
70
71 static LIST_HEAD(clocks);
72 static DEFINE_SPINLOCK(clk_lock);
73
74 static u32 at91_pllb_usb_init;
75
76 /*
77 * Four primary clock sources: two crystal oscillators (32K, main), and
78 * two PLLs. PLLA usually runs the master clock; and PLLB must run at
79 * 48 MHz (unless no USB function clocks are needed). The main clock and
80 * both PLLs are turned off to run in "slow clock mode" (system suspend).
81 */
82 static struct clk clk32k = {
83 .name = "clk32k",
84 .rate_hz = AT91_SLOW_CLOCK,
85 .users = 1, /* always on */
86 .id = 0,
87 .type = CLK_TYPE_PRIMARY,
88 };
89 static struct clk main_clk = {
90 .name = "main",
91 .pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */
92 .id = 1,
93 .type = CLK_TYPE_PRIMARY,
94 };
95 static struct clk plla = {
96 .name = "plla",
97 .parent = &main_clk,
98 .pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */
99 .id = 2,
100 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
101 };
102
pllb_mode(struct clk * clk,int is_on)103 static void pllb_mode(struct clk *clk, int is_on)
104 {
105 u32 value;
106
107 if (is_on) {
108 is_on = AT91_PMC_LOCKB;
109 value = at91_pllb_usb_init;
110 } else
111 value = 0;
112
113 // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
114 at91_sys_write(AT91_CKGR_PLLBR, value);
115
116 do {
117 cpu_relax();
118 } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
119 }
120
121 static struct clk pllb = {
122 .name = "pllb",
123 .parent = &main_clk,
124 .pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */
125 .mode = pllb_mode,
126 .id = 3,
127 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
128 };
129
pmc_sys_mode(struct clk * clk,int is_on)130 static void pmc_sys_mode(struct clk *clk, int is_on)
131 {
132 if (is_on)
133 at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
134 else
135 at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
136 }
137
pmc_uckr_mode(struct clk * clk,int is_on)138 static void pmc_uckr_mode(struct clk *clk, int is_on)
139 {
140 unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
141
142 if (cpu_is_at91sam9g45()) {
143 if (is_on)
144 uckr |= AT91_PMC_BIASEN;
145 else
146 uckr &= ~AT91_PMC_BIASEN;
147 }
148
149 if (is_on) {
150 is_on = AT91_PMC_LOCKU;
151 at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
152 } else
153 at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
154
155 do {
156 cpu_relax();
157 } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
158 }
159
160 /* USB function clocks (PLLB must be 48 MHz) */
161 static struct clk udpck = {
162 .name = "udpck",
163 .parent = &pllb,
164 .mode = pmc_sys_mode,
165 };
166 struct clk utmi_clk = {
167 .name = "utmi_clk",
168 .parent = &main_clk,
169 .pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */
170 .mode = pmc_uckr_mode,
171 .type = CLK_TYPE_PLL,
172 };
173 static struct clk uhpck = {
174 .name = "uhpck",
175 /*.parent = ... we choose parent at runtime */
176 .mode = pmc_sys_mode,
177 };
178
179
180 /*
181 * The master clock is divided from the CPU clock (by 1-4). It's used for
182 * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
183 * (e.g baud rate generation). It's sourced from one of the primary clocks.
184 */
185 struct clk mck = {
186 .name = "mck",
187 .pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */
188 };
189
pmc_periph_mode(struct clk * clk,int is_on)190 static void pmc_periph_mode(struct clk *clk, int is_on)
191 {
192 if (is_on)
193 at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
194 else
195 at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
196 }
197
at91_css_to_clk(unsigned long css)198 static struct clk __init *at91_css_to_clk(unsigned long css)
199 {
200 switch (css) {
201 case AT91_PMC_CSS_SLOW:
202 return &clk32k;
203 case AT91_PMC_CSS_MAIN:
204 return &main_clk;
205 case AT91_PMC_CSS_PLLA:
206 return &plla;
207 case AT91_PMC_CSS_PLLB:
208 if (cpu_has_upll())
209 /* CSS_PLLB == CSS_UPLL */
210 return &utmi_clk;
211 else if (cpu_has_pllb())
212 return &pllb;
213 }
214
215 return NULL;
216 }
217
__clk_enable(struct clk * clk)218 static void __clk_enable(struct clk *clk)
219 {
220 if (clk->parent)
221 __clk_enable(clk->parent);
222 if (clk->users++ == 0 && clk->mode)
223 clk->mode(clk, 1);
224 }
225
clk_enable(struct clk * clk)226 int clk_enable(struct clk *clk)
227 {
228 unsigned long flags;
229
230 spin_lock_irqsave(&clk_lock, flags);
231 __clk_enable(clk);
232 spin_unlock_irqrestore(&clk_lock, flags);
233 return 0;
234 }
235 EXPORT_SYMBOL(clk_enable);
236
__clk_disable(struct clk * clk)237 static void __clk_disable(struct clk *clk)
238 {
239 BUG_ON(clk->users == 0);
240 if (--clk->users == 0 && clk->mode)
241 clk->mode(clk, 0);
242 if (clk->parent)
243 __clk_disable(clk->parent);
244 }
245
clk_disable(struct clk * clk)246 void clk_disable(struct clk *clk)
247 {
248 unsigned long flags;
249
250 spin_lock_irqsave(&clk_lock, flags);
251 __clk_disable(clk);
252 spin_unlock_irqrestore(&clk_lock, flags);
253 }
254 EXPORT_SYMBOL(clk_disable);
255
clk_get_rate(struct clk * clk)256 unsigned long clk_get_rate(struct clk *clk)
257 {
258 unsigned long flags;
259 unsigned long rate;
260
261 spin_lock_irqsave(&clk_lock, flags);
262 for (;;) {
263 rate = clk->rate_hz;
264 if (rate || !clk->parent)
265 break;
266 clk = clk->parent;
267 }
268 spin_unlock_irqrestore(&clk_lock, flags);
269 return rate;
270 }
271 EXPORT_SYMBOL(clk_get_rate);
272
273 /*------------------------------------------------------------------------*/
274
275 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
276
277 /*
278 * For now, only the programmable clocks support reparenting (MCK could
279 * do this too, with care) or rate changing (the PLLs could do this too,
280 * ditto MCK but that's more for cpufreq). Drivers may reparent to get
281 * a better rate match; we don't.
282 */
283
clk_round_rate(struct clk * clk,unsigned long rate)284 long clk_round_rate(struct clk *clk, unsigned long rate)
285 {
286 unsigned long flags;
287 unsigned prescale;
288 unsigned long actual;
289 unsigned long prev = ULONG_MAX;
290
291 if (!clk_is_programmable(clk))
292 return -EINVAL;
293 spin_lock_irqsave(&clk_lock, flags);
294
295 actual = clk->parent->rate_hz;
296 for (prescale = 0; prescale < 7; prescale++) {
297 if (actual > rate)
298 prev = actual;
299
300 if (actual && actual <= rate) {
301 if ((prev - rate) < (rate - actual)) {
302 actual = prev;
303 prescale--;
304 }
305 break;
306 }
307 actual >>= 1;
308 }
309
310 spin_unlock_irqrestore(&clk_lock, flags);
311 return (prescale < 7) ? actual : -ENOENT;
312 }
313 EXPORT_SYMBOL(clk_round_rate);
314
clk_set_rate(struct clk * clk,unsigned long rate)315 int clk_set_rate(struct clk *clk, unsigned long rate)
316 {
317 unsigned long flags;
318 unsigned prescale;
319 unsigned long actual;
320
321 if (!clk_is_programmable(clk))
322 return -EINVAL;
323 if (clk->users)
324 return -EBUSY;
325 spin_lock_irqsave(&clk_lock, flags);
326
327 actual = clk->parent->rate_hz;
328 for (prescale = 0; prescale < 7; prescale++) {
329 if (actual && actual <= rate) {
330 u32 pckr;
331
332 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
333 pckr &= AT91_PMC_CSS; /* clock selection */
334 pckr |= prescale << 2;
335 at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
336 clk->rate_hz = actual;
337 break;
338 }
339 actual >>= 1;
340 }
341
342 spin_unlock_irqrestore(&clk_lock, flags);
343 return (prescale < 7) ? actual : -ENOENT;
344 }
345 EXPORT_SYMBOL(clk_set_rate);
346
clk_get_parent(struct clk * clk)347 struct clk *clk_get_parent(struct clk *clk)
348 {
349 return clk->parent;
350 }
351 EXPORT_SYMBOL(clk_get_parent);
352
clk_set_parent(struct clk * clk,struct clk * parent)353 int clk_set_parent(struct clk *clk, struct clk *parent)
354 {
355 unsigned long flags;
356
357 if (clk->users)
358 return -EBUSY;
359 if (!clk_is_primary(parent) || !clk_is_programmable(clk))
360 return -EINVAL;
361
362 if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
363 return -EINVAL;
364
365 spin_lock_irqsave(&clk_lock, flags);
366
367 clk->rate_hz = parent->rate_hz;
368 clk->parent = parent;
369 at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
370
371 spin_unlock_irqrestore(&clk_lock, flags);
372 return 0;
373 }
374 EXPORT_SYMBOL(clk_set_parent);
375
376 /* establish PCK0..PCKN parentage and rate */
init_programmable_clock(struct clk * clk)377 static void __init init_programmable_clock(struct clk *clk)
378 {
379 struct clk *parent;
380 u32 pckr;
381
382 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
383 parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
384 clk->parent = parent;
385 clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
386 }
387
388 #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
389
390 /*------------------------------------------------------------------------*/
391
392 #ifdef CONFIG_DEBUG_FS
393
at91_clk_show(struct seq_file * s,void * unused)394 static int at91_clk_show(struct seq_file *s, void *unused)
395 {
396 u32 scsr, pcsr, uckr = 0, sr;
397 struct clk *clk;
398
399 seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
400 seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
401 seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR));
402 seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
403 seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
404 if (cpu_has_pllb())
405 seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
406 if (cpu_has_utmi())
407 seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
408 seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
409 if (cpu_has_upll())
410 seq_printf(s, "USB = %8x\n", at91_sys_read(AT91_PMC_USB));
411 seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
412
413 seq_printf(s, "\n");
414
415 list_for_each_entry(clk, &clocks, node) {
416 char *state;
417
418 if (clk->mode == pmc_sys_mode)
419 state = (scsr & clk->pmc_mask) ? "on" : "off";
420 else if (clk->mode == pmc_periph_mode)
421 state = (pcsr & clk->pmc_mask) ? "on" : "off";
422 else if (clk->mode == pmc_uckr_mode)
423 state = (uckr & clk->pmc_mask) ? "on" : "off";
424 else if (clk->pmc_mask)
425 state = (sr & clk->pmc_mask) ? "on" : "off";
426 else if (clk == &clk32k || clk == &main_clk)
427 state = "on";
428 else
429 state = "";
430
431 seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
432 clk->name, clk->users, state, clk_get_rate(clk),
433 clk->parent ? clk->parent->name : "");
434 }
435 return 0;
436 }
437
at91_clk_open(struct inode * inode,struct file * file)438 static int at91_clk_open(struct inode *inode, struct file *file)
439 {
440 return single_open(file, at91_clk_show, NULL);
441 }
442
443 static const struct file_operations at91_clk_operations = {
444 .open = at91_clk_open,
445 .read = seq_read,
446 .llseek = seq_lseek,
447 .release = single_release,
448 };
449
at91_clk_debugfs_init(void)450 static int __init at91_clk_debugfs_init(void)
451 {
452 /* /sys/kernel/debug/at91_clk */
453 (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
454
455 return 0;
456 }
457 postcore_initcall(at91_clk_debugfs_init);
458
459 #endif
460
461 /*------------------------------------------------------------------------*/
462
463 /* Register a new clock */
at91_clk_add(struct clk * clk)464 static void __init at91_clk_add(struct clk *clk)
465 {
466 list_add_tail(&clk->node, &clocks);
467
468 clk->cl.con_id = clk->name;
469 clk->cl.clk = clk;
470 clkdev_add(&clk->cl);
471 }
472
clk_register(struct clk * clk)473 int __init clk_register(struct clk *clk)
474 {
475 if (clk_is_peripheral(clk)) {
476 if (!clk->parent)
477 clk->parent = &mck;
478 clk->mode = pmc_periph_mode;
479 }
480 else if (clk_is_sys(clk)) {
481 clk->parent = &mck;
482 clk->mode = pmc_sys_mode;
483 }
484 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
485 else if (clk_is_programmable(clk)) {
486 clk->mode = pmc_sys_mode;
487 init_programmable_clock(clk);
488 }
489 #endif
490
491 at91_clk_add(clk);
492
493 return 0;
494 }
495
496 /*------------------------------------------------------------------------*/
497
at91_pll_rate(struct clk * pll,u32 freq,u32 reg)498 static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
499 {
500 unsigned mul, div;
501
502 div = reg & 0xff;
503 mul = (reg >> 16) & 0x7ff;
504 if (div && mul) {
505 freq /= div;
506 freq *= mul + 1;
507 } else
508 freq = 0;
509
510 return freq;
511 }
512
at91_usb_rate(struct clk * pll,u32 freq,u32 reg)513 static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
514 {
515 if (pll == &pllb && (reg & AT91_PMC_USB96M))
516 return freq / 2;
517 else
518 return freq;
519 }
520
at91_pll_calc(unsigned main_freq,unsigned out_freq)521 static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
522 {
523 unsigned i, div = 0, mul = 0, diff = 1 << 30;
524 unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
525
526 /* PLL output max 240 MHz (or 180 MHz per errata) */
527 if (out_freq > 240000000)
528 goto fail;
529
530 for (i = 1; i < 256; i++) {
531 int diff1;
532 unsigned input, mul1;
533
534 /*
535 * PLL input between 1MHz and 32MHz per spec, but lower
536 * frequences seem necessary in some cases so allow 100K.
537 * Warning: some newer products need 2MHz min.
538 */
539 input = main_freq / i;
540 if (cpu_is_at91sam9g20() && input < 2000000)
541 continue;
542 if (input < 100000)
543 continue;
544 if (input > 32000000)
545 continue;
546
547 mul1 = out_freq / input;
548 if (cpu_is_at91sam9g20() && mul > 63)
549 continue;
550 if (mul1 > 2048)
551 continue;
552 if (mul1 < 2)
553 goto fail;
554
555 diff1 = out_freq - input * mul1;
556 if (diff1 < 0)
557 diff1 = -diff1;
558 if (diff > diff1) {
559 diff = diff1;
560 div = i;
561 mul = mul1;
562 if (diff == 0)
563 break;
564 }
565 }
566 if (i == 256 && diff > (out_freq >> 5))
567 goto fail;
568 return ret | ((mul - 1) << 16) | div;
569 fail:
570 return 0;
571 }
572
573 static struct clk *const standard_pmc_clocks[] __initdata = {
574 /* four primary clocks */
575 &clk32k,
576 &main_clk,
577 &plla,
578
579 /* MCK */
580 &mck
581 };
582
583 /* PLLB generated USB full speed clock init */
at91_pllb_usbfs_clock_init(unsigned long main_clock)584 static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
585 {
586 /*
587 * USB clock init: choose 48 MHz PLLB value,
588 * disable 48MHz clock during usb peripheral suspend.
589 *
590 * REVISIT: assumes MCK doesn't derive from PLLB!
591 */
592 uhpck.parent = &pllb;
593
594 at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
595 pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
596 if (cpu_is_at91rm9200()) {
597 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
598 udpck.pmc_mask = AT91RM9200_PMC_UDP;
599 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
600 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
601 cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
602 cpu_is_at91sam9g10()) {
603 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
604 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
605 } else if (cpu_is_at91cap9()) {
606 uhpck.pmc_mask = AT91CAP9_PMC_UHP;
607 }
608 at91_sys_write(AT91_CKGR_PLLBR, 0);
609
610 udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
611 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
612 }
613
614 /* UPLL generated USB full speed clock init */
at91_upll_usbfs_clock_init(unsigned long main_clock)615 static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
616 {
617 /*
618 * USB clock init: choose 480 MHz from UPLL,
619 */
620 unsigned int usbr = AT91_PMC_USBS_UPLL;
621
622 /* Setup divider by 10 to reach 48 MHz */
623 usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
624
625 at91_sys_write(AT91_PMC_USB, usbr);
626
627 /* Now set uhpck values */
628 uhpck.parent = &utmi_clk;
629 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
630 uhpck.rate_hz = utmi_clk.rate_hz;
631 uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
632 }
633
at91_clock_init(unsigned long main_clock)634 int __init at91_clock_init(unsigned long main_clock)
635 {
636 unsigned tmp, freq, mckr;
637 int i;
638 int pll_overclock = false;
639
640 /*
641 * When the bootloader initialized the main oscillator correctly,
642 * there's no problem using the cycle counter. But if it didn't,
643 * or when using oscillator bypass mode, we must be told the speed
644 * of the main clock.
645 */
646 if (!main_clock) {
647 do {
648 tmp = at91_sys_read(AT91_CKGR_MCFR);
649 } while (!(tmp & AT91_PMC_MAINRDY));
650 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
651 }
652 main_clk.rate_hz = main_clock;
653
654 /* report if PLLA is more than mildly overclocked */
655 plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
656 if (cpu_has_300M_plla()) {
657 if (plla.rate_hz > 300000000)
658 pll_overclock = true;
659 } else if (cpu_has_800M_plla()) {
660 if (plla.rate_hz > 800000000)
661 pll_overclock = true;
662 } else {
663 if (plla.rate_hz > 209000000)
664 pll_overclock = true;
665 }
666 if (pll_overclock)
667 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
668
669 if (cpu_is_at91sam9g45()) {
670 mckr = at91_sys_read(AT91_PMC_MCKR);
671 plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
672 }
673
674 if (!cpu_has_pllb() && cpu_has_upll()) {
675 /* setup UTMI clock as the fourth primary clock
676 * (instead of pllb) */
677 utmi_clk.type |= CLK_TYPE_PRIMARY;
678 utmi_clk.id = 3;
679 }
680
681
682 /*
683 * USB HS clock init
684 */
685 if (cpu_has_utmi()) {
686 /*
687 * multiplier is hard-wired to 40
688 * (obtain the USB High Speed 480 MHz when input is 12 MHz)
689 */
690 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
691 }
692
693 /*
694 * USB FS clock init
695 */
696 if (cpu_has_pllb())
697 at91_pllb_usbfs_clock_init(main_clock);
698 if (cpu_has_upll())
699 /* assumes that we choose UPLL for USB and not PLLA */
700 at91_upll_usbfs_clock_init(main_clock);
701
702 /*
703 * MCK and CPU derive from one of those primary clocks.
704 * For now, assume this parentage won't change.
705 */
706 mckr = at91_sys_read(AT91_PMC_MCKR);
707 mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
708 freq = mck.parent->rate_hz;
709 freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */
710 if (cpu_is_at91rm9200()) {
711 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
712 } else if (cpu_is_at91sam9g20()) {
713 mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
714 freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
715 if (mckr & AT91_PMC_PDIV)
716 freq /= 2; /* processor clock division */
717 } else if (cpu_is_at91sam9g45()) {
718 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
719 freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
720 } else {
721 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
722 }
723
724 /* Register the PMC's standard clocks */
725 for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
726 at91_clk_add(standard_pmc_clocks[i]);
727
728 if (cpu_has_pllb())
729 at91_clk_add(&pllb);
730
731 if (cpu_has_uhp())
732 at91_clk_add(&uhpck);
733
734 if (cpu_has_udpfs())
735 at91_clk_add(&udpck);
736
737 if (cpu_has_utmi())
738 at91_clk_add(&utmi_clk);
739
740 /* MCK and CPU clock are "always on" */
741 clk_enable(&mck);
742
743 printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
744 freq / 1000000, (unsigned) mck.rate_hz / 1000000,
745 (unsigned) main_clock / 1000000,
746 ((unsigned) main_clock % 1000000) / 1000);
747
748 return 0;
749 }
750
751 /*
752 * Several unused clocks may be active. Turn them off.
753 */
at91_clock_reset(void)754 static int __init at91_clock_reset(void)
755 {
756 unsigned long pcdr = 0;
757 unsigned long scdr = 0;
758 struct clk *clk;
759
760 list_for_each_entry(clk, &clocks, node) {
761 if (clk->users > 0)
762 continue;
763
764 if (clk->mode == pmc_periph_mode)
765 pcdr |= clk->pmc_mask;
766
767 if (clk->mode == pmc_sys_mode)
768 scdr |= clk->pmc_mask;
769
770 pr_debug("Clocks: disable unused %s\n", clk->name);
771 }
772
773 at91_sys_write(AT91_PMC_PCDR, pcdr);
774 at91_sys_write(AT91_PMC_SCDR, scdr);
775
776 return 0;
777 }
778 late_initcall(at91_clock_reset);
779