1 /*
2 * arch/arm/mach-at91/at91sam9rl.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2007 Atmel Corporation
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
9 * more details.
10 */
11
12 #include <linux/module.h>
13
14 #include <asm/irq.h>
15 #include <asm/mach/arch.h>
16 #include <asm/mach/map.h>
17 #include <mach/cpu.h>
18 #include <mach/at91_dbgu.h>
19 #include <mach/at91sam9rl.h>
20 #include <mach/at91_pmc.h>
21 #include <mach/at91_rstc.h>
22
23 #include "soc.h"
24 #include "generic.h"
25 #include "clock.h"
26 #include "sam9_smc.h"
27
28 /* --------------------------------------------------------------------
29 * Clocks
30 * -------------------------------------------------------------------- */
31
32 /*
33 * The peripheral clocks.
34 */
35 static struct clk pioA_clk = {
36 .name = "pioA_clk",
37 .pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
38 .type = CLK_TYPE_PERIPHERAL,
39 };
40 static struct clk pioB_clk = {
41 .name = "pioB_clk",
42 .pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
43 .type = CLK_TYPE_PERIPHERAL,
44 };
45 static struct clk pioC_clk = {
46 .name = "pioC_clk",
47 .pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
48 .type = CLK_TYPE_PERIPHERAL,
49 };
50 static struct clk pioD_clk = {
51 .name = "pioD_clk",
52 .pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
53 .type = CLK_TYPE_PERIPHERAL,
54 };
55 static struct clk usart0_clk = {
56 .name = "usart0_clk",
57 .pmc_mask = 1 << AT91SAM9RL_ID_US0,
58 .type = CLK_TYPE_PERIPHERAL,
59 };
60 static struct clk usart1_clk = {
61 .name = "usart1_clk",
62 .pmc_mask = 1 << AT91SAM9RL_ID_US1,
63 .type = CLK_TYPE_PERIPHERAL,
64 };
65 static struct clk usart2_clk = {
66 .name = "usart2_clk",
67 .pmc_mask = 1 << AT91SAM9RL_ID_US2,
68 .type = CLK_TYPE_PERIPHERAL,
69 };
70 static struct clk usart3_clk = {
71 .name = "usart3_clk",
72 .pmc_mask = 1 << AT91SAM9RL_ID_US3,
73 .type = CLK_TYPE_PERIPHERAL,
74 };
75 static struct clk mmc_clk = {
76 .name = "mci_clk",
77 .pmc_mask = 1 << AT91SAM9RL_ID_MCI,
78 .type = CLK_TYPE_PERIPHERAL,
79 };
80 static struct clk twi0_clk = {
81 .name = "twi0_clk",
82 .pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
83 .type = CLK_TYPE_PERIPHERAL,
84 };
85 static struct clk twi1_clk = {
86 .name = "twi1_clk",
87 .pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
88 .type = CLK_TYPE_PERIPHERAL,
89 };
90 static struct clk spi_clk = {
91 .name = "spi_clk",
92 .pmc_mask = 1 << AT91SAM9RL_ID_SPI,
93 .type = CLK_TYPE_PERIPHERAL,
94 };
95 static struct clk ssc0_clk = {
96 .name = "ssc0_clk",
97 .pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
98 .type = CLK_TYPE_PERIPHERAL,
99 };
100 static struct clk ssc1_clk = {
101 .name = "ssc1_clk",
102 .pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
103 .type = CLK_TYPE_PERIPHERAL,
104 };
105 static struct clk tc0_clk = {
106 .name = "tc0_clk",
107 .pmc_mask = 1 << AT91SAM9RL_ID_TC0,
108 .type = CLK_TYPE_PERIPHERAL,
109 };
110 static struct clk tc1_clk = {
111 .name = "tc1_clk",
112 .pmc_mask = 1 << AT91SAM9RL_ID_TC1,
113 .type = CLK_TYPE_PERIPHERAL,
114 };
115 static struct clk tc2_clk = {
116 .name = "tc2_clk",
117 .pmc_mask = 1 << AT91SAM9RL_ID_TC2,
118 .type = CLK_TYPE_PERIPHERAL,
119 };
120 static struct clk pwm_clk = {
121 .name = "pwm_clk",
122 .pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
123 .type = CLK_TYPE_PERIPHERAL,
124 };
125 static struct clk tsc_clk = {
126 .name = "tsc_clk",
127 .pmc_mask = 1 << AT91SAM9RL_ID_TSC,
128 .type = CLK_TYPE_PERIPHERAL,
129 };
130 static struct clk dma_clk = {
131 .name = "dma_clk",
132 .pmc_mask = 1 << AT91SAM9RL_ID_DMA,
133 .type = CLK_TYPE_PERIPHERAL,
134 };
135 static struct clk udphs_clk = {
136 .name = "udphs_clk",
137 .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
138 .type = CLK_TYPE_PERIPHERAL,
139 };
140 static struct clk lcdc_clk = {
141 .name = "lcdc_clk",
142 .pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
143 .type = CLK_TYPE_PERIPHERAL,
144 };
145 static struct clk ac97_clk = {
146 .name = "ac97_clk",
147 .pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
148 .type = CLK_TYPE_PERIPHERAL,
149 };
150
151 static struct clk *periph_clocks[] __initdata = {
152 &pioA_clk,
153 &pioB_clk,
154 &pioC_clk,
155 &pioD_clk,
156 &usart0_clk,
157 &usart1_clk,
158 &usart2_clk,
159 &usart3_clk,
160 &mmc_clk,
161 &twi0_clk,
162 &twi1_clk,
163 &spi_clk,
164 &ssc0_clk,
165 &ssc1_clk,
166 &tc0_clk,
167 &tc1_clk,
168 &tc2_clk,
169 &pwm_clk,
170 &tsc_clk,
171 &dma_clk,
172 &udphs_clk,
173 &lcdc_clk,
174 &ac97_clk,
175 // irq0
176 };
177
178 static struct clk_lookup periph_clocks_lookups[] = {
179 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
180 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
181 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
182 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
183 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
184 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
185 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
186 CLKDEV_CON_ID("pioA", &pioA_clk),
187 CLKDEV_CON_ID("pioB", &pioB_clk),
188 CLKDEV_CON_ID("pioC", &pioC_clk),
189 CLKDEV_CON_ID("pioD", &pioD_clk),
190 };
191
192 static struct clk_lookup usart_clocks_lookups[] = {
193 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
194 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
195 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
196 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
197 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
198 };
199
200 /*
201 * The two programmable clocks.
202 * You must configure pin multiplexing to bring these signals out.
203 */
204 static struct clk pck0 = {
205 .name = "pck0",
206 .pmc_mask = AT91_PMC_PCK0,
207 .type = CLK_TYPE_PROGRAMMABLE,
208 .id = 0,
209 };
210 static struct clk pck1 = {
211 .name = "pck1",
212 .pmc_mask = AT91_PMC_PCK1,
213 .type = CLK_TYPE_PROGRAMMABLE,
214 .id = 1,
215 };
216
at91sam9rl_register_clocks(void)217 static void __init at91sam9rl_register_clocks(void)
218 {
219 int i;
220
221 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
222 clk_register(periph_clocks[i]);
223
224 clkdev_add_table(periph_clocks_lookups,
225 ARRAY_SIZE(periph_clocks_lookups));
226 clkdev_add_table(usart_clocks_lookups,
227 ARRAY_SIZE(usart_clocks_lookups));
228
229 clk_register(&pck0);
230 clk_register(&pck1);
231 }
232
233 static struct clk_lookup console_clock_lookup;
234
at91sam9rl_set_console_clock(int id)235 void __init at91sam9rl_set_console_clock(int id)
236 {
237 if (id >= ARRAY_SIZE(usart_clocks_lookups))
238 return;
239
240 console_clock_lookup.con_id = "usart";
241 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
242 clkdev_add(&console_clock_lookup);
243 }
244
245 /* --------------------------------------------------------------------
246 * GPIO
247 * -------------------------------------------------------------------- */
248
249 static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
250 {
251 .id = AT91SAM9RL_ID_PIOA,
252 .regbase = AT91SAM9RL_BASE_PIOA,
253 }, {
254 .id = AT91SAM9RL_ID_PIOB,
255 .regbase = AT91SAM9RL_BASE_PIOB,
256 }, {
257 .id = AT91SAM9RL_ID_PIOC,
258 .regbase = AT91SAM9RL_BASE_PIOC,
259 }, {
260 .id = AT91SAM9RL_ID_PIOD,
261 .regbase = AT91SAM9RL_BASE_PIOD,
262 }
263 };
264
265 /* --------------------------------------------------------------------
266 * AT91SAM9RL processor initialization
267 * -------------------------------------------------------------------- */
268
at91sam9rl_map_io(void)269 static void __init at91sam9rl_map_io(void)
270 {
271 unsigned long sram_size;
272
273 switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
274 case AT91_CIDR_SRAMSIZ_32K:
275 sram_size = 2 * SZ_16K;
276 break;
277 case AT91_CIDR_SRAMSIZ_16K:
278 default:
279 sram_size = SZ_16K;
280 }
281
282 /* Map SRAM */
283 at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
284 }
285
at91sam9rl_ioremap_registers(void)286 static void __init at91sam9rl_ioremap_registers(void)
287 {
288 at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
289 at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
290 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
291 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
292 }
293
at91sam9rl_initialize(void)294 static void __init at91sam9rl_initialize(void)
295 {
296 arm_pm_restart = at91sam9_alt_restart;
297 at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
298
299 /* Register GPIO subsystem */
300 at91_gpio_init(at91sam9rl_gpio, 4);
301 }
302
303 /* --------------------------------------------------------------------
304 * Interrupt initialization
305 * -------------------------------------------------------------------- */
306
307 /*
308 * The default interrupt priority levels (0 = lowest, 7 = highest).
309 */
310 static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
311 7, /* Advanced Interrupt Controller */
312 7, /* System Peripherals */
313 1, /* Parallel IO Controller A */
314 1, /* Parallel IO Controller B */
315 1, /* Parallel IO Controller C */
316 1, /* Parallel IO Controller D */
317 5, /* USART 0 */
318 5, /* USART 1 */
319 5, /* USART 2 */
320 5, /* USART 3 */
321 0, /* Multimedia Card Interface */
322 6, /* Two-Wire Interface 0 */
323 6, /* Two-Wire Interface 1 */
324 5, /* Serial Peripheral Interface */
325 4, /* Serial Synchronous Controller 0 */
326 4, /* Serial Synchronous Controller 1 */
327 0, /* Timer Counter 0 */
328 0, /* Timer Counter 1 */
329 0, /* Timer Counter 2 */
330 0,
331 0, /* Touch Screen Controller */
332 0, /* DMA Controller */
333 2, /* USB Device High speed port */
334 2, /* LCD Controller */
335 6, /* AC97 Controller */
336 0,
337 0,
338 0,
339 0,
340 0,
341 0,
342 0, /* Advanced Interrupt Controller */
343 };
344
345 struct at91_init_soc __initdata at91sam9rl_soc = {
346 .map_io = at91sam9rl_map_io,
347 .default_irq_priority = at91sam9rl_default_irq_priority,
348 .ioremap_registers = at91sam9rl_ioremap_registers,
349 .register_clocks = at91sam9rl_register_clocks,
350 .init = at91sam9rl_initialize,
351 };
352