1 /*
2 * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
3 *
4 * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
5 * Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
6 * Converted to ClockSource/ClockEvents by David Brownell.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/kernel.h>
15 #include <linux/clk.h>
16 #include <linux/clockchips.h>
17
18 #include <asm/mach/time.h>
19
20 #include <mach/at91_pit.h>
21
22
23 #define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
24 #define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
25
26 static u32 pit_cycle; /* write-once */
27 static u32 pit_cnt; /* access only w/system irq blocked */
28 static void __iomem *pit_base_addr __read_mostly;
29
pit_read(unsigned int reg_offset)30 static inline unsigned int pit_read(unsigned int reg_offset)
31 {
32 return __raw_readl(pit_base_addr + reg_offset);
33 }
34
pit_write(unsigned int reg_offset,unsigned long value)35 static inline void pit_write(unsigned int reg_offset, unsigned long value)
36 {
37 __raw_writel(value, pit_base_addr + reg_offset);
38 }
39
40 /*
41 * Clocksource: just a monotonic counter of MCK/16 cycles.
42 * We don't care whether or not PIT irqs are enabled.
43 */
read_pit_clk(struct clocksource * cs)44 static cycle_t read_pit_clk(struct clocksource *cs)
45 {
46 unsigned long flags;
47 u32 elapsed;
48 u32 t;
49
50 raw_local_irq_save(flags);
51 elapsed = pit_cnt;
52 t = pit_read(AT91_PIT_PIIR);
53 raw_local_irq_restore(flags);
54
55 elapsed += PIT_PICNT(t) * pit_cycle;
56 elapsed += PIT_CPIV(t);
57 return elapsed;
58 }
59
60 static struct clocksource pit_clk = {
61 .name = "pit",
62 .rating = 175,
63 .read = read_pit_clk,
64 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
65 };
66
67
68 /*
69 * Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16)
70 */
71 static void
pit_clkevt_mode(enum clock_event_mode mode,struct clock_event_device * dev)72 pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
73 {
74 switch (mode) {
75 case CLOCK_EVT_MODE_PERIODIC:
76 /* update clocksource counter */
77 pit_cnt += pit_cycle * PIT_PICNT(pit_read(AT91_PIT_PIVR));
78 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
79 | AT91_PIT_PITIEN);
80 break;
81 case CLOCK_EVT_MODE_ONESHOT:
82 BUG();
83 /* FALLTHROUGH */
84 case CLOCK_EVT_MODE_SHUTDOWN:
85 case CLOCK_EVT_MODE_UNUSED:
86 /* disable irq, leaving the clocksource active */
87 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
88 break;
89 case CLOCK_EVT_MODE_RESUME:
90 break;
91 }
92 }
93
94 static struct clock_event_device pit_clkevt = {
95 .name = "pit",
96 .features = CLOCK_EVT_FEAT_PERIODIC,
97 .shift = 32,
98 .rating = 100,
99 .set_mode = pit_clkevt_mode,
100 };
101
102
103 /*
104 * IRQ handler for the timer.
105 */
at91sam926x_pit_interrupt(int irq,void * dev_id)106 static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
107 {
108 /*
109 * irqs should be disabled here, but as the irq is shared they are only
110 * guaranteed to be off if the timer irq is registered first.
111 */
112 WARN_ON_ONCE(!irqs_disabled());
113
114 /* The PIT interrupt may be disabled, and is shared */
115 if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC)
116 && (pit_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
117 unsigned nr_ticks;
118
119 /* Get number of ticks performed before irq, and ack it */
120 nr_ticks = PIT_PICNT(pit_read(AT91_PIT_PIVR));
121 do {
122 pit_cnt += pit_cycle;
123 pit_clkevt.event_handler(&pit_clkevt);
124 nr_ticks--;
125 } while (nr_ticks);
126
127 return IRQ_HANDLED;
128 }
129
130 return IRQ_NONE;
131 }
132
133 static struct irqaction at91sam926x_pit_irq = {
134 .name = "at91_tick",
135 .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
136 .handler = at91sam926x_pit_interrupt
137 };
138
at91sam926x_pit_reset(void)139 static void at91sam926x_pit_reset(void)
140 {
141 /* Disable timer and irqs */
142 pit_write(AT91_PIT_MR, 0);
143
144 /* Clear any pending interrupts, wait for PIT to stop counting */
145 while (PIT_CPIV(pit_read(AT91_PIT_PIVR)) != 0)
146 cpu_relax();
147
148 /* Start PIT but don't enable IRQ */
149 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
150 }
151
152 /*
153 * Set up both clocksource and clockevent support.
154 */
at91sam926x_pit_init(void)155 static void __init at91sam926x_pit_init(void)
156 {
157 unsigned long pit_rate;
158 unsigned bits;
159
160 /*
161 * Use our actual MCK to figure out how many MCK/16 ticks per
162 * 1/HZ period (instead of a compile-time constant LATCH).
163 */
164 pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
165 pit_cycle = (pit_rate + HZ/2) / HZ;
166 WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
167
168 /* Initialize and enable the timer */
169 at91sam926x_pit_reset();
170
171 /*
172 * Register clocksource. The high order bits of PIV are unused,
173 * so this isn't a 32-bit counter unless we get clockevent irqs.
174 */
175 bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
176 pit_clk.mask = CLOCKSOURCE_MASK(bits);
177 clocksource_register_hz(&pit_clk, pit_rate);
178
179 /* Set up irq handler */
180 setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
181
182 /* Set up and register clockevents */
183 pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
184 pit_clkevt.cpumask = cpumask_of(0);
185 clockevents_register_device(&pit_clkevt);
186 }
187
at91sam926x_pit_suspend(void)188 static void at91sam926x_pit_suspend(void)
189 {
190 /* Disable timer */
191 pit_write(AT91_PIT_MR, 0);
192 }
193
at91sam926x_ioremap_pit(u32 addr)194 void __init at91sam926x_ioremap_pit(u32 addr)
195 {
196 pit_base_addr = ioremap(addr, 16);
197
198 if (!pit_base_addr)
199 panic("Impossible to ioremap PIT\n");
200 }
201
202 struct sys_timer at91sam926x_timer = {
203 .init = at91sam926x_pit_init,
204 .suspend = at91sam926x_pit_suspend,
205 .resume = at91sam926x_pit_reset,
206 };
207