1 /*
2 * arch/arm/mach-at91/at91sam9263.c
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13 #include <linux/module.h>
14
15 #include <asm/irq.h>
16 #include <asm/mach/arch.h>
17 #include <asm/mach/map.h>
18 #include <mach/at91sam9263.h>
19 #include <mach/at91_pmc.h>
20 #include <mach/at91_rstc.h>
21
22 #include "soc.h"
23 #include "generic.h"
24 #include "clock.h"
25 #include "sam9_smc.h"
26
27 /* --------------------------------------------------------------------
28 * Clocks
29 * -------------------------------------------------------------------- */
30
31 /*
32 * The peripheral clocks.
33 */
34 static struct clk pioA_clk = {
35 .name = "pioA_clk",
36 .pmc_mask = 1 << AT91SAM9263_ID_PIOA,
37 .type = CLK_TYPE_PERIPHERAL,
38 };
39 static struct clk pioB_clk = {
40 .name = "pioB_clk",
41 .pmc_mask = 1 << AT91SAM9263_ID_PIOB,
42 .type = CLK_TYPE_PERIPHERAL,
43 };
44 static struct clk pioCDE_clk = {
45 .name = "pioCDE_clk",
46 .pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
47 .type = CLK_TYPE_PERIPHERAL,
48 };
49 static struct clk usart0_clk = {
50 .name = "usart0_clk",
51 .pmc_mask = 1 << AT91SAM9263_ID_US0,
52 .type = CLK_TYPE_PERIPHERAL,
53 };
54 static struct clk usart1_clk = {
55 .name = "usart1_clk",
56 .pmc_mask = 1 << AT91SAM9263_ID_US1,
57 .type = CLK_TYPE_PERIPHERAL,
58 };
59 static struct clk usart2_clk = {
60 .name = "usart2_clk",
61 .pmc_mask = 1 << AT91SAM9263_ID_US2,
62 .type = CLK_TYPE_PERIPHERAL,
63 };
64 static struct clk mmc0_clk = {
65 .name = "mci0_clk",
66 .pmc_mask = 1 << AT91SAM9263_ID_MCI0,
67 .type = CLK_TYPE_PERIPHERAL,
68 };
69 static struct clk mmc1_clk = {
70 .name = "mci1_clk",
71 .pmc_mask = 1 << AT91SAM9263_ID_MCI1,
72 .type = CLK_TYPE_PERIPHERAL,
73 };
74 static struct clk can_clk = {
75 .name = "can_clk",
76 .pmc_mask = 1 << AT91SAM9263_ID_CAN,
77 .type = CLK_TYPE_PERIPHERAL,
78 };
79 static struct clk twi_clk = {
80 .name = "twi_clk",
81 .pmc_mask = 1 << AT91SAM9263_ID_TWI,
82 .type = CLK_TYPE_PERIPHERAL,
83 };
84 static struct clk spi0_clk = {
85 .name = "spi0_clk",
86 .pmc_mask = 1 << AT91SAM9263_ID_SPI0,
87 .type = CLK_TYPE_PERIPHERAL,
88 };
89 static struct clk spi1_clk = {
90 .name = "spi1_clk",
91 .pmc_mask = 1 << AT91SAM9263_ID_SPI1,
92 .type = CLK_TYPE_PERIPHERAL,
93 };
94 static struct clk ssc0_clk = {
95 .name = "ssc0_clk",
96 .pmc_mask = 1 << AT91SAM9263_ID_SSC0,
97 .type = CLK_TYPE_PERIPHERAL,
98 };
99 static struct clk ssc1_clk = {
100 .name = "ssc1_clk",
101 .pmc_mask = 1 << AT91SAM9263_ID_SSC1,
102 .type = CLK_TYPE_PERIPHERAL,
103 };
104 static struct clk ac97_clk = {
105 .name = "ac97_clk",
106 .pmc_mask = 1 << AT91SAM9263_ID_AC97C,
107 .type = CLK_TYPE_PERIPHERAL,
108 };
109 static struct clk tcb_clk = {
110 .name = "tcb_clk",
111 .pmc_mask = 1 << AT91SAM9263_ID_TCB,
112 .type = CLK_TYPE_PERIPHERAL,
113 };
114 static struct clk pwm_clk = {
115 .name = "pwm_clk",
116 .pmc_mask = 1 << AT91SAM9263_ID_PWMC,
117 .type = CLK_TYPE_PERIPHERAL,
118 };
119 static struct clk macb_clk = {
120 .name = "pclk",
121 .pmc_mask = 1 << AT91SAM9263_ID_EMAC,
122 .type = CLK_TYPE_PERIPHERAL,
123 };
124 static struct clk dma_clk = {
125 .name = "dma_clk",
126 .pmc_mask = 1 << AT91SAM9263_ID_DMA,
127 .type = CLK_TYPE_PERIPHERAL,
128 };
129 static struct clk twodge_clk = {
130 .name = "2dge_clk",
131 .pmc_mask = 1 << AT91SAM9263_ID_2DGE,
132 .type = CLK_TYPE_PERIPHERAL,
133 };
134 static struct clk udc_clk = {
135 .name = "udc_clk",
136 .pmc_mask = 1 << AT91SAM9263_ID_UDP,
137 .type = CLK_TYPE_PERIPHERAL,
138 };
139 static struct clk isi_clk = {
140 .name = "isi_clk",
141 .pmc_mask = 1 << AT91SAM9263_ID_ISI,
142 .type = CLK_TYPE_PERIPHERAL,
143 };
144 static struct clk lcdc_clk = {
145 .name = "lcdc_clk",
146 .pmc_mask = 1 << AT91SAM9263_ID_LCDC,
147 .type = CLK_TYPE_PERIPHERAL,
148 };
149 static struct clk ohci_clk = {
150 .name = "ohci_clk",
151 .pmc_mask = 1 << AT91SAM9263_ID_UHP,
152 .type = CLK_TYPE_PERIPHERAL,
153 };
154
155 static struct clk *periph_clocks[] __initdata = {
156 &pioA_clk,
157 &pioB_clk,
158 &pioCDE_clk,
159 &usart0_clk,
160 &usart1_clk,
161 &usart2_clk,
162 &mmc0_clk,
163 &mmc1_clk,
164 &can_clk,
165 &twi_clk,
166 &spi0_clk,
167 &spi1_clk,
168 &ssc0_clk,
169 &ssc1_clk,
170 &ac97_clk,
171 &tcb_clk,
172 &pwm_clk,
173 &macb_clk,
174 &twodge_clk,
175 &udc_clk,
176 &isi_clk,
177 &lcdc_clk,
178 &dma_clk,
179 &ohci_clk,
180 // irq0 .. irq1
181 };
182
183 static struct clk_lookup periph_clocks_lookups[] = {
184 /* One additional fake clock for macb_hclk */
185 CLKDEV_CON_ID("hclk", &macb_clk),
186 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
187 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
188 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
189 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
190 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
191 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
192 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
193 /* fake hclk clock */
194 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
195 CLKDEV_CON_ID("pioA", &pioA_clk),
196 CLKDEV_CON_ID("pioB", &pioB_clk),
197 CLKDEV_CON_ID("pioC", &pioCDE_clk),
198 CLKDEV_CON_ID("pioD", &pioCDE_clk),
199 CLKDEV_CON_ID("pioE", &pioCDE_clk),
200 };
201
202 static struct clk_lookup usart_clocks_lookups[] = {
203 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
204 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
205 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
206 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
207 };
208
209 /*
210 * The four programmable clocks.
211 * You must configure pin multiplexing to bring these signals out.
212 */
213 static struct clk pck0 = {
214 .name = "pck0",
215 .pmc_mask = AT91_PMC_PCK0,
216 .type = CLK_TYPE_PROGRAMMABLE,
217 .id = 0,
218 };
219 static struct clk pck1 = {
220 .name = "pck1",
221 .pmc_mask = AT91_PMC_PCK1,
222 .type = CLK_TYPE_PROGRAMMABLE,
223 .id = 1,
224 };
225 static struct clk pck2 = {
226 .name = "pck2",
227 .pmc_mask = AT91_PMC_PCK2,
228 .type = CLK_TYPE_PROGRAMMABLE,
229 .id = 2,
230 };
231 static struct clk pck3 = {
232 .name = "pck3",
233 .pmc_mask = AT91_PMC_PCK3,
234 .type = CLK_TYPE_PROGRAMMABLE,
235 .id = 3,
236 };
237
at91sam9263_register_clocks(void)238 static void __init at91sam9263_register_clocks(void)
239 {
240 int i;
241
242 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
243 clk_register(periph_clocks[i]);
244
245 clkdev_add_table(periph_clocks_lookups,
246 ARRAY_SIZE(periph_clocks_lookups));
247 clkdev_add_table(usart_clocks_lookups,
248 ARRAY_SIZE(usart_clocks_lookups));
249
250 clk_register(&pck0);
251 clk_register(&pck1);
252 clk_register(&pck2);
253 clk_register(&pck3);
254 }
255
256 static struct clk_lookup console_clock_lookup;
257
at91sam9263_set_console_clock(int id)258 void __init at91sam9263_set_console_clock(int id)
259 {
260 if (id >= ARRAY_SIZE(usart_clocks_lookups))
261 return;
262
263 console_clock_lookup.con_id = "usart";
264 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
265 clkdev_add(&console_clock_lookup);
266 }
267
268 /* --------------------------------------------------------------------
269 * GPIO
270 * -------------------------------------------------------------------- */
271
272 static struct at91_gpio_bank at91sam9263_gpio[] __initdata = {
273 {
274 .id = AT91SAM9263_ID_PIOA,
275 .regbase = AT91SAM9263_BASE_PIOA,
276 }, {
277 .id = AT91SAM9263_ID_PIOB,
278 .regbase = AT91SAM9263_BASE_PIOB,
279 }, {
280 .id = AT91SAM9263_ID_PIOCDE,
281 .regbase = AT91SAM9263_BASE_PIOC,
282 }, {
283 .id = AT91SAM9263_ID_PIOCDE,
284 .regbase = AT91SAM9263_BASE_PIOD,
285 }, {
286 .id = AT91SAM9263_ID_PIOCDE,
287 .regbase = AT91SAM9263_BASE_PIOE,
288 }
289 };
290
291 /* --------------------------------------------------------------------
292 * AT91SAM9263 processor initialization
293 * -------------------------------------------------------------------- */
294
at91sam9263_map_io(void)295 static void __init at91sam9263_map_io(void)
296 {
297 at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE);
298 at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
299 }
300
at91sam9263_ioremap_registers(void)301 static void __init at91sam9263_ioremap_registers(void)
302 {
303 at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
304 at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
305 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
306 at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
307 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
308 }
309
at91sam9263_initialize(void)310 static void __init at91sam9263_initialize(void)
311 {
312 arm_pm_restart = at91sam9_alt_restart;
313 at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
314
315 /* Register GPIO subsystem */
316 at91_gpio_init(at91sam9263_gpio, 5);
317 }
318
319 /* --------------------------------------------------------------------
320 * Interrupt initialization
321 * -------------------------------------------------------------------- */
322
323 /*
324 * The default interrupt priority levels (0 = lowest, 7 = highest).
325 */
326 static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
327 7, /* Advanced Interrupt Controller (FIQ) */
328 7, /* System Peripherals */
329 1, /* Parallel IO Controller A */
330 1, /* Parallel IO Controller B */
331 1, /* Parallel IO Controller C, D and E */
332 0,
333 0,
334 5, /* USART 0 */
335 5, /* USART 1 */
336 5, /* USART 2 */
337 0, /* Multimedia Card Interface 0 */
338 0, /* Multimedia Card Interface 1 */
339 3, /* CAN */
340 6, /* Two-Wire Interface */
341 5, /* Serial Peripheral Interface 0 */
342 5, /* Serial Peripheral Interface 1 */
343 4, /* Serial Synchronous Controller 0 */
344 4, /* Serial Synchronous Controller 1 */
345 5, /* AC97 Controller */
346 0, /* Timer Counter 0, 1 and 2 */
347 0, /* Pulse Width Modulation Controller */
348 3, /* Ethernet */
349 0,
350 0, /* 2D Graphic Engine */
351 2, /* USB Device Port */
352 0, /* Image Sensor Interface */
353 3, /* LDC Controller */
354 0, /* DMA Controller */
355 0,
356 2, /* USB Host port */
357 0, /* Advanced Interrupt Controller (IRQ0) */
358 0, /* Advanced Interrupt Controller (IRQ1) */
359 };
360
361 struct at91_init_soc __initdata at91sam9263_soc = {
362 .map_io = at91sam9263_map_io,
363 .default_irq_priority = at91sam9263_default_irq_priority,
364 .ioremap_registers = at91sam9263_ioremap_registers,
365 .register_clocks = at91sam9263_register_clocks,
366 .init = at91sam9263_initialize,
367 };
368