1 /*
2 * arch/arm/mach-at91/at91sam9261.c
3 *
4 * Copyright (C) 2005 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13 #include <linux/module.h>
14
15 #include <asm/irq.h>
16 #include <asm/mach/arch.h>
17 #include <asm/mach/map.h>
18 #include <mach/cpu.h>
19 #include <mach/at91sam9261.h>
20 #include <mach/at91_pmc.h>
21 #include <mach/at91_rstc.h>
22
23 #include "soc.h"
24 #include "generic.h"
25 #include "clock.h"
26 #include "sam9_smc.h"
27
28 /* --------------------------------------------------------------------
29 * Clocks
30 * -------------------------------------------------------------------- */
31
32 /*
33 * The peripheral clocks.
34 */
35 static struct clk pioA_clk = {
36 .name = "pioA_clk",
37 .pmc_mask = 1 << AT91SAM9261_ID_PIOA,
38 .type = CLK_TYPE_PERIPHERAL,
39 };
40 static struct clk pioB_clk = {
41 .name = "pioB_clk",
42 .pmc_mask = 1 << AT91SAM9261_ID_PIOB,
43 .type = CLK_TYPE_PERIPHERAL,
44 };
45 static struct clk pioC_clk = {
46 .name = "pioC_clk",
47 .pmc_mask = 1 << AT91SAM9261_ID_PIOC,
48 .type = CLK_TYPE_PERIPHERAL,
49 };
50 static struct clk usart0_clk = {
51 .name = "usart0_clk",
52 .pmc_mask = 1 << AT91SAM9261_ID_US0,
53 .type = CLK_TYPE_PERIPHERAL,
54 };
55 static struct clk usart1_clk = {
56 .name = "usart1_clk",
57 .pmc_mask = 1 << AT91SAM9261_ID_US1,
58 .type = CLK_TYPE_PERIPHERAL,
59 };
60 static struct clk usart2_clk = {
61 .name = "usart2_clk",
62 .pmc_mask = 1 << AT91SAM9261_ID_US2,
63 .type = CLK_TYPE_PERIPHERAL,
64 };
65 static struct clk mmc_clk = {
66 .name = "mci_clk",
67 .pmc_mask = 1 << AT91SAM9261_ID_MCI,
68 .type = CLK_TYPE_PERIPHERAL,
69 };
70 static struct clk udc_clk = {
71 .name = "udc_clk",
72 .pmc_mask = 1 << AT91SAM9261_ID_UDP,
73 .type = CLK_TYPE_PERIPHERAL,
74 };
75 static struct clk twi_clk = {
76 .name = "twi_clk",
77 .pmc_mask = 1 << AT91SAM9261_ID_TWI,
78 .type = CLK_TYPE_PERIPHERAL,
79 };
80 static struct clk spi0_clk = {
81 .name = "spi0_clk",
82 .pmc_mask = 1 << AT91SAM9261_ID_SPI0,
83 .type = CLK_TYPE_PERIPHERAL,
84 };
85 static struct clk spi1_clk = {
86 .name = "spi1_clk",
87 .pmc_mask = 1 << AT91SAM9261_ID_SPI1,
88 .type = CLK_TYPE_PERIPHERAL,
89 };
90 static struct clk ssc0_clk = {
91 .name = "ssc0_clk",
92 .pmc_mask = 1 << AT91SAM9261_ID_SSC0,
93 .type = CLK_TYPE_PERIPHERAL,
94 };
95 static struct clk ssc1_clk = {
96 .name = "ssc1_clk",
97 .pmc_mask = 1 << AT91SAM9261_ID_SSC1,
98 .type = CLK_TYPE_PERIPHERAL,
99 };
100 static struct clk ssc2_clk = {
101 .name = "ssc2_clk",
102 .pmc_mask = 1 << AT91SAM9261_ID_SSC2,
103 .type = CLK_TYPE_PERIPHERAL,
104 };
105 static struct clk tc0_clk = {
106 .name = "tc0_clk",
107 .pmc_mask = 1 << AT91SAM9261_ID_TC0,
108 .type = CLK_TYPE_PERIPHERAL,
109 };
110 static struct clk tc1_clk = {
111 .name = "tc1_clk",
112 .pmc_mask = 1 << AT91SAM9261_ID_TC1,
113 .type = CLK_TYPE_PERIPHERAL,
114 };
115 static struct clk tc2_clk = {
116 .name = "tc2_clk",
117 .pmc_mask = 1 << AT91SAM9261_ID_TC2,
118 .type = CLK_TYPE_PERIPHERAL,
119 };
120 static struct clk ohci_clk = {
121 .name = "ohci_clk",
122 .pmc_mask = 1 << AT91SAM9261_ID_UHP,
123 .type = CLK_TYPE_PERIPHERAL,
124 };
125 static struct clk lcdc_clk = {
126 .name = "lcdc_clk",
127 .pmc_mask = 1 << AT91SAM9261_ID_LCDC,
128 .type = CLK_TYPE_PERIPHERAL,
129 };
130
131 /* HClocks */
132 static struct clk hck0 = {
133 .name = "hck0",
134 .pmc_mask = AT91_PMC_HCK0,
135 .type = CLK_TYPE_SYSTEM,
136 .id = 0,
137 };
138 static struct clk hck1 = {
139 .name = "hck1",
140 .pmc_mask = AT91_PMC_HCK1,
141 .type = CLK_TYPE_SYSTEM,
142 .id = 1,
143 };
144
145 static struct clk *periph_clocks[] __initdata = {
146 &pioA_clk,
147 &pioB_clk,
148 &pioC_clk,
149 &usart0_clk,
150 &usart1_clk,
151 &usart2_clk,
152 &mmc_clk,
153 &udc_clk,
154 &twi_clk,
155 &spi0_clk,
156 &spi1_clk,
157 &ssc0_clk,
158 &ssc1_clk,
159 &ssc2_clk,
160 &tc0_clk,
161 &tc1_clk,
162 &tc2_clk,
163 &ohci_clk,
164 &lcdc_clk,
165 // irq0 .. irq2
166 };
167
168 static struct clk_lookup periph_clocks_lookups[] = {
169 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
170 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
171 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
172 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
173 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
174 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
175 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
176 CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
177 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
178 CLKDEV_CON_ID("pioA", &pioA_clk),
179 CLKDEV_CON_ID("pioB", &pioB_clk),
180 CLKDEV_CON_ID("pioC", &pioC_clk),
181 };
182
183 static struct clk_lookup usart_clocks_lookups[] = {
184 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
185 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
186 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
187 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
188 };
189
190 /*
191 * The four programmable clocks.
192 * You must configure pin multiplexing to bring these signals out.
193 */
194 static struct clk pck0 = {
195 .name = "pck0",
196 .pmc_mask = AT91_PMC_PCK0,
197 .type = CLK_TYPE_PROGRAMMABLE,
198 .id = 0,
199 };
200 static struct clk pck1 = {
201 .name = "pck1",
202 .pmc_mask = AT91_PMC_PCK1,
203 .type = CLK_TYPE_PROGRAMMABLE,
204 .id = 1,
205 };
206 static struct clk pck2 = {
207 .name = "pck2",
208 .pmc_mask = AT91_PMC_PCK2,
209 .type = CLK_TYPE_PROGRAMMABLE,
210 .id = 2,
211 };
212 static struct clk pck3 = {
213 .name = "pck3",
214 .pmc_mask = AT91_PMC_PCK3,
215 .type = CLK_TYPE_PROGRAMMABLE,
216 .id = 3,
217 };
218
at91sam9261_register_clocks(void)219 static void __init at91sam9261_register_clocks(void)
220 {
221 int i;
222
223 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
224 clk_register(periph_clocks[i]);
225
226 clkdev_add_table(periph_clocks_lookups,
227 ARRAY_SIZE(periph_clocks_lookups));
228 clkdev_add_table(usart_clocks_lookups,
229 ARRAY_SIZE(usart_clocks_lookups));
230
231 clk_register(&pck0);
232 clk_register(&pck1);
233 clk_register(&pck2);
234 clk_register(&pck3);
235
236 clk_register(&hck0);
237 clk_register(&hck1);
238 }
239
240 static struct clk_lookup console_clock_lookup;
241
at91sam9261_set_console_clock(int id)242 void __init at91sam9261_set_console_clock(int id)
243 {
244 if (id >= ARRAY_SIZE(usart_clocks_lookups))
245 return;
246
247 console_clock_lookup.con_id = "usart";
248 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
249 clkdev_add(&console_clock_lookup);
250 }
251
252 /* --------------------------------------------------------------------
253 * GPIO
254 * -------------------------------------------------------------------- */
255
256 static struct at91_gpio_bank at91sam9261_gpio[] __initdata = {
257 {
258 .id = AT91SAM9261_ID_PIOA,
259 .regbase = AT91SAM9261_BASE_PIOA,
260 }, {
261 .id = AT91SAM9261_ID_PIOB,
262 .regbase = AT91SAM9261_BASE_PIOB,
263 }, {
264 .id = AT91SAM9261_ID_PIOC,
265 .regbase = AT91SAM9261_BASE_PIOC,
266 }
267 };
268
269 /* --------------------------------------------------------------------
270 * AT91SAM9261 processor initialization
271 * -------------------------------------------------------------------- */
272
at91sam9261_map_io(void)273 static void __init at91sam9261_map_io(void)
274 {
275 if (cpu_is_at91sam9g10())
276 at91_init_sram(0, AT91SAM9G10_SRAM_BASE, AT91SAM9G10_SRAM_SIZE);
277 else
278 at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
279 }
280
at91sam9261_ioremap_registers(void)281 static void __init at91sam9261_ioremap_registers(void)
282 {
283 at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
284 at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
285 at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
286 at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
287 }
288
at91sam9261_initialize(void)289 static void __init at91sam9261_initialize(void)
290 {
291 arm_pm_restart = at91sam9_alt_restart;
292 at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
293 | (1 << AT91SAM9261_ID_IRQ2);
294
295 /* Register GPIO subsystem */
296 at91_gpio_init(at91sam9261_gpio, 3);
297 }
298
299 /* --------------------------------------------------------------------
300 * Interrupt initialization
301 * -------------------------------------------------------------------- */
302
303 /*
304 * The default interrupt priority levels (0 = lowest, 7 = highest).
305 */
306 static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
307 7, /* Advanced Interrupt Controller */
308 7, /* System Peripherals */
309 1, /* Parallel IO Controller A */
310 1, /* Parallel IO Controller B */
311 1, /* Parallel IO Controller C */
312 0,
313 5, /* USART 0 */
314 5, /* USART 1 */
315 5, /* USART 2 */
316 0, /* Multimedia Card Interface */
317 2, /* USB Device Port */
318 6, /* Two-Wire Interface */
319 5, /* Serial Peripheral Interface 0 */
320 5, /* Serial Peripheral Interface 1 */
321 4, /* Serial Synchronous Controller 0 */
322 4, /* Serial Synchronous Controller 1 */
323 4, /* Serial Synchronous Controller 2 */
324 0, /* Timer Counter 0 */
325 0, /* Timer Counter 1 */
326 0, /* Timer Counter 2 */
327 2, /* USB Host port */
328 3, /* LCD Controller */
329 0,
330 0,
331 0,
332 0,
333 0,
334 0,
335 0,
336 0, /* Advanced Interrupt Controller */
337 0, /* Advanced Interrupt Controller */
338 0, /* Advanced Interrupt Controller */
339 };
340
341 struct at91_init_soc __initdata at91sam9261_soc = {
342 .map_io = at91sam9261_map_io,
343 .default_irq_priority = at91sam9261_default_irq_priority,
344 .ioremap_registers = at91sam9261_ioremap_registers,
345 .register_clocks = at91sam9261_register_clocks,
346 .init = at91sam9261_initialize,
347 };
348