1 /*
2 * arch/arm/mach-at91/at91sam9260.c
3 *
4 * Copyright (C) 2006 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13 #include <linux/module.h>
14
15 #include <asm/irq.h>
16 #include <asm/mach/arch.h>
17 #include <asm/mach/map.h>
18 #include <mach/cpu.h>
19 #include <mach/at91_dbgu.h>
20 #include <mach/at91sam9260.h>
21 #include <mach/at91_pmc.h>
22 #include <mach/at91_rstc.h>
23
24 #include "soc.h"
25 #include "generic.h"
26 #include "clock.h"
27 #include "sam9_smc.h"
28
29 /* --------------------------------------------------------------------
30 * Clocks
31 * -------------------------------------------------------------------- */
32
33 /*
34 * The peripheral clocks.
35 */
36 static struct clk pioA_clk = {
37 .name = "pioA_clk",
38 .pmc_mask = 1 << AT91SAM9260_ID_PIOA,
39 .type = CLK_TYPE_PERIPHERAL,
40 };
41 static struct clk pioB_clk = {
42 .name = "pioB_clk",
43 .pmc_mask = 1 << AT91SAM9260_ID_PIOB,
44 .type = CLK_TYPE_PERIPHERAL,
45 };
46 static struct clk pioC_clk = {
47 .name = "pioC_clk",
48 .pmc_mask = 1 << AT91SAM9260_ID_PIOC,
49 .type = CLK_TYPE_PERIPHERAL,
50 };
51 static struct clk adc_clk = {
52 .name = "adc_clk",
53 .pmc_mask = 1 << AT91SAM9260_ID_ADC,
54 .type = CLK_TYPE_PERIPHERAL,
55 };
56 static struct clk usart0_clk = {
57 .name = "usart0_clk",
58 .pmc_mask = 1 << AT91SAM9260_ID_US0,
59 .type = CLK_TYPE_PERIPHERAL,
60 };
61 static struct clk usart1_clk = {
62 .name = "usart1_clk",
63 .pmc_mask = 1 << AT91SAM9260_ID_US1,
64 .type = CLK_TYPE_PERIPHERAL,
65 };
66 static struct clk usart2_clk = {
67 .name = "usart2_clk",
68 .pmc_mask = 1 << AT91SAM9260_ID_US2,
69 .type = CLK_TYPE_PERIPHERAL,
70 };
71 static struct clk mmc_clk = {
72 .name = "mci_clk",
73 .pmc_mask = 1 << AT91SAM9260_ID_MCI,
74 .type = CLK_TYPE_PERIPHERAL,
75 };
76 static struct clk udc_clk = {
77 .name = "udc_clk",
78 .pmc_mask = 1 << AT91SAM9260_ID_UDP,
79 .type = CLK_TYPE_PERIPHERAL,
80 };
81 static struct clk twi_clk = {
82 .name = "twi_clk",
83 .pmc_mask = 1 << AT91SAM9260_ID_TWI,
84 .type = CLK_TYPE_PERIPHERAL,
85 };
86 static struct clk spi0_clk = {
87 .name = "spi0_clk",
88 .pmc_mask = 1 << AT91SAM9260_ID_SPI0,
89 .type = CLK_TYPE_PERIPHERAL,
90 };
91 static struct clk spi1_clk = {
92 .name = "spi1_clk",
93 .pmc_mask = 1 << AT91SAM9260_ID_SPI1,
94 .type = CLK_TYPE_PERIPHERAL,
95 };
96 static struct clk ssc_clk = {
97 .name = "ssc_clk",
98 .pmc_mask = 1 << AT91SAM9260_ID_SSC,
99 .type = CLK_TYPE_PERIPHERAL,
100 };
101 static struct clk tc0_clk = {
102 .name = "tc0_clk",
103 .pmc_mask = 1 << AT91SAM9260_ID_TC0,
104 .type = CLK_TYPE_PERIPHERAL,
105 };
106 static struct clk tc1_clk = {
107 .name = "tc1_clk",
108 .pmc_mask = 1 << AT91SAM9260_ID_TC1,
109 .type = CLK_TYPE_PERIPHERAL,
110 };
111 static struct clk tc2_clk = {
112 .name = "tc2_clk",
113 .pmc_mask = 1 << AT91SAM9260_ID_TC2,
114 .type = CLK_TYPE_PERIPHERAL,
115 };
116 static struct clk ohci_clk = {
117 .name = "ohci_clk",
118 .pmc_mask = 1 << AT91SAM9260_ID_UHP,
119 .type = CLK_TYPE_PERIPHERAL,
120 };
121 static struct clk macb_clk = {
122 .name = "pclk",
123 .pmc_mask = 1 << AT91SAM9260_ID_EMAC,
124 .type = CLK_TYPE_PERIPHERAL,
125 };
126 static struct clk isi_clk = {
127 .name = "isi_clk",
128 .pmc_mask = 1 << AT91SAM9260_ID_ISI,
129 .type = CLK_TYPE_PERIPHERAL,
130 };
131 static struct clk usart3_clk = {
132 .name = "usart3_clk",
133 .pmc_mask = 1 << AT91SAM9260_ID_US3,
134 .type = CLK_TYPE_PERIPHERAL,
135 };
136 static struct clk usart4_clk = {
137 .name = "usart4_clk",
138 .pmc_mask = 1 << AT91SAM9260_ID_US4,
139 .type = CLK_TYPE_PERIPHERAL,
140 };
141 static struct clk usart5_clk = {
142 .name = "usart5_clk",
143 .pmc_mask = 1 << AT91SAM9260_ID_US5,
144 .type = CLK_TYPE_PERIPHERAL,
145 };
146 static struct clk tc3_clk = {
147 .name = "tc3_clk",
148 .pmc_mask = 1 << AT91SAM9260_ID_TC3,
149 .type = CLK_TYPE_PERIPHERAL,
150 };
151 static struct clk tc4_clk = {
152 .name = "tc4_clk",
153 .pmc_mask = 1 << AT91SAM9260_ID_TC4,
154 .type = CLK_TYPE_PERIPHERAL,
155 };
156 static struct clk tc5_clk = {
157 .name = "tc5_clk",
158 .pmc_mask = 1 << AT91SAM9260_ID_TC5,
159 .type = CLK_TYPE_PERIPHERAL,
160 };
161
162 static struct clk *periph_clocks[] __initdata = {
163 &pioA_clk,
164 &pioB_clk,
165 &pioC_clk,
166 &adc_clk,
167 &usart0_clk,
168 &usart1_clk,
169 &usart2_clk,
170 &mmc_clk,
171 &udc_clk,
172 &twi_clk,
173 &spi0_clk,
174 &spi1_clk,
175 &ssc_clk,
176 &tc0_clk,
177 &tc1_clk,
178 &tc2_clk,
179 &ohci_clk,
180 &macb_clk,
181 &isi_clk,
182 &usart3_clk,
183 &usart4_clk,
184 &usart5_clk,
185 &tc3_clk,
186 &tc4_clk,
187 &tc5_clk,
188 // irq0 .. irq2
189 };
190
191 static struct clk_lookup periph_clocks_lookups[] = {
192 /* One additional fake clock for macb_hclk */
193 CLKDEV_CON_ID("hclk", &macb_clk),
194 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
195 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
196 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
197 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
198 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
199 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
200 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
201 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
202 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
203 /* more usart lookup table for DT entries */
204 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
205 CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
206 CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
207 CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
208 CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
209 CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
210 CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
211 /* fake hclk clock */
212 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
213 CLKDEV_CON_ID("pioA", &pioA_clk),
214 CLKDEV_CON_ID("pioB", &pioB_clk),
215 CLKDEV_CON_ID("pioC", &pioC_clk),
216 };
217
218 static struct clk_lookup usart_clocks_lookups[] = {
219 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
220 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
221 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
222 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
223 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
224 CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
225 CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
226 };
227
228 /*
229 * The two programmable clocks.
230 * You must configure pin multiplexing to bring these signals out.
231 */
232 static struct clk pck0 = {
233 .name = "pck0",
234 .pmc_mask = AT91_PMC_PCK0,
235 .type = CLK_TYPE_PROGRAMMABLE,
236 .id = 0,
237 };
238 static struct clk pck1 = {
239 .name = "pck1",
240 .pmc_mask = AT91_PMC_PCK1,
241 .type = CLK_TYPE_PROGRAMMABLE,
242 .id = 1,
243 };
244
at91sam9260_register_clocks(void)245 static void __init at91sam9260_register_clocks(void)
246 {
247 int i;
248
249 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
250 clk_register(periph_clocks[i]);
251
252 clkdev_add_table(periph_clocks_lookups,
253 ARRAY_SIZE(periph_clocks_lookups));
254 clkdev_add_table(usart_clocks_lookups,
255 ARRAY_SIZE(usart_clocks_lookups));
256
257 clk_register(&pck0);
258 clk_register(&pck1);
259 }
260
261 static struct clk_lookup console_clock_lookup;
262
at91sam9260_set_console_clock(int id)263 void __init at91sam9260_set_console_clock(int id)
264 {
265 if (id >= ARRAY_SIZE(usart_clocks_lookups))
266 return;
267
268 console_clock_lookup.con_id = "usart";
269 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
270 clkdev_add(&console_clock_lookup);
271 }
272
273 /* --------------------------------------------------------------------
274 * GPIO
275 * -------------------------------------------------------------------- */
276
277 static struct at91_gpio_bank at91sam9260_gpio[] __initdata = {
278 {
279 .id = AT91SAM9260_ID_PIOA,
280 .regbase = AT91SAM9260_BASE_PIOA,
281 }, {
282 .id = AT91SAM9260_ID_PIOB,
283 .regbase = AT91SAM9260_BASE_PIOB,
284 }, {
285 .id = AT91SAM9260_ID_PIOC,
286 .regbase = AT91SAM9260_BASE_PIOC,
287 }
288 };
289
290 /* --------------------------------------------------------------------
291 * AT91SAM9260 processor initialization
292 * -------------------------------------------------------------------- */
293
at91sam9xe_map_io(void)294 static void __init at91sam9xe_map_io(void)
295 {
296 unsigned long sram_size;
297
298 switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
299 case AT91_CIDR_SRAMSIZ_32K:
300 sram_size = 2 * SZ_16K;
301 break;
302 case AT91_CIDR_SRAMSIZ_16K:
303 default:
304 sram_size = SZ_16K;
305 }
306
307 at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size);
308 }
309
at91sam9260_map_io(void)310 static void __init at91sam9260_map_io(void)
311 {
312 if (cpu_is_at91sam9xe()) {
313 at91sam9xe_map_io();
314 } else if (cpu_is_at91sam9g20()) {
315 at91_init_sram(0, AT91SAM9G20_SRAM0_BASE, AT91SAM9G20_SRAM0_SIZE);
316 at91_init_sram(1, AT91SAM9G20_SRAM1_BASE, AT91SAM9G20_SRAM1_SIZE);
317 } else {
318 at91_init_sram(0, AT91SAM9260_SRAM0_BASE, AT91SAM9260_SRAM0_SIZE);
319 at91_init_sram(1, AT91SAM9260_SRAM1_BASE, AT91SAM9260_SRAM1_SIZE);
320 }
321 }
322
at91sam9260_ioremap_registers(void)323 static void __init at91sam9260_ioremap_registers(void)
324 {
325 at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
326 at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
327 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
328 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
329 }
330
at91sam9260_initialize(void)331 static void __init at91sam9260_initialize(void)
332 {
333 arm_pm_restart = at91sam9_alt_restart;
334 at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
335 | (1 << AT91SAM9260_ID_IRQ2);
336
337 /* Register GPIO subsystem */
338 at91_gpio_init(at91sam9260_gpio, 3);
339 }
340
341 /* --------------------------------------------------------------------
342 * Interrupt initialization
343 * -------------------------------------------------------------------- */
344
345 /*
346 * The default interrupt priority levels (0 = lowest, 7 = highest).
347 */
348 static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
349 7, /* Advanced Interrupt Controller */
350 7, /* System Peripherals */
351 1, /* Parallel IO Controller A */
352 1, /* Parallel IO Controller B */
353 1, /* Parallel IO Controller C */
354 0, /* Analog-to-Digital Converter */
355 5, /* USART 0 */
356 5, /* USART 1 */
357 5, /* USART 2 */
358 0, /* Multimedia Card Interface */
359 2, /* USB Device Port */
360 6, /* Two-Wire Interface */
361 5, /* Serial Peripheral Interface 0 */
362 5, /* Serial Peripheral Interface 1 */
363 5, /* Serial Synchronous Controller */
364 0,
365 0,
366 0, /* Timer Counter 0 */
367 0, /* Timer Counter 1 */
368 0, /* Timer Counter 2 */
369 2, /* USB Host port */
370 3, /* Ethernet */
371 0, /* Image Sensor Interface */
372 5, /* USART 3 */
373 5, /* USART 4 */
374 5, /* USART 5 */
375 0, /* Timer Counter 3 */
376 0, /* Timer Counter 4 */
377 0, /* Timer Counter 5 */
378 0, /* Advanced Interrupt Controller */
379 0, /* Advanced Interrupt Controller */
380 0, /* Advanced Interrupt Controller */
381 };
382
383 struct at91_init_soc __initdata at91sam9260_soc = {
384 .map_io = at91sam9260_map_io,
385 .default_irq_priority = at91sam9260_default_irq_priority,
386 .ioremap_registers = at91sam9260_ioremap_registers,
387 .register_clocks = at91sam9260_register_clocks,
388 .init = at91sam9260_initialize,
389 };
390