1 /*
2 * arch/arm/mach-at91/at91cap9.c
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2007 Atmel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 */
14
15 #include <linux/module.h>
16
17 #include <asm/irq.h>
18 #include <asm/mach/arch.h>
19 #include <asm/mach/map.h>
20
21 #include <mach/cpu.h>
22 #include <mach/at91cap9.h>
23 #include <mach/at91_pmc.h>
24
25 #include "soc.h"
26 #include "generic.h"
27 #include "clock.h"
28 #include "sam9_smc.h"
29
30 /* --------------------------------------------------------------------
31 * Clocks
32 * -------------------------------------------------------------------- */
33
34 /*
35 * The peripheral clocks.
36 */
37 static struct clk pioABCD_clk = {
38 .name = "pioABCD_clk",
39 .pmc_mask = 1 << AT91CAP9_ID_PIOABCD,
40 .type = CLK_TYPE_PERIPHERAL,
41 };
42 static struct clk mpb0_clk = {
43 .name = "mpb0_clk",
44 .pmc_mask = 1 << AT91CAP9_ID_MPB0,
45 .type = CLK_TYPE_PERIPHERAL,
46 };
47 static struct clk mpb1_clk = {
48 .name = "mpb1_clk",
49 .pmc_mask = 1 << AT91CAP9_ID_MPB1,
50 .type = CLK_TYPE_PERIPHERAL,
51 };
52 static struct clk mpb2_clk = {
53 .name = "mpb2_clk",
54 .pmc_mask = 1 << AT91CAP9_ID_MPB2,
55 .type = CLK_TYPE_PERIPHERAL,
56 };
57 static struct clk mpb3_clk = {
58 .name = "mpb3_clk",
59 .pmc_mask = 1 << AT91CAP9_ID_MPB3,
60 .type = CLK_TYPE_PERIPHERAL,
61 };
62 static struct clk mpb4_clk = {
63 .name = "mpb4_clk",
64 .pmc_mask = 1 << AT91CAP9_ID_MPB4,
65 .type = CLK_TYPE_PERIPHERAL,
66 };
67 static struct clk usart0_clk = {
68 .name = "usart0_clk",
69 .pmc_mask = 1 << AT91CAP9_ID_US0,
70 .type = CLK_TYPE_PERIPHERAL,
71 };
72 static struct clk usart1_clk = {
73 .name = "usart1_clk",
74 .pmc_mask = 1 << AT91CAP9_ID_US1,
75 .type = CLK_TYPE_PERIPHERAL,
76 };
77 static struct clk usart2_clk = {
78 .name = "usart2_clk",
79 .pmc_mask = 1 << AT91CAP9_ID_US2,
80 .type = CLK_TYPE_PERIPHERAL,
81 };
82 static struct clk mmc0_clk = {
83 .name = "mci0_clk",
84 .pmc_mask = 1 << AT91CAP9_ID_MCI0,
85 .type = CLK_TYPE_PERIPHERAL,
86 };
87 static struct clk mmc1_clk = {
88 .name = "mci1_clk",
89 .pmc_mask = 1 << AT91CAP9_ID_MCI1,
90 .type = CLK_TYPE_PERIPHERAL,
91 };
92 static struct clk can_clk = {
93 .name = "can_clk",
94 .pmc_mask = 1 << AT91CAP9_ID_CAN,
95 .type = CLK_TYPE_PERIPHERAL,
96 };
97 static struct clk twi_clk = {
98 .name = "twi_clk",
99 .pmc_mask = 1 << AT91CAP9_ID_TWI,
100 .type = CLK_TYPE_PERIPHERAL,
101 };
102 static struct clk spi0_clk = {
103 .name = "spi0_clk",
104 .pmc_mask = 1 << AT91CAP9_ID_SPI0,
105 .type = CLK_TYPE_PERIPHERAL,
106 };
107 static struct clk spi1_clk = {
108 .name = "spi1_clk",
109 .pmc_mask = 1 << AT91CAP9_ID_SPI1,
110 .type = CLK_TYPE_PERIPHERAL,
111 };
112 static struct clk ssc0_clk = {
113 .name = "ssc0_clk",
114 .pmc_mask = 1 << AT91CAP9_ID_SSC0,
115 .type = CLK_TYPE_PERIPHERAL,
116 };
117 static struct clk ssc1_clk = {
118 .name = "ssc1_clk",
119 .pmc_mask = 1 << AT91CAP9_ID_SSC1,
120 .type = CLK_TYPE_PERIPHERAL,
121 };
122 static struct clk ac97_clk = {
123 .name = "ac97_clk",
124 .pmc_mask = 1 << AT91CAP9_ID_AC97C,
125 .type = CLK_TYPE_PERIPHERAL,
126 };
127 static struct clk tcb_clk = {
128 .name = "tcb_clk",
129 .pmc_mask = 1 << AT91CAP9_ID_TCB,
130 .type = CLK_TYPE_PERIPHERAL,
131 };
132 static struct clk pwm_clk = {
133 .name = "pwm_clk",
134 .pmc_mask = 1 << AT91CAP9_ID_PWMC,
135 .type = CLK_TYPE_PERIPHERAL,
136 };
137 static struct clk macb_clk = {
138 .name = "pclk",
139 .pmc_mask = 1 << AT91CAP9_ID_EMAC,
140 .type = CLK_TYPE_PERIPHERAL,
141 };
142 static struct clk aestdes_clk = {
143 .name = "aestdes_clk",
144 .pmc_mask = 1 << AT91CAP9_ID_AESTDES,
145 .type = CLK_TYPE_PERIPHERAL,
146 };
147 static struct clk adc_clk = {
148 .name = "adc_clk",
149 .pmc_mask = 1 << AT91CAP9_ID_ADC,
150 .type = CLK_TYPE_PERIPHERAL,
151 };
152 static struct clk isi_clk = {
153 .name = "isi_clk",
154 .pmc_mask = 1 << AT91CAP9_ID_ISI,
155 .type = CLK_TYPE_PERIPHERAL,
156 };
157 static struct clk lcdc_clk = {
158 .name = "lcdc_clk",
159 .pmc_mask = 1 << AT91CAP9_ID_LCDC,
160 .type = CLK_TYPE_PERIPHERAL,
161 };
162 static struct clk dma_clk = {
163 .name = "dma_clk",
164 .pmc_mask = 1 << AT91CAP9_ID_DMA,
165 .type = CLK_TYPE_PERIPHERAL,
166 };
167 static struct clk udphs_clk = {
168 .name = "udphs_clk",
169 .pmc_mask = 1 << AT91CAP9_ID_UDPHS,
170 .type = CLK_TYPE_PERIPHERAL,
171 };
172 static struct clk ohci_clk = {
173 .name = "ohci_clk",
174 .pmc_mask = 1 << AT91CAP9_ID_UHP,
175 .type = CLK_TYPE_PERIPHERAL,
176 };
177
178 static struct clk *periph_clocks[] __initdata = {
179 &pioABCD_clk,
180 &mpb0_clk,
181 &mpb1_clk,
182 &mpb2_clk,
183 &mpb3_clk,
184 &mpb4_clk,
185 &usart0_clk,
186 &usart1_clk,
187 &usart2_clk,
188 &mmc0_clk,
189 &mmc1_clk,
190 &can_clk,
191 &twi_clk,
192 &spi0_clk,
193 &spi1_clk,
194 &ssc0_clk,
195 &ssc1_clk,
196 &ac97_clk,
197 &tcb_clk,
198 &pwm_clk,
199 &macb_clk,
200 &aestdes_clk,
201 &adc_clk,
202 &isi_clk,
203 &lcdc_clk,
204 &dma_clk,
205 &udphs_clk,
206 &ohci_clk,
207 // irq0 .. irq1
208 };
209
210 static struct clk_lookup periph_clocks_lookups[] = {
211 /* One additional fake clock for macb_hclk */
212 CLKDEV_CON_ID("hclk", &macb_clk),
213 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
214 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
215 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
216 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
217 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
218 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
219 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
220 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
221 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
222 /* fake hclk clock */
223 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
224 CLKDEV_CON_ID("pioA", &pioABCD_clk),
225 CLKDEV_CON_ID("pioB", &pioABCD_clk),
226 CLKDEV_CON_ID("pioC", &pioABCD_clk),
227 CLKDEV_CON_ID("pioD", &pioABCD_clk),
228 };
229
230 static struct clk_lookup usart_clocks_lookups[] = {
231 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
232 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
233 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
234 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
235 };
236
237 /*
238 * The four programmable clocks.
239 * You must configure pin multiplexing to bring these signals out.
240 */
241 static struct clk pck0 = {
242 .name = "pck0",
243 .pmc_mask = AT91_PMC_PCK0,
244 .type = CLK_TYPE_PROGRAMMABLE,
245 .id = 0,
246 };
247 static struct clk pck1 = {
248 .name = "pck1",
249 .pmc_mask = AT91_PMC_PCK1,
250 .type = CLK_TYPE_PROGRAMMABLE,
251 .id = 1,
252 };
253 static struct clk pck2 = {
254 .name = "pck2",
255 .pmc_mask = AT91_PMC_PCK2,
256 .type = CLK_TYPE_PROGRAMMABLE,
257 .id = 2,
258 };
259 static struct clk pck3 = {
260 .name = "pck3",
261 .pmc_mask = AT91_PMC_PCK3,
262 .type = CLK_TYPE_PROGRAMMABLE,
263 .id = 3,
264 };
265
at91cap9_register_clocks(void)266 static void __init at91cap9_register_clocks(void)
267 {
268 int i;
269
270 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
271 clk_register(periph_clocks[i]);
272
273 clkdev_add_table(periph_clocks_lookups,
274 ARRAY_SIZE(periph_clocks_lookups));
275 clkdev_add_table(usart_clocks_lookups,
276 ARRAY_SIZE(usart_clocks_lookups));
277
278 clk_register(&pck0);
279 clk_register(&pck1);
280 clk_register(&pck2);
281 clk_register(&pck3);
282 }
283
284 static struct clk_lookup console_clock_lookup;
285
at91cap9_set_console_clock(int id)286 void __init at91cap9_set_console_clock(int id)
287 {
288 if (id >= ARRAY_SIZE(usart_clocks_lookups))
289 return;
290
291 console_clock_lookup.con_id = "usart";
292 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
293 clkdev_add(&console_clock_lookup);
294 }
295
296 /* --------------------------------------------------------------------
297 * GPIO
298 * -------------------------------------------------------------------- */
299
300 static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
301 {
302 .id = AT91CAP9_ID_PIOABCD,
303 .regbase = AT91CAP9_BASE_PIOA,
304 }, {
305 .id = AT91CAP9_ID_PIOABCD,
306 .regbase = AT91CAP9_BASE_PIOB,
307 }, {
308 .id = AT91CAP9_ID_PIOABCD,
309 .regbase = AT91CAP9_BASE_PIOC,
310 }, {
311 .id = AT91CAP9_ID_PIOABCD,
312 .regbase = AT91CAP9_BASE_PIOD,
313 }
314 };
315
316 /* --------------------------------------------------------------------
317 * AT91CAP9 processor initialization
318 * -------------------------------------------------------------------- */
319
at91cap9_map_io(void)320 static void __init at91cap9_map_io(void)
321 {
322 at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE);
323 }
324
at91cap9_ioremap_registers(void)325 static void __init at91cap9_ioremap_registers(void)
326 {
327 at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
328 at91_ioremap_rstc(AT91CAP9_BASE_RSTC);
329 at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
330 at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
331 }
332
at91cap9_initialize(void)333 static void __init at91cap9_initialize(void)
334 {
335 arm_pm_restart = at91sam9g45_restart;
336 at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
337
338 /* Register GPIO subsystem */
339 at91_gpio_init(at91cap9_gpio, 4);
340
341 /* Remember the silicon revision */
342 if (cpu_is_at91cap9_revB())
343 system_rev = 0xB;
344 else if (cpu_is_at91cap9_revC())
345 system_rev = 0xC;
346 }
347
348 /* --------------------------------------------------------------------
349 * Interrupt initialization
350 * -------------------------------------------------------------------- */
351
352 /*
353 * The default interrupt priority levels (0 = lowest, 7 = highest).
354 */
355 static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
356 7, /* Advanced Interrupt Controller (FIQ) */
357 7, /* System Peripherals */
358 1, /* Parallel IO Controller A, B, C and D */
359 0, /* MP Block Peripheral 0 */
360 0, /* MP Block Peripheral 1 */
361 0, /* MP Block Peripheral 2 */
362 0, /* MP Block Peripheral 3 */
363 0, /* MP Block Peripheral 4 */
364 5, /* USART 0 */
365 5, /* USART 1 */
366 5, /* USART 2 */
367 0, /* Multimedia Card Interface 0 */
368 0, /* Multimedia Card Interface 1 */
369 3, /* CAN */
370 6, /* Two-Wire Interface */
371 5, /* Serial Peripheral Interface 0 */
372 5, /* Serial Peripheral Interface 1 */
373 4, /* Serial Synchronous Controller 0 */
374 4, /* Serial Synchronous Controller 1 */
375 5, /* AC97 Controller */
376 0, /* Timer Counter 0, 1 and 2 */
377 0, /* Pulse Width Modulation Controller */
378 3, /* Ethernet */
379 0, /* Advanced Encryption Standard, Triple DES*/
380 0, /* Analog-to-Digital Converter */
381 0, /* Image Sensor Interface */
382 3, /* LCD Controller */
383 0, /* DMA Controller */
384 2, /* USB Device Port */
385 2, /* USB Host port */
386 0, /* Advanced Interrupt Controller (IRQ0) */
387 0, /* Advanced Interrupt Controller (IRQ1) */
388 };
389
390 struct at91_init_soc __initdata at91cap9_soc = {
391 .map_io = at91cap9_map_io,
392 .default_irq_priority = at91cap9_default_irq_priority,
393 .ioremap_registers = at91cap9_ioremap_registers,
394 .register_clocks = at91cap9_register_clocks,
395 .init = at91cap9_initialize,
396 };
397