1config ARM 2 bool 3 default y 4 select HAVE_AOUT 5 select HAVE_DMA_API_DEBUG 6 select HAVE_IDE if PCI || ISA || PCMCIA 7 select HAVE_MEMBLOCK 8 select RTC_LIB 9 select SYS_SUPPORTS_APM_EMULATION 10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI) 11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 12 select HAVE_ARCH_KGDB 13 select HAVE_KPROBES if !XIP_KERNEL 14 select HAVE_KRETPROBES if (HAVE_KPROBES) 15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) 18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 19 select ARCH_BINFMT_ELF_RANDOMIZE_PIE 20 select HAVE_GENERIC_DMA_COHERENT 21 select HAVE_KERNEL_GZIP 22 select HAVE_KERNEL_LZO 23 select HAVE_KERNEL_LZMA 24 select HAVE_IRQ_WORK 25 select HAVE_PERF_EVENTS 26 select PERF_USE_VMALLOC 27 select HAVE_REGS_AND_STACK_ACCESS_API 28 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 29 select HAVE_C_RECORDMCOUNT 30 select HAVE_GENERIC_HARDIRQS 31 select HAVE_SPARSE_IRQ 32 select GENERIC_IRQ_SHOW 33 select CPU_PM if (SUSPEND || CPU_IDLE) 34 select GENERIC_PCI_IOMAP 35 help 36 The ARM series is a line of low-power-consumption RISC chip designs 37 licensed by ARM Ltd and targeted at embedded applications and 38 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 39 manufactured, but legacy ARM-based PC hardware remains popular in 40 Europe. There is an ARM Linux project with a web page at 41 <http://www.arm.linux.org.uk/>. 42 43config ARM_HAS_SG_CHAIN 44 bool 45 46config HAVE_PWM 47 bool 48 49config MIGHT_HAVE_PCI 50 bool 51 52config SYS_SUPPORTS_APM_EMULATION 53 bool 54 55config HAVE_SCHED_CLOCK 56 bool 57 58config GENERIC_GPIO 59 bool 60 61config ARCH_USES_GETTIMEOFFSET 62 bool 63 default n 64 65config GENERIC_CLOCKEVENTS 66 bool 67 68config GENERIC_CLOCKEVENTS_BROADCAST 69 bool 70 depends on GENERIC_CLOCKEVENTS 71 default y if SMP 72 73config KTIME_SCALAR 74 bool 75 default y 76 77config HAVE_TCM 78 bool 79 select GENERIC_ALLOCATOR 80 81config HAVE_PROC_CPU 82 bool 83 84config NO_IOPORT 85 bool 86 87config EISA 88 bool 89 ---help--- 90 The Extended Industry Standard Architecture (EISA) bus was 91 developed as an open alternative to the IBM MicroChannel bus. 92 93 The EISA bus provided some of the features of the IBM MicroChannel 94 bus while maintaining backward compatibility with cards made for 95 the older ISA bus. The EISA bus saw limited use between 1988 and 96 1995 when it was made obsolete by the PCI bus. 97 98 Say Y here if you are building a kernel for an EISA-based machine. 99 100 Otherwise, say N. 101 102config SBUS 103 bool 104 105config MCA 106 bool 107 help 108 MicroChannel Architecture is found in some IBM PS/2 machines and 109 laptops. It is a bus system similar to PCI or ISA. See 110 <file:Documentation/mca.txt> (and especially the web page given 111 there) before attempting to build an MCA bus kernel. 112 113config STACKTRACE_SUPPORT 114 bool 115 default y 116 117config HAVE_LATENCYTOP_SUPPORT 118 bool 119 depends on !SMP 120 default y 121 122config LOCKDEP_SUPPORT 123 bool 124 default y 125 126config TRACE_IRQFLAGS_SUPPORT 127 bool 128 default y 129 130config HARDIRQS_SW_RESEND 131 bool 132 default y 133 134config GENERIC_IRQ_PROBE 135 bool 136 default y 137 138config GENERIC_LOCKBREAK 139 bool 140 default y 141 depends on SMP && PREEMPT 142 143config RWSEM_GENERIC_SPINLOCK 144 bool 145 default y 146 147config RWSEM_XCHGADD_ALGORITHM 148 bool 149 150config ARCH_HAS_ILOG2_U32 151 bool 152 153config ARCH_HAS_ILOG2_U64 154 bool 155 156config ARCH_HAS_CPUFREQ 157 bool 158 help 159 Internal node to signify that the ARCH has CPUFREQ support 160 and that the relevant menu configurations are displayed for 161 it. 162 163config ARCH_HAS_CPU_IDLE_WAIT 164 def_bool y 165 166config GENERIC_HWEIGHT 167 bool 168 default y 169 170config GENERIC_CALIBRATE_DELAY 171 bool 172 default y 173 174config ARCH_MAY_HAVE_PC_FDC 175 bool 176 177config ZONE_DMA 178 bool 179 180config NEED_DMA_MAP_STATE 181 def_bool y 182 183config GENERIC_ISA_DMA 184 bool 185 186config FIQ 187 bool 188 189config ARCH_MTD_XIP 190 bool 191 192config VECTORS_BASE 193 hex 194 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 195 default DRAM_BASE if REMAP_VECTORS_TO_RAM 196 default 0x00000000 197 help 198 The base address of exception vectors. 199 200config ARM_PATCH_PHYS_VIRT 201 bool "Patch physical to virtual translations at runtime" if EMBEDDED 202 default y 203 depends on !XIP_KERNEL && MMU 204 depends on !ARCH_REALVIEW || !SPARSEMEM 205 help 206 Patch phys-to-virt and virt-to-phys translation functions at 207 boot and module load time according to the position of the 208 kernel in system memory. 209 210 This can only be used with non-XIP MMU kernels where the base 211 of physical memory is at a 16MB boundary. 212 213 Only disable this option if you know that you do not require 214 this feature (eg, building a kernel for a single machine) and 215 you need to shrink the kernel to the minimal size. 216 217config NEED_MACH_MEMORY_H 218 bool 219 help 220 Select this when mach/memory.h is required to provide special 221 definitions for this platform. The need for mach/memory.h should 222 be avoided when possible. 223 224config PHYS_OFFSET 225 hex "Physical address of main memory" if MMU 226 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H 227 default DRAM_BASE if !MMU 228 help 229 Please provide the physical address corresponding to the 230 location of main memory in your system. 231 232config GENERIC_BUG 233 def_bool y 234 depends on BUG 235 236source "init/Kconfig" 237 238source "kernel/Kconfig.freezer" 239 240menu "System Type" 241 242config MMU 243 bool "MMU-based Paged Memory Management Support" 244 default y 245 help 246 Select if you want MMU-based virtualised addressing space 247 support by paged memory management. If unsure, say 'Y'. 248 249# 250# The "ARM system type" choice list is ordered alphabetically by option 251# text. Please add new entries in the option alphabetic order. 252# 253choice 254 prompt "ARM system type" 255 default ARCH_VERSATILE 256 257config ARCH_INTEGRATOR 258 bool "ARM Ltd. Integrator family" 259 select ARM_AMBA 260 select ARCH_HAS_CPUFREQ 261 select CLKDEV_LOOKUP 262 select HAVE_MACH_CLKDEV 263 select HAVE_TCM 264 select ICST 265 select GENERIC_CLOCKEVENTS 266 select PLAT_VERSATILE 267 select PLAT_VERSATILE_FPGA_IRQ 268 select NEED_MACH_MEMORY_H 269 help 270 Support for ARM's Integrator platform. 271 272config ARCH_REALVIEW 273 bool "ARM Ltd. RealView family" 274 select ARM_AMBA 275 select CLKDEV_LOOKUP 276 select HAVE_MACH_CLKDEV 277 select ICST 278 select GENERIC_CLOCKEVENTS 279 select ARCH_WANT_OPTIONAL_GPIOLIB 280 select PLAT_VERSATILE 281 select PLAT_VERSATILE_CLCD 282 select ARM_TIMER_SP804 283 select GPIO_PL061 if GPIOLIB 284 select NEED_MACH_MEMORY_H 285 help 286 This enables support for ARM Ltd RealView boards. 287 288config ARCH_VERSATILE 289 bool "ARM Ltd. Versatile family" 290 select ARM_AMBA 291 select ARM_VIC 292 select CLKDEV_LOOKUP 293 select HAVE_MACH_CLKDEV 294 select ICST 295 select GENERIC_CLOCKEVENTS 296 select ARCH_WANT_OPTIONAL_GPIOLIB 297 select PLAT_VERSATILE 298 select PLAT_VERSATILE_CLCD 299 select PLAT_VERSATILE_FPGA_IRQ 300 select ARM_TIMER_SP804 301 help 302 This enables support for ARM Ltd Versatile board. 303 304config ARCH_VEXPRESS 305 bool "ARM Ltd. Versatile Express family" 306 select ARCH_WANT_OPTIONAL_GPIOLIB 307 select ARM_AMBA 308 select ARM_TIMER_SP804 309 select CLKDEV_LOOKUP 310 select HAVE_MACH_CLKDEV 311 select GENERIC_CLOCKEVENTS 312 select HAVE_CLK 313 select HAVE_PATA_PLATFORM 314 select ICST 315 select PLAT_VERSATILE 316 select PLAT_VERSATILE_CLCD 317 help 318 This enables support for the ARM Ltd Versatile Express boards. 319 320config ARCH_AT91 321 bool "Atmel AT91" 322 select ARCH_REQUIRE_GPIOLIB 323 select HAVE_CLK 324 select CLKDEV_LOOKUP 325 help 326 This enables support for systems based on the Atmel AT91RM9200, 327 AT91SAM9 and AT91CAP9 processors. 328 329config ARCH_BCMRING 330 bool "Broadcom BCMRING" 331 depends on MMU 332 select CPU_V6 333 select ARM_AMBA 334 select ARM_TIMER_SP804 335 select CLKDEV_LOOKUP 336 select GENERIC_CLOCKEVENTS 337 select ARCH_WANT_OPTIONAL_GPIOLIB 338 help 339 Support for Broadcom's BCMRing platform. 340 341config ARCH_HIGHBANK 342 bool "Calxeda Highbank-based" 343 select ARCH_WANT_OPTIONAL_GPIOLIB 344 select ARM_AMBA 345 select ARM_GIC 346 select ARM_TIMER_SP804 347 select CACHE_L2X0 348 select CLKDEV_LOOKUP 349 select CPU_V7 350 select GENERIC_CLOCKEVENTS 351 select HAVE_ARM_SCU 352 select HAVE_SMP 353 select USE_OF 354 help 355 Support for the Calxeda Highbank SoC based boards. 356 357config ARCH_CLPS711X 358 bool "Cirrus Logic CLPS711x/EP721x-based" 359 select CPU_ARM720T 360 select ARCH_USES_GETTIMEOFFSET 361 select NEED_MACH_MEMORY_H 362 help 363 Support for Cirrus Logic 711x/721x based boards. 364 365config ARCH_CNS3XXX 366 bool "Cavium Networks CNS3XXX family" 367 select CPU_V6K 368 select GENERIC_CLOCKEVENTS 369 select ARM_GIC 370 select MIGHT_HAVE_CACHE_L2X0 371 select MIGHT_HAVE_PCI 372 select PCI_DOMAINS if PCI 373 help 374 Support for Cavium Networks CNS3XXX platform. 375 376config ARCH_GEMINI 377 bool "Cortina Systems Gemini" 378 select CPU_FA526 379 select ARCH_REQUIRE_GPIOLIB 380 select ARCH_USES_GETTIMEOFFSET 381 help 382 Support for the Cortina Systems Gemini family SoCs 383 384config ARCH_PRIMA2 385 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" 386 select CPU_V7 387 select NO_IOPORT 388 select GENERIC_CLOCKEVENTS 389 select CLKDEV_LOOKUP 390 select GENERIC_IRQ_CHIP 391 select MIGHT_HAVE_CACHE_L2X0 392 select USE_OF 393 select ZONE_DMA 394 help 395 Support for CSR SiRFSoC ARM Cortex A9 Platform 396 397config ARCH_EBSA110 398 bool "EBSA-110" 399 select CPU_SA110 400 select ISA 401 select NO_IOPORT 402 select ARCH_USES_GETTIMEOFFSET 403 select NEED_MACH_MEMORY_H 404 help 405 This is an evaluation board for the StrongARM processor available 406 from Digital. It has limited hardware on-board, including an 407 Ethernet interface, two PCMCIA sockets, two serial ports and a 408 parallel port. 409 410config ARCH_EP93XX 411 bool "EP93xx-based" 412 select CPU_ARM920T 413 select ARM_AMBA 414 select ARM_VIC 415 select CLKDEV_LOOKUP 416 select ARCH_REQUIRE_GPIOLIB 417 select ARCH_HAS_HOLES_MEMORYMODEL 418 select ARCH_USES_GETTIMEOFFSET 419 select NEED_MACH_MEMORY_H 420 help 421 This enables support for the Cirrus EP93xx series of CPUs. 422 423config ARCH_FOOTBRIDGE 424 bool "FootBridge" 425 select CPU_SA110 426 select FOOTBRIDGE 427 select GENERIC_CLOCKEVENTS 428 select HAVE_IDE 429 select NEED_MACH_MEMORY_H 430 help 431 Support for systems based on the DC21285 companion chip 432 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 433 434config ARCH_MXC 435 bool "Freescale MXC/iMX-based" 436 select GENERIC_CLOCKEVENTS 437 select ARCH_REQUIRE_GPIOLIB 438 select CLKDEV_LOOKUP 439 select CLKSRC_MMIO 440 select GENERIC_IRQ_CHIP 441 select HAVE_SCHED_CLOCK 442 select MULTI_IRQ_HANDLER 443 help 444 Support for Freescale MXC/iMX-based family of processors 445 446config ARCH_MXS 447 bool "Freescale MXS-based" 448 select GENERIC_CLOCKEVENTS 449 select ARCH_REQUIRE_GPIOLIB 450 select CLKDEV_LOOKUP 451 select CLKSRC_MMIO 452 select HAVE_CLK_PREPARE 453 help 454 Support for Freescale MXS-based family of processors 455 456config ARCH_NETX 457 bool "Hilscher NetX based" 458 select CLKSRC_MMIO 459 select CPU_ARM926T 460 select ARM_VIC 461 select GENERIC_CLOCKEVENTS 462 help 463 This enables support for systems based on the Hilscher NetX Soc 464 465config ARCH_H720X 466 bool "Hynix HMS720x-based" 467 select CPU_ARM720T 468 select ISA_DMA_API 469 select ARCH_USES_GETTIMEOFFSET 470 help 471 This enables support for systems based on the Hynix HMS720x 472 473config ARCH_IOP13XX 474 bool "IOP13xx-based" 475 depends on MMU 476 select CPU_XSC3 477 select PLAT_IOP 478 select PCI 479 select ARCH_SUPPORTS_MSI 480 select VMSPLIT_1G 481 select NEED_MACH_MEMORY_H 482 help 483 Support for Intel's IOP13XX (XScale) family of processors. 484 485config ARCH_IOP32X 486 bool "IOP32x-based" 487 depends on MMU 488 select CPU_XSCALE 489 select PLAT_IOP 490 select PCI 491 select ARCH_REQUIRE_GPIOLIB 492 help 493 Support for Intel's 80219 and IOP32X (XScale) family of 494 processors. 495 496config ARCH_IOP33X 497 bool "IOP33x-based" 498 depends on MMU 499 select CPU_XSCALE 500 select PLAT_IOP 501 select PCI 502 select ARCH_REQUIRE_GPIOLIB 503 help 504 Support for Intel's IOP33X (XScale) family of processors. 505 506config ARCH_IXP23XX 507 bool "IXP23XX-based" 508 depends on MMU 509 select CPU_XSC3 510 select PCI 511 select ARCH_USES_GETTIMEOFFSET 512 select NEED_MACH_MEMORY_H 513 help 514 Support for Intel's IXP23xx (XScale) family of processors. 515 516config ARCH_IXP2000 517 bool "IXP2400/2800-based" 518 depends on MMU 519 select CPU_XSCALE 520 select PCI 521 select ARCH_USES_GETTIMEOFFSET 522 select NEED_MACH_MEMORY_H 523 help 524 Support for Intel's IXP2400/2800 (XScale) family of processors. 525 526config ARCH_IXP4XX 527 bool "IXP4xx-based" 528 depends on MMU 529 select CLKSRC_MMIO 530 select CPU_XSCALE 531 select GENERIC_GPIO 532 select GENERIC_CLOCKEVENTS 533 select HAVE_SCHED_CLOCK 534 select MIGHT_HAVE_PCI 535 select DMABOUNCE if PCI 536 help 537 Support for Intel's IXP4XX (XScale) family of processors. 538 539config ARCH_DOVE 540 bool "Marvell Dove" 541 select CPU_V7 542 select PCI 543 select ARCH_REQUIRE_GPIOLIB 544 select GENERIC_CLOCKEVENTS 545 select PLAT_ORION 546 help 547 Support for the Marvell Dove SoC 88AP510 548 549config ARCH_KIRKWOOD 550 bool "Marvell Kirkwood" 551 select CPU_FEROCEON 552 select PCI 553 select ARCH_REQUIRE_GPIOLIB 554 select GENERIC_CLOCKEVENTS 555 select PLAT_ORION 556 help 557 Support for the following Marvell Kirkwood series SoCs: 558 88F6180, 88F6192 and 88F6281. 559 560config ARCH_LPC32XX 561 bool "NXP LPC32XX" 562 select CLKSRC_MMIO 563 select CPU_ARM926T 564 select ARCH_REQUIRE_GPIOLIB 565 select HAVE_IDE 566 select ARM_AMBA 567 select USB_ARCH_HAS_OHCI 568 select CLKDEV_LOOKUP 569 select GENERIC_CLOCKEVENTS 570 help 571 Support for the NXP LPC32XX family of processors 572 573config ARCH_MV78XX0 574 bool "Marvell MV78xx0" 575 select CPU_FEROCEON 576 select PCI 577 select ARCH_REQUIRE_GPIOLIB 578 select GENERIC_CLOCKEVENTS 579 select PLAT_ORION 580 help 581 Support for the following Marvell MV78xx0 series SoCs: 582 MV781x0, MV782x0. 583 584config ARCH_ORION5X 585 bool "Marvell Orion" 586 depends on MMU 587 select CPU_FEROCEON 588 select PCI 589 select ARCH_REQUIRE_GPIOLIB 590 select GENERIC_CLOCKEVENTS 591 select PLAT_ORION 592 help 593 Support for the following Marvell Orion 5x series SoCs: 594 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), 595 Orion-2 (5281), Orion-1-90 (6183). 596 597config ARCH_MMP 598 bool "Marvell PXA168/910/MMP2" 599 depends on MMU 600 select ARCH_REQUIRE_GPIOLIB 601 select CLKDEV_LOOKUP 602 select GENERIC_CLOCKEVENTS 603 select GPIO_PXA 604 select HAVE_SCHED_CLOCK 605 select TICK_ONESHOT 606 select PLAT_PXA 607 select SPARSE_IRQ 608 select GENERIC_ALLOCATOR 609 help 610 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. 611 612config ARCH_KS8695 613 bool "Micrel/Kendin KS8695" 614 select CPU_ARM922T 615 select ARCH_REQUIRE_GPIOLIB 616 select ARCH_USES_GETTIMEOFFSET 617 select NEED_MACH_MEMORY_H 618 help 619 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 620 System-on-Chip devices. 621 622config ARCH_W90X900 623 bool "Nuvoton W90X900 CPU" 624 select CPU_ARM926T 625 select ARCH_REQUIRE_GPIOLIB 626 select CLKDEV_LOOKUP 627 select CLKSRC_MMIO 628 select GENERIC_CLOCKEVENTS 629 help 630 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 631 At present, the w90x900 has been renamed nuc900, regarding 632 the ARM series product line, you can login the following 633 link address to know more. 634 635 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 636 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 637 638config ARCH_TEGRA 639 bool "NVIDIA Tegra" 640 select CLKDEV_LOOKUP 641 select CLKSRC_MMIO 642 select GENERIC_CLOCKEVENTS 643 select GENERIC_GPIO 644 select HAVE_CLK 645 select HAVE_SCHED_CLOCK 646 select HAVE_SMP 647 select MIGHT_HAVE_CACHE_L2X0 648 select ARCH_HAS_CPUFREQ 649 help 650 This enables support for NVIDIA Tegra based systems (Tegra APX, 651 Tegra 6xx and Tegra 2 series). 652 653config ARCH_PICOXCELL 654 bool "Picochip picoXcell" 655 select ARCH_REQUIRE_GPIOLIB 656 select ARM_PATCH_PHYS_VIRT 657 select ARM_VIC 658 select CPU_V6K 659 select DW_APB_TIMER 660 select GENERIC_CLOCKEVENTS 661 select GENERIC_GPIO 662 select HAVE_SCHED_CLOCK 663 select HAVE_TCM 664 select NO_IOPORT 665 select SPARSE_IRQ 666 select USE_OF 667 help 668 This enables support for systems based on the Picochip picoXcell 669 family of Femtocell devices. The picoxcell support requires device tree 670 for all boards. 671 672config ARCH_PNX4008 673 bool "Philips Nexperia PNX4008 Mobile" 674 select CPU_ARM926T 675 select CLKDEV_LOOKUP 676 select ARCH_USES_GETTIMEOFFSET 677 help 678 This enables support for Philips PNX4008 mobile platform. 679 680config ARCH_PXA 681 bool "PXA2xx/PXA3xx-based" 682 depends on MMU 683 select ARCH_MTD_XIP 684 select ARCH_HAS_CPUFREQ 685 select CLKDEV_LOOKUP 686 select CLKSRC_MMIO 687 select ARCH_REQUIRE_GPIOLIB 688 select GENERIC_CLOCKEVENTS 689 select GPIO_PXA 690 select HAVE_SCHED_CLOCK 691 select TICK_ONESHOT 692 select PLAT_PXA 693 select SPARSE_IRQ 694 select AUTO_ZRELADDR 695 select MULTI_IRQ_HANDLER 696 select ARM_CPU_SUSPEND if PM 697 select HAVE_IDE 698 help 699 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 700 701config ARCH_MSM 702 bool "Qualcomm MSM" 703 select HAVE_CLK 704 select GENERIC_CLOCKEVENTS 705 select ARCH_REQUIRE_GPIOLIB 706 select CLKDEV_LOOKUP 707 help 708 Support for Qualcomm MSM/QSD based systems. This runs on the 709 apps processor of the MSM/QSD and depends on a shared memory 710 interface to the modem processor which runs the baseband 711 stack and controls some vital subsystems 712 (clock and power control, etc). 713 714config ARCH_SHMOBILE 715 bool "Renesas SH-Mobile / R-Mobile" 716 select HAVE_CLK 717 select CLKDEV_LOOKUP 718 select HAVE_MACH_CLKDEV 719 select HAVE_SMP 720 select GENERIC_CLOCKEVENTS 721 select MIGHT_HAVE_CACHE_L2X0 722 select NO_IOPORT 723 select SPARSE_IRQ 724 select MULTI_IRQ_HANDLER 725 select PM_GENERIC_DOMAINS if PM 726 select NEED_MACH_MEMORY_H 727 help 728 Support for Renesas's SH-Mobile and R-Mobile ARM platforms. 729 730config ARCH_RPC 731 bool "RiscPC" 732 select ARCH_ACORN 733 select FIQ 734 select TIMER_ACORN 735 select ARCH_MAY_HAVE_PC_FDC 736 select HAVE_PATA_PLATFORM 737 select ISA_DMA_API 738 select NO_IOPORT 739 select ARCH_SPARSEMEM_ENABLE 740 select ARCH_USES_GETTIMEOFFSET 741 select HAVE_IDE 742 select NEED_MACH_MEMORY_H 743 help 744 On the Acorn Risc-PC, Linux can support the internal IDE disk and 745 CD-ROM interface, serial and parallel port, and the floppy drive. 746 747config ARCH_SA1100 748 bool "SA1100-based" 749 select CLKSRC_MMIO 750 select CPU_SA1100 751 select ISA 752 select ARCH_SPARSEMEM_ENABLE 753 select ARCH_MTD_XIP 754 select ARCH_HAS_CPUFREQ 755 select CPU_FREQ 756 select GENERIC_CLOCKEVENTS 757 select HAVE_CLK 758 select HAVE_SCHED_CLOCK 759 select TICK_ONESHOT 760 select ARCH_REQUIRE_GPIOLIB 761 select HAVE_IDE 762 select NEED_MACH_MEMORY_H 763 help 764 Support for StrongARM 11x0 based boards. 765 766config ARCH_S3C2410 767 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450" 768 select GENERIC_GPIO 769 select ARCH_HAS_CPUFREQ 770 select HAVE_CLK 771 select CLKDEV_LOOKUP 772 select ARCH_USES_GETTIMEOFFSET 773 select HAVE_S3C2410_I2C if I2C 774 help 775 Samsung S3C2410X CPU based systems, such as the Simtec Electronics 776 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or 777 the Samsung SMDK2410 development board (and derivatives). 778 779 Note, the S3C2416 and the S3C2450 are so close that they even share 780 the same SoC ID code. This means that there is no separate machine 781 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first. 782 783config ARCH_S3C64XX 784 bool "Samsung S3C64XX" 785 select PLAT_SAMSUNG 786 select CPU_V6 787 select ARM_VIC 788 select HAVE_CLK 789 select HAVE_TCM 790 select CLKDEV_LOOKUP 791 select NO_IOPORT 792 select ARCH_USES_GETTIMEOFFSET 793 select ARCH_HAS_CPUFREQ 794 select ARCH_REQUIRE_GPIOLIB 795 select SAMSUNG_CLKSRC 796 select SAMSUNG_IRQ_VIC_TIMER 797 select S3C_GPIO_TRACK 798 select S3C_DEV_NAND 799 select USB_ARCH_HAS_OHCI 800 select SAMSUNG_GPIOLIB_4BIT 801 select HAVE_S3C2410_I2C if I2C 802 select HAVE_S3C2410_WATCHDOG if WATCHDOG 803 help 804 Samsung S3C64XX series based systems 805 806config ARCH_S5P64X0 807 bool "Samsung S5P6440 S5P6450" 808 select CPU_V6 809 select GENERIC_GPIO 810 select HAVE_CLK 811 select CLKDEV_LOOKUP 812 select CLKSRC_MMIO 813 select HAVE_S3C2410_WATCHDOG if WATCHDOG 814 select GENERIC_CLOCKEVENTS 815 select HAVE_SCHED_CLOCK 816 select HAVE_S3C2410_I2C if I2C 817 select HAVE_S3C_RTC if RTC_CLASS 818 help 819 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, 820 SMDK6450. 821 822config ARCH_S5PC100 823 bool "Samsung S5PC100" 824 select GENERIC_GPIO 825 select HAVE_CLK 826 select CLKDEV_LOOKUP 827 select CPU_V7 828 select ARCH_USES_GETTIMEOFFSET 829 select HAVE_S3C2410_I2C if I2C 830 select HAVE_S3C_RTC if RTC_CLASS 831 select HAVE_S3C2410_WATCHDOG if WATCHDOG 832 help 833 Samsung S5PC100 series based systems 834 835config ARCH_S5PV210 836 bool "Samsung S5PV210/S5PC110" 837 select CPU_V7 838 select ARCH_SPARSEMEM_ENABLE 839 select ARCH_HAS_HOLES_MEMORYMODEL 840 select GENERIC_GPIO 841 select HAVE_CLK 842 select CLKDEV_LOOKUP 843 select CLKSRC_MMIO 844 select ARCH_HAS_CPUFREQ 845 select GENERIC_CLOCKEVENTS 846 select HAVE_SCHED_CLOCK 847 select HAVE_S3C2410_I2C if I2C 848 select HAVE_S3C_RTC if RTC_CLASS 849 select HAVE_S3C2410_WATCHDOG if WATCHDOG 850 select NEED_MACH_MEMORY_H 851 help 852 Samsung S5PV210/S5PC110 series based systems 853 854config ARCH_EXYNOS 855 bool "SAMSUNG EXYNOS" 856 select CPU_V7 857 select ARCH_SPARSEMEM_ENABLE 858 select ARCH_HAS_HOLES_MEMORYMODEL 859 select GENERIC_GPIO 860 select HAVE_CLK 861 select CLKDEV_LOOKUP 862 select ARCH_HAS_CPUFREQ 863 select GENERIC_CLOCKEVENTS 864 select HAVE_S3C_RTC if RTC_CLASS 865 select HAVE_S3C2410_I2C if I2C 866 select HAVE_S3C2410_WATCHDOG if WATCHDOG 867 select NEED_MACH_MEMORY_H 868 help 869 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) 870 871config ARCH_SHARK 872 bool "Shark" 873 select CPU_SA110 874 select ISA 875 select ISA_DMA 876 select ZONE_DMA 877 select PCI 878 select ARCH_USES_GETTIMEOFFSET 879 select NEED_MACH_MEMORY_H 880 help 881 Support for the StrongARM based Digital DNARD machine, also known 882 as "Shark" (<http://www.shark-linux.de/shark.html>). 883 884config ARCH_U300 885 bool "ST-Ericsson U300 Series" 886 depends on MMU 887 select CLKSRC_MMIO 888 select CPU_ARM926T 889 select HAVE_SCHED_CLOCK 890 select HAVE_TCM 891 select ARM_AMBA 892 select ARM_PATCH_PHYS_VIRT 893 select ARM_VIC 894 select GENERIC_CLOCKEVENTS 895 select CLKDEV_LOOKUP 896 select HAVE_MACH_CLKDEV 897 select GENERIC_GPIO 898 select ARCH_REQUIRE_GPIOLIB 899 help 900 Support for ST-Ericsson U300 series mobile platforms. 901 902config ARCH_U8500 903 bool "ST-Ericsson U8500 Series" 904 select CPU_V7 905 select ARM_AMBA 906 select GENERIC_CLOCKEVENTS 907 select CLKDEV_LOOKUP 908 select ARCH_REQUIRE_GPIOLIB 909 select ARCH_HAS_CPUFREQ 910 select HAVE_SMP 911 select MIGHT_HAVE_CACHE_L2X0 912 help 913 Support for ST-Ericsson's Ux500 architecture 914 915config ARCH_NOMADIK 916 bool "STMicroelectronics Nomadik" 917 select ARM_AMBA 918 select ARM_VIC 919 select CPU_ARM926T 920 select CLKDEV_LOOKUP 921 select GENERIC_CLOCKEVENTS 922 select MIGHT_HAVE_CACHE_L2X0 923 select ARCH_REQUIRE_GPIOLIB 924 help 925 Support for the Nomadik platform by ST-Ericsson 926 927config ARCH_DAVINCI 928 bool "TI DaVinci" 929 select GENERIC_CLOCKEVENTS 930 select ARCH_REQUIRE_GPIOLIB 931 select ZONE_DMA 932 select HAVE_IDE 933 select CLKDEV_LOOKUP 934 select GENERIC_ALLOCATOR 935 select GENERIC_IRQ_CHIP 936 select ARCH_HAS_HOLES_MEMORYMODEL 937 help 938 Support for TI's DaVinci platform. 939 940config ARCH_OMAP 941 bool "TI OMAP" 942 select HAVE_CLK 943 select ARCH_REQUIRE_GPIOLIB 944 select ARCH_HAS_CPUFREQ 945 select CLKSRC_MMIO 946 select GENERIC_CLOCKEVENTS 947 select HAVE_SCHED_CLOCK 948 select ARCH_HAS_HOLES_MEMORYMODEL 949 help 950 Support for TI's OMAP platform (OMAP1/2/3/4). 951 952config PLAT_SPEAR 953 bool "ST SPEAr" 954 select ARM_AMBA 955 select ARCH_REQUIRE_GPIOLIB 956 select CLKDEV_LOOKUP 957 select CLKSRC_MMIO 958 select GENERIC_CLOCKEVENTS 959 select HAVE_CLK 960 help 961 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). 962 963config ARCH_VT8500 964 bool "VIA/WonderMedia 85xx" 965 select CPU_ARM926T 966 select GENERIC_GPIO 967 select ARCH_HAS_CPUFREQ 968 select GENERIC_CLOCKEVENTS 969 select ARCH_REQUIRE_GPIOLIB 970 select HAVE_PWM 971 help 972 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. 973 974config ARCH_ZYNQ 975 bool "Xilinx Zynq ARM Cortex A9 Platform" 976 select CPU_V7 977 select GENERIC_CLOCKEVENTS 978 select CLKDEV_LOOKUP 979 select ARM_GIC 980 select ARM_AMBA 981 select ICST 982 select MIGHT_HAVE_CACHE_L2X0 983 select USE_OF 984 help 985 Support for Xilinx Zynq ARM Cortex A9 Platform 986endchoice 987 988# 989# This is sorted alphabetically by mach-* pathname. However, plat-* 990# Kconfigs may be included either alphabetically (according to the 991# plat- suffix) or along side the corresponding mach-* source. 992# 993source "arch/arm/mach-at91/Kconfig" 994 995source "arch/arm/mach-bcmring/Kconfig" 996 997source "arch/arm/mach-clps711x/Kconfig" 998 999source "arch/arm/mach-cns3xxx/Kconfig" 1000 1001source "arch/arm/mach-davinci/Kconfig" 1002 1003source "arch/arm/mach-dove/Kconfig" 1004 1005source "arch/arm/mach-ep93xx/Kconfig" 1006 1007source "arch/arm/mach-footbridge/Kconfig" 1008 1009source "arch/arm/mach-gemini/Kconfig" 1010 1011source "arch/arm/mach-h720x/Kconfig" 1012 1013source "arch/arm/mach-integrator/Kconfig" 1014 1015source "arch/arm/mach-iop32x/Kconfig" 1016 1017source "arch/arm/mach-iop33x/Kconfig" 1018 1019source "arch/arm/mach-iop13xx/Kconfig" 1020 1021source "arch/arm/mach-ixp4xx/Kconfig" 1022 1023source "arch/arm/mach-ixp2000/Kconfig" 1024 1025source "arch/arm/mach-ixp23xx/Kconfig" 1026 1027source "arch/arm/mach-kirkwood/Kconfig" 1028 1029source "arch/arm/mach-ks8695/Kconfig" 1030 1031source "arch/arm/mach-lpc32xx/Kconfig" 1032 1033source "arch/arm/mach-msm/Kconfig" 1034 1035source "arch/arm/mach-mv78xx0/Kconfig" 1036 1037source "arch/arm/plat-mxc/Kconfig" 1038 1039source "arch/arm/mach-mxs/Kconfig" 1040 1041source "arch/arm/mach-netx/Kconfig" 1042 1043source "arch/arm/mach-nomadik/Kconfig" 1044source "arch/arm/plat-nomadik/Kconfig" 1045 1046source "arch/arm/plat-omap/Kconfig" 1047 1048source "arch/arm/mach-omap1/Kconfig" 1049 1050source "arch/arm/mach-omap2/Kconfig" 1051 1052source "arch/arm/mach-orion5x/Kconfig" 1053 1054source "arch/arm/mach-pxa/Kconfig" 1055source "arch/arm/plat-pxa/Kconfig" 1056 1057source "arch/arm/mach-mmp/Kconfig" 1058 1059source "arch/arm/mach-realview/Kconfig" 1060 1061source "arch/arm/mach-sa1100/Kconfig" 1062 1063source "arch/arm/plat-samsung/Kconfig" 1064source "arch/arm/plat-s3c24xx/Kconfig" 1065source "arch/arm/plat-s5p/Kconfig" 1066 1067source "arch/arm/plat-spear/Kconfig" 1068 1069if ARCH_S3C2410 1070source "arch/arm/mach-s3c2410/Kconfig" 1071source "arch/arm/mach-s3c2412/Kconfig" 1072source "arch/arm/mach-s3c2416/Kconfig" 1073source "arch/arm/mach-s3c2440/Kconfig" 1074source "arch/arm/mach-s3c2443/Kconfig" 1075endif 1076 1077if ARCH_S3C64XX 1078source "arch/arm/mach-s3c64xx/Kconfig" 1079endif 1080 1081source "arch/arm/mach-s5p64x0/Kconfig" 1082 1083source "arch/arm/mach-s5pc100/Kconfig" 1084 1085source "arch/arm/mach-s5pv210/Kconfig" 1086 1087source "arch/arm/mach-exynos/Kconfig" 1088 1089source "arch/arm/mach-shmobile/Kconfig" 1090 1091source "arch/arm/mach-tegra/Kconfig" 1092 1093source "arch/arm/mach-u300/Kconfig" 1094 1095source "arch/arm/mach-ux500/Kconfig" 1096 1097source "arch/arm/mach-versatile/Kconfig" 1098 1099source "arch/arm/mach-vexpress/Kconfig" 1100source "arch/arm/plat-versatile/Kconfig" 1101 1102source "arch/arm/mach-vt8500/Kconfig" 1103 1104source "arch/arm/mach-w90x900/Kconfig" 1105 1106# Definitions to make life easier 1107config ARCH_ACORN 1108 bool 1109 1110config PLAT_IOP 1111 bool 1112 select GENERIC_CLOCKEVENTS 1113 select HAVE_SCHED_CLOCK 1114 1115config PLAT_ORION 1116 bool 1117 select CLKSRC_MMIO 1118 select GENERIC_IRQ_CHIP 1119 select HAVE_SCHED_CLOCK 1120 1121config PLAT_PXA 1122 bool 1123 1124config PLAT_VERSATILE 1125 bool 1126 1127config ARM_TIMER_SP804 1128 bool 1129 select CLKSRC_MMIO 1130 1131source arch/arm/mm/Kconfig 1132 1133config ARM_NR_BANKS 1134 int 1135 default 16 if ARCH_EP93XX 1136 default 8 1137 1138config IWMMXT 1139 bool "Enable iWMMXt support" 1140 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 1141 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP 1142 help 1143 Enable support for iWMMXt context switching at run time if 1144 running on a CPU that supports it. 1145 1146config XSCALE_PMU 1147 bool 1148 depends on CPU_XSCALE 1149 default y 1150 1151config CPU_HAS_PMU 1152 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \ 1153 (!ARCH_OMAP3 || OMAP3_EMU) 1154 default y 1155 bool 1156 1157config MULTI_IRQ_HANDLER 1158 bool 1159 help 1160 Allow each machine to specify it's own IRQ handler at run time. 1161 1162if !MMU 1163source "arch/arm/Kconfig-nommu" 1164endif 1165 1166config ARM_ERRATA_411920 1167 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 1168 depends on CPU_V6 || CPU_V6K 1169 help 1170 Invalidation of the Instruction Cache operation can 1171 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 1172 It does not affect the MPCore. This option enables the ARM Ltd. 1173 recommended workaround. 1174 1175config ARM_ERRATA_430973 1176 bool "ARM errata: Stale prediction on replaced interworking branch" 1177 depends on CPU_V7 1178 help 1179 This option enables the workaround for the 430973 Cortex-A8 1180 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb 1181 interworking branch is replaced with another code sequence at the 1182 same virtual address, whether due to self-modifying code or virtual 1183 to physical address re-mapping, Cortex-A8 does not recover from the 1184 stale interworking branch prediction. This results in Cortex-A8 1185 executing the new code sequence in the incorrect ARM or Thumb state. 1186 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 1187 and also flushes the branch target cache at every context switch. 1188 Note that setting specific bits in the ACTLR register may not be 1189 available in non-secure mode. 1190 1191config ARM_ERRATA_458693 1192 bool "ARM errata: Processor deadlock when a false hazard is created" 1193 depends on CPU_V7 1194 help 1195 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 1196 erratum. For very specific sequences of memory operations, it is 1197 possible for a hazard condition intended for a cache line to instead 1198 be incorrectly associated with a different cache line. This false 1199 hazard might then cause a processor deadlock. The workaround enables 1200 the L1 caching of the NEON accesses and disables the PLD instruction 1201 in the ACTLR register. Note that setting specific bits in the ACTLR 1202 register may not be available in non-secure mode. 1203 1204config ARM_ERRATA_460075 1205 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 1206 depends on CPU_V7 1207 help 1208 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1209 erratum. Any asynchronous access to the L2 cache may encounter a 1210 situation in which recent store transactions to the L2 cache are lost 1211 and overwritten with stale memory contents from external memory. The 1212 workaround disables the write-allocate mode for the L2 cache via the 1213 ACTLR register. Note that setting specific bits in the ACTLR register 1214 may not be available in non-secure mode. 1215 1216config ARM_ERRATA_742230 1217 bool "ARM errata: DMB operation may be faulty" 1218 depends on CPU_V7 && SMP 1219 help 1220 This option enables the workaround for the 742230 Cortex-A9 1221 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1222 between two write operations may not ensure the correct visibility 1223 ordering of the two writes. This workaround sets a specific bit in 1224 the diagnostic register of the Cortex-A9 which causes the DMB 1225 instruction to behave as a DSB, ensuring the correct behaviour of 1226 the two writes. 1227 1228config ARM_ERRATA_742231 1229 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1230 depends on CPU_V7 && SMP 1231 help 1232 This option enables the workaround for the 742231 Cortex-A9 1233 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1234 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1235 accessing some data located in the same cache line, may get corrupted 1236 data due to bad handling of the address hazard when the line gets 1237 replaced from one of the CPUs at the same time as another CPU is 1238 accessing it. This workaround sets specific bits in the diagnostic 1239 register of the Cortex-A9 which reduces the linefill issuing 1240 capabilities of the processor. 1241 1242config PL310_ERRATA_588369 1243 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" 1244 depends on CACHE_L2X0 1245 help 1246 The PL310 L2 cache controller implements three types of Clean & 1247 Invalidate maintenance operations: by Physical Address 1248 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). 1249 They are architecturally defined to behave as the execution of a 1250 clean operation followed immediately by an invalidate operation, 1251 both performing to the same memory location. This functionality 1252 is not correctly implemented in PL310 as clean lines are not 1253 invalidated as a result of these operations. 1254 1255config ARM_ERRATA_720789 1256 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1257 depends on CPU_V7 1258 help 1259 This option enables the workaround for the 720789 Cortex-A9 (prior to 1260 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1261 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1262 As a consequence of this erratum, some TLB entries which should be 1263 invalidated are not, resulting in an incoherency in the system page 1264 tables. The workaround changes the TLB flushing routines to invalidate 1265 entries regardless of the ASID. 1266 1267config PL310_ERRATA_727915 1268 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" 1269 depends on CACHE_L2X0 1270 help 1271 PL310 implements the Clean & Invalidate by Way L2 cache maintenance 1272 operation (offset 0x7FC). This operation runs in background so that 1273 PL310 can handle normal accesses while it is in progress. Under very 1274 rare circumstances, due to this erratum, write data can be lost when 1275 PL310 treats a cacheable write transaction during a Clean & 1276 Invalidate by Way operation. 1277 1278config ARM_ERRATA_743622 1279 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1280 depends on CPU_V7 1281 help 1282 This option enables the workaround for the 743622 Cortex-A9 1283 (r2p*) erratum. Under very rare conditions, a faulty 1284 optimisation in the Cortex-A9 Store Buffer may lead to data 1285 corruption. This workaround sets a specific bit in the diagnostic 1286 register of the Cortex-A9 which disables the Store Buffer 1287 optimisation, preventing the defect from occurring. This has no 1288 visible impact on the overall performance or power consumption of the 1289 processor. 1290 1291config ARM_ERRATA_751472 1292 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1293 depends on CPU_V7 1294 help 1295 This option enables the workaround for the 751472 Cortex-A9 (prior 1296 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1297 completion of a following broadcasted operation if the second 1298 operation is received by a CPU before the ICIALLUIS has completed, 1299 potentially leading to corrupted entries in the cache or TLB. 1300 1301config PL310_ERRATA_753970 1302 bool "PL310 errata: cache sync operation may be faulty" 1303 depends on CACHE_PL310 1304 help 1305 This option enables the workaround for the 753970 PL310 (r3p0) erratum. 1306 1307 Under some condition the effect of cache sync operation on 1308 the store buffer still remains when the operation completes. 1309 This means that the store buffer is always asked to drain and 1310 this prevents it from merging any further writes. The workaround 1311 is to replace the normal offset of cache sync operation (0x730) 1312 by another offset targeting an unmapped PL310 register 0x740. 1313 This has the same effect as the cache sync operation: store buffer 1314 drain and waiting for all buffers empty. 1315 1316config ARM_ERRATA_754322 1317 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1318 depends on CPU_V7 1319 help 1320 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1321 r3p*) erratum. A speculative memory access may cause a page table walk 1322 which starts prior to an ASID switch but completes afterwards. This 1323 can populate the micro-TLB with a stale entry which may be hit with 1324 the new ASID. This workaround places two dsb instructions in the mm 1325 switching code so that no page table walks can cross the ASID switch. 1326 1327config ARM_ERRATA_754327 1328 bool "ARM errata: no automatic Store Buffer drain" 1329 depends on CPU_V7 && SMP 1330 help 1331 This option enables the workaround for the 754327 Cortex-A9 (prior to 1332 r2p0) erratum. The Store Buffer does not have any automatic draining 1333 mechanism and therefore a livelock may occur if an external agent 1334 continuously polls a memory location waiting to observe an update. 1335 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1336 written polling loops from denying visibility of updates to memory. 1337 1338config ARM_ERRATA_364296 1339 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1340 depends on CPU_V6 && !SMP 1341 help 1342 This options enables the workaround for the 364296 ARM1136 1343 r0p2 erratum (possible cache data corruption with 1344 hit-under-miss enabled). It sets the undocumented bit 31 in 1345 the auxiliary control register and the FI bit in the control 1346 register, thus disabling hit-under-miss without putting the 1347 processor into full low interrupt latency mode. ARM11MPCore 1348 is not affected. 1349 1350config ARM_ERRATA_764369 1351 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1352 depends on CPU_V7 && SMP 1353 help 1354 This option enables the workaround for erratum 764369 1355 affecting Cortex-A9 MPCore with two or more processors (all 1356 current revisions). Under certain timing circumstances, a data 1357 cache line maintenance operation by MVA targeting an Inner 1358 Shareable memory region may fail to proceed up to either the 1359 Point of Coherency or to the Point of Unification of the 1360 system. This workaround adds a DSB instruction before the 1361 relevant cache maintenance functions and sets a specific bit 1362 in the diagnostic control register of the SCU. 1363 1364config PL310_ERRATA_769419 1365 bool "PL310 errata: no automatic Store Buffer drain" 1366 depends on CACHE_L2X0 1367 help 1368 On revisions of the PL310 prior to r3p2, the Store Buffer does 1369 not automatically drain. This can cause normal, non-cacheable 1370 writes to be retained when the memory system is idle, leading 1371 to suboptimal I/O performance for drivers using coherent DMA. 1372 This option adds a write barrier to the cpu_idle loop so that, 1373 on systems with an outer cache, the store buffer is drained 1374 explicitly. 1375 1376endmenu 1377 1378source "arch/arm/common/Kconfig" 1379 1380menu "Bus support" 1381 1382config ARM_AMBA 1383 bool 1384 1385config ISA 1386 bool 1387 help 1388 Find out whether you have ISA slots on your motherboard. ISA is the 1389 name of a bus system, i.e. the way the CPU talks to the other stuff 1390 inside your box. Other bus systems are PCI, EISA, MicroChannel 1391 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1392 newer boards don't support it. If you have ISA, say Y, otherwise N. 1393 1394# Select ISA DMA controller support 1395config ISA_DMA 1396 bool 1397 select ISA_DMA_API 1398 1399# Select ISA DMA interface 1400config ISA_DMA_API 1401 bool 1402 1403config PCI 1404 bool "PCI support" if MIGHT_HAVE_PCI 1405 help 1406 Find out whether you have a PCI motherboard. PCI is the name of a 1407 bus system, i.e. the way the CPU talks to the other stuff inside 1408 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1409 VESA. If you have PCI, say Y, otherwise N. 1410 1411config PCI_DOMAINS 1412 bool 1413 depends on PCI 1414 1415config PCI_NANOENGINE 1416 bool "BSE nanoEngine PCI support" 1417 depends on SA1100_NANOENGINE 1418 help 1419 Enable PCI on the BSE nanoEngine board. 1420 1421config PCI_SYSCALL 1422 def_bool PCI 1423 1424# Select the host bridge type 1425config PCI_HOST_VIA82C505 1426 bool 1427 depends on PCI && ARCH_SHARK 1428 default y 1429 1430config PCI_HOST_ITE8152 1431 bool 1432 depends on PCI && MACH_ARMCORE 1433 default y 1434 select DMABOUNCE 1435 1436source "drivers/pci/Kconfig" 1437 1438source "drivers/pcmcia/Kconfig" 1439 1440endmenu 1441 1442menu "Kernel Features" 1443 1444source "kernel/time/Kconfig" 1445 1446config HAVE_SMP 1447 bool 1448 help 1449 This option should be selected by machines which have an SMP- 1450 capable CPU. 1451 1452 The only effect of this option is to make the SMP-related 1453 options available to the user for configuration. 1454 1455config SMP 1456 bool "Symmetric Multi-Processing" 1457 depends on CPU_V6K || CPU_V7 1458 depends on GENERIC_CLOCKEVENTS 1459 depends on HAVE_SMP 1460 depends on MMU 1461 select USE_GENERIC_SMP_HELPERS 1462 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP 1463 help 1464 This enables support for systems with more than one CPU. If you have 1465 a system with only one CPU, like most personal computers, say N. If 1466 you have a system with more than one CPU, say Y. 1467 1468 If you say N here, the kernel will run on single and multiprocessor 1469 machines, but will use only one CPU of a multiprocessor machine. If 1470 you say Y here, the kernel will run on many, but not all, single 1471 processor machines. On a single processor machine, the kernel will 1472 run faster if you say N here. 1473 1474 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1475 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1476 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1477 1478 If you don't know what to do here, say N. 1479 1480config SMP_ON_UP 1481 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" 1482 depends on EXPERIMENTAL 1483 depends on SMP && !XIP_KERNEL 1484 default y 1485 help 1486 SMP kernels contain instructions which fail on non-SMP processors. 1487 Enabling this option allows the kernel to modify itself to make 1488 these instructions safe. Disabling it allows about 1K of space 1489 savings. 1490 1491 If you don't know what to do here, say Y. 1492 1493config ARM_CPU_TOPOLOGY 1494 bool "Support cpu topology definition" 1495 depends on SMP && CPU_V7 1496 default y 1497 help 1498 Support ARM cpu topology definition. The MPIDR register defines 1499 affinity between processors which is then used to describe the cpu 1500 topology of an ARM System. 1501 1502config SCHED_MC 1503 bool "Multi-core scheduler support" 1504 depends on ARM_CPU_TOPOLOGY 1505 help 1506 Multi-core scheduler support improves the CPU scheduler's decision 1507 making when dealing with multi-core CPU chips at a cost of slightly 1508 increased overhead in some places. If unsure say N here. 1509 1510config SCHED_SMT 1511 bool "SMT scheduler support" 1512 depends on ARM_CPU_TOPOLOGY 1513 help 1514 Improves the CPU scheduler's decision making when dealing with 1515 MultiThreading at a cost of slightly increased overhead in some 1516 places. If unsure say N here. 1517 1518config HAVE_ARM_SCU 1519 bool 1520 help 1521 This option enables support for the ARM system coherency unit 1522 1523config HAVE_ARM_TWD 1524 bool 1525 depends on SMP 1526 select TICK_ONESHOT 1527 help 1528 This options enables support for the ARM timer and watchdog unit 1529 1530choice 1531 prompt "Memory split" 1532 default VMSPLIT_3G 1533 help 1534 Select the desired split between kernel and user memory. 1535 1536 If you are not absolutely sure what you are doing, leave this 1537 option alone! 1538 1539 config VMSPLIT_3G 1540 bool "3G/1G user/kernel split" 1541 config VMSPLIT_2G 1542 bool "2G/2G user/kernel split" 1543 config VMSPLIT_1G 1544 bool "1G/3G user/kernel split" 1545endchoice 1546 1547config PAGE_OFFSET 1548 hex 1549 default 0x40000000 if VMSPLIT_1G 1550 default 0x80000000 if VMSPLIT_2G 1551 default 0xC0000000 1552 1553config NR_CPUS 1554 int "Maximum number of CPUs (2-32)" 1555 range 2 32 1556 depends on SMP 1557 default "4" 1558 1559config HOTPLUG_CPU 1560 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)" 1561 depends on SMP && HOTPLUG && EXPERIMENTAL 1562 help 1563 Say Y here to experiment with turning CPUs off and on. CPUs 1564 can be controlled through /sys/devices/system/cpu. 1565 1566config LOCAL_TIMERS 1567 bool "Use local timer interrupts" 1568 depends on SMP 1569 default y 1570 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT) 1571 help 1572 Enable support for local timers on SMP platforms, rather then the 1573 legacy IPI broadcast method. Local timers allows the system 1574 accounting to be spread across the timer interval, preventing a 1575 "thundering herd" at every timer tick. 1576 1577config ARCH_NR_GPIO 1578 int 1579 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA 1580 default 350 if ARCH_U8500 1581 default 0 1582 help 1583 Maximum number of GPIOs in the system. 1584 1585 If unsure, leave the default value. 1586 1587source kernel/Kconfig.preempt 1588 1589config HZ 1590 int 1591 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \ 1592 ARCH_S5PV210 || ARCH_EXYNOS4 1593 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER 1594 default AT91_TIMER_HZ if ARCH_AT91 1595 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE 1596 default 100 1597 1598config THUMB2_KERNEL 1599 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)" 1600 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL 1601 select AEABI 1602 select ARM_ASM_UNIFIED 1603 select ARM_UNWIND 1604 help 1605 By enabling this option, the kernel will be compiled in 1606 Thumb-2 mode. A compiler/assembler that understand the unified 1607 ARM-Thumb syntax is needed. 1608 1609 If unsure, say N. 1610 1611config THUMB2_AVOID_R_ARM_THM_JUMP11 1612 bool "Work around buggy Thumb-2 short branch relocations in gas" 1613 depends on THUMB2_KERNEL && MODULES 1614 default y 1615 help 1616 Various binutils versions can resolve Thumb-2 branches to 1617 locally-defined, preemptible global symbols as short-range "b.n" 1618 branch instructions. 1619 1620 This is a problem, because there's no guarantee the final 1621 destination of the symbol, or any candidate locations for a 1622 trampoline, are within range of the branch. For this reason, the 1623 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1624 relocation in modules at all, and it makes little sense to add 1625 support. 1626 1627 The symptom is that the kernel fails with an "unsupported 1628 relocation" error when loading some modules. 1629 1630 Until fixed tools are available, passing 1631 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1632 code which hits this problem, at the cost of a bit of extra runtime 1633 stack usage in some cases. 1634 1635 The problem is described in more detail at: 1636 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1637 1638 Only Thumb-2 kernels are affected. 1639 1640 Unless you are sure your tools don't have this problem, say Y. 1641 1642config ARM_ASM_UNIFIED 1643 bool 1644 1645config AEABI 1646 bool "Use the ARM EABI to compile the kernel" 1647 help 1648 This option allows for the kernel to be compiled using the latest 1649 ARM ABI (aka EABI). This is only useful if you are using a user 1650 space environment that is also compiled with EABI. 1651 1652 Since there are major incompatibilities between the legacy ABI and 1653 EABI, especially with regard to structure member alignment, this 1654 option also changes the kernel syscall calling convention to 1655 disambiguate both ABIs and allow for backward compatibility support 1656 (selected with CONFIG_OABI_COMPAT). 1657 1658 To use this you need GCC version 4.0.0 or later. 1659 1660config OABI_COMPAT 1661 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1662 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL 1663 default y 1664 help 1665 This option preserves the old syscall interface along with the 1666 new (ARM EABI) one. It also provides a compatibility layer to 1667 intercept syscalls that have structure arguments which layout 1668 in memory differs between the legacy ABI and the new ARM EABI 1669 (only for non "thumb" binaries). This option adds a tiny 1670 overhead to all syscalls and produces a slightly larger kernel. 1671 If you know you'll be using only pure EABI user space then you 1672 can say N here. If this option is not selected and you attempt 1673 to execute a legacy ABI binary then the result will be 1674 UNPREDICTABLE (in fact it can be predicted that it won't work 1675 at all). If in doubt say Y. 1676 1677config ARCH_HAS_HOLES_MEMORYMODEL 1678 bool 1679 1680config ARCH_SPARSEMEM_ENABLE 1681 bool 1682 1683config ARCH_SPARSEMEM_DEFAULT 1684 def_bool ARCH_SPARSEMEM_ENABLE 1685 1686config ARCH_SELECT_MEMORY_MODEL 1687 def_bool ARCH_SPARSEMEM_ENABLE 1688 1689config HAVE_ARCH_PFN_VALID 1690 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1691 1692config HIGHMEM 1693 bool "High Memory Support" 1694 depends on MMU 1695 help 1696 The address space of ARM processors is only 4 Gigabytes large 1697 and it has to accommodate user address space, kernel address 1698 space as well as some memory mapped IO. That means that, if you 1699 have a large amount of physical memory and/or IO, not all of the 1700 memory can be "permanently mapped" by the kernel. The physical 1701 memory that is not permanently mapped is called "high memory". 1702 1703 Depending on the selected kernel/user memory split, minimum 1704 vmalloc space and actual amount of RAM, you may not need this 1705 option which should result in a slightly faster kernel. 1706 1707 If unsure, say n. 1708 1709config HIGHPTE 1710 bool "Allocate 2nd-level pagetables from highmem" 1711 depends on HIGHMEM 1712 1713config HW_PERF_EVENTS 1714 bool "Enable hardware performance counter support for perf events" 1715 depends on PERF_EVENTS && CPU_HAS_PMU 1716 default y 1717 help 1718 Enable hardware performance counter support for perf events. If 1719 disabled, perf events will use software events only. 1720 1721source "mm/Kconfig" 1722 1723config FORCE_MAX_ZONEORDER 1724 int "Maximum zone order" if ARCH_SHMOBILE 1725 range 11 64 if ARCH_SHMOBILE 1726 default "9" if SA1111 1727 default "11" 1728 help 1729 The kernel memory allocator divides physically contiguous memory 1730 blocks into "zones", where each zone is a power of two number of 1731 pages. This option selects the largest power of two that the kernel 1732 keeps in the memory allocator. If you need to allocate very large 1733 blocks of physically contiguous memory, then you may need to 1734 increase this value. 1735 1736 This config option is actually maximum order plus one. For example, 1737 a value of 11 means that the largest free memory block is 2^10 pages. 1738 1739config LEDS 1740 bool "Timer and CPU usage LEDs" 1741 depends on ARCH_CDB89712 || ARCH_EBSA110 || \ 1742 ARCH_EBSA285 || ARCH_INTEGRATOR || \ 1743 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ 1744 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ 1745 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ 1746 ARCH_AT91 || ARCH_DAVINCI || \ 1747 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW 1748 help 1749 If you say Y here, the LEDs on your machine will be used 1750 to provide useful information about your current system status. 1751 1752 If you are compiling a kernel for a NetWinder or EBSA-285, you will 1753 be able to select which LEDs are active using the options below. If 1754 you are compiling a kernel for the EBSA-110 or the LART however, the 1755 red LED will simply flash regularly to indicate that the system is 1756 still functional. It is safe to say Y here if you have a CATS 1757 system, but the driver will do nothing. 1758 1759config LEDS_TIMER 1760 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \ 1761 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ 1762 || MACH_OMAP_PERSEUS2 1763 depends on LEDS 1764 depends on !GENERIC_CLOCKEVENTS 1765 default y if ARCH_EBSA110 1766 help 1767 If you say Y here, one of the system LEDs (the green one on the 1768 NetWinder, the amber one on the EBSA285, or the red one on the LART) 1769 will flash regularly to indicate that the system is still 1770 operational. This is mainly useful to kernel hackers who are 1771 debugging unstable kernels. 1772 1773 The LART uses the same LED for both Timer LED and CPU usage LED 1774 functions. You may choose to use both, but the Timer LED function 1775 will overrule the CPU usage LED. 1776 1777config LEDS_CPU 1778 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \ 1779 !ARCH_OMAP) \ 1780 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ 1781 || MACH_OMAP_PERSEUS2 1782 depends on LEDS 1783 help 1784 If you say Y here, the red LED will be used to give a good real 1785 time indication of CPU usage, by lighting whenever the idle task 1786 is not currently executing. 1787 1788 The LART uses the same LED for both Timer LED and CPU usage LED 1789 functions. You may choose to use both, but the Timer LED function 1790 will overrule the CPU usage LED. 1791 1792config ALIGNMENT_TRAP 1793 bool 1794 depends on CPU_CP15_MMU 1795 default y if !ARCH_EBSA110 1796 select HAVE_PROC_CPU if PROC_FS 1797 help 1798 ARM processors cannot fetch/store information which is not 1799 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1800 address divisible by 4. On 32-bit ARM processors, these non-aligned 1801 fetch/store instructions will be emulated in software if you say 1802 here, which has a severe performance impact. This is necessary for 1803 correct operation of some network protocols. With an IP-only 1804 configuration it is safe to say N, otherwise say Y. 1805 1806config UACCESS_WITH_MEMCPY 1807 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)" 1808 depends on MMU && EXPERIMENTAL 1809 default y if CPU_FEROCEON 1810 help 1811 Implement faster copy_to_user and clear_user methods for CPU 1812 cores where a 8-word STM instruction give significantly higher 1813 memory write throughput than a sequence of individual 32bit stores. 1814 1815 A possible side effect is a slight increase in scheduling latency 1816 between threads sharing the same address space if they invoke 1817 such copy operations with large buffers. 1818 1819 However, if the CPU data cache is using a write-allocate mode, 1820 this option is unlikely to provide any performance gain. 1821 1822config SECCOMP 1823 bool 1824 prompt "Enable seccomp to safely compute untrusted bytecode" 1825 ---help--- 1826 This kernel feature is useful for number crunching applications 1827 that may need to compute untrusted bytecode during their 1828 execution. By using pipes or other transports made available to 1829 the process as file descriptors supporting the read/write 1830 syscalls, it's possible to isolate those applications in 1831 their own address space using seccomp. Once seccomp is 1832 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1833 and the task is only allowed to execute a few safe syscalls 1834 defined by each seccomp mode. 1835 1836config CC_STACKPROTECTOR 1837 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" 1838 depends on EXPERIMENTAL 1839 help 1840 This option turns on the -fstack-protector GCC feature. This 1841 feature puts, at the beginning of functions, a canary value on 1842 the stack just before the return address, and validates 1843 the value just before actually returning. Stack based buffer 1844 overflows (that need to overwrite this return address) now also 1845 overwrite the canary, which gets detected and the attack is then 1846 neutralized via a kernel panic. 1847 This feature requires gcc version 4.2 or above. 1848 1849config DEPRECATED_PARAM_STRUCT 1850 bool "Provide old way to pass kernel parameters" 1851 help 1852 This was deprecated in 2001 and announced to live on for 5 years. 1853 Some old boot loaders still use this way. 1854 1855endmenu 1856 1857menu "Boot options" 1858 1859config USE_OF 1860 bool "Flattened Device Tree support" 1861 select OF 1862 select OF_EARLY_FLATTREE 1863 select IRQ_DOMAIN 1864 help 1865 Include support for flattened device tree machine descriptions. 1866 1867# Compressed boot loader in ROM. Yes, we really want to ask about 1868# TEXT and BSS so we preserve their values in the config files. 1869config ZBOOT_ROM_TEXT 1870 hex "Compressed ROM boot loader base address" 1871 default "0" 1872 help 1873 The physical address at which the ROM-able zImage is to be 1874 placed in the target. Platforms which normally make use of 1875 ROM-able zImage formats normally set this to a suitable 1876 value in their defconfig file. 1877 1878 If ZBOOT_ROM is not enabled, this has no effect. 1879 1880config ZBOOT_ROM_BSS 1881 hex "Compressed ROM boot loader BSS address" 1882 default "0" 1883 help 1884 The base address of an area of read/write memory in the target 1885 for the ROM-able zImage which must be available while the 1886 decompressor is running. It must be large enough to hold the 1887 entire decompressed kernel plus an additional 128 KiB. 1888 Platforms which normally make use of ROM-able zImage formats 1889 normally set this to a suitable value in their defconfig file. 1890 1891 If ZBOOT_ROM is not enabled, this has no effect. 1892 1893config ZBOOT_ROM 1894 bool "Compressed boot loader in ROM/flash" 1895 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1896 help 1897 Say Y here if you intend to execute your compressed kernel image 1898 (zImage) directly from ROM or flash. If unsure, say N. 1899 1900choice 1901 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)" 1902 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL 1903 default ZBOOT_ROM_NONE 1904 help 1905 Include experimental SD/MMC loading code in the ROM-able zImage. 1906 With this enabled it is possible to write the the ROM-able zImage 1907 kernel image to an MMC or SD card and boot the kernel straight 1908 from the reset vector. At reset the processor Mask ROM will load 1909 the first part of the the ROM-able zImage which in turn loads the 1910 rest the kernel image to RAM. 1911 1912config ZBOOT_ROM_NONE 1913 bool "No SD/MMC loader in zImage (EXPERIMENTAL)" 1914 help 1915 Do not load image from SD or MMC 1916 1917config ZBOOT_ROM_MMCIF 1918 bool "Include MMCIF loader in zImage (EXPERIMENTAL)" 1919 help 1920 Load image from MMCIF hardware block. 1921 1922config ZBOOT_ROM_SH_MOBILE_SDHI 1923 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)" 1924 help 1925 Load image from SDHI hardware block 1926 1927endchoice 1928 1929config ARM_APPENDED_DTB 1930 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1931 depends on OF && !ZBOOT_ROM && EXPERIMENTAL 1932 help 1933 With this option, the boot code will look for a device tree binary 1934 (DTB) appended to zImage 1935 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1936 1937 This is meant as a backward compatibility convenience for those 1938 systems with a bootloader that can't be upgraded to accommodate 1939 the documented boot protocol using a device tree. 1940 1941 Beware that there is very little in terms of protection against 1942 this option being confused by leftover garbage in memory that might 1943 look like a DTB header after a reboot if no actual DTB is appended 1944 to zImage. Do not leave this option active in a production kernel 1945 if you don't intend to always append a DTB. Proper passing of the 1946 location into r2 of a bootloader provided DTB is always preferable 1947 to this option. 1948 1949config ARM_ATAG_DTB_COMPAT 1950 bool "Supplement the appended DTB with traditional ATAG information" 1951 depends on ARM_APPENDED_DTB 1952 help 1953 Some old bootloaders can't be updated to a DTB capable one, yet 1954 they provide ATAGs with memory configuration, the ramdisk address, 1955 the kernel cmdline string, etc. Such information is dynamically 1956 provided by the bootloader and can't always be stored in a static 1957 DTB. To allow a device tree enabled kernel to be used with such 1958 bootloaders, this option allows zImage to extract the information 1959 from the ATAG list and store it at run time into the appended DTB. 1960 1961config CMDLINE 1962 string "Default kernel command string" 1963 default "" 1964 help 1965 On some architectures (EBSA110 and CATS), there is currently no way 1966 for the boot loader to pass arguments to the kernel. For these 1967 architectures, you should supply some command-line options at build 1968 time by entering them here. As a minimum, you should specify the 1969 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1970 1971choice 1972 prompt "Kernel command line type" if CMDLINE != "" 1973 default CMDLINE_FROM_BOOTLOADER 1974 1975config CMDLINE_FROM_BOOTLOADER 1976 bool "Use bootloader kernel arguments if available" 1977 help 1978 Uses the command-line options passed by the boot loader. If 1979 the boot loader doesn't provide any, the default kernel command 1980 string provided in CMDLINE will be used. 1981 1982config CMDLINE_EXTEND 1983 bool "Extend bootloader kernel arguments" 1984 help 1985 The command-line arguments provided by the boot loader will be 1986 appended to the default kernel command string. 1987 1988config CMDLINE_FORCE 1989 bool "Always use the default kernel command string" 1990 help 1991 Always use the default kernel command string, even if the boot 1992 loader passes other arguments to the kernel. 1993 This is useful if you cannot or don't want to change the 1994 command-line options your boot loader passes to the kernel. 1995endchoice 1996 1997config XIP_KERNEL 1998 bool "Kernel Execute-In-Place from ROM" 1999 depends on !ZBOOT_ROM && !ARM_LPAE 2000 help 2001 Execute-In-Place allows the kernel to run from non-volatile storage 2002 directly addressable by the CPU, such as NOR flash. This saves RAM 2003 space since the text section of the kernel is not loaded from flash 2004 to RAM. Read-write sections, such as the data section and stack, 2005 are still copied to RAM. The XIP kernel is not compressed since 2006 it has to run directly from flash, so it will take more space to 2007 store it. The flash address used to link the kernel object files, 2008 and for storing it, is configuration dependent. Therefore, if you 2009 say Y here, you must know the proper physical address where to 2010 store the kernel image depending on your own flash memory usage. 2011 2012 Also note that the make target becomes "make xipImage" rather than 2013 "make zImage" or "make Image". The final kernel binary to put in 2014 ROM memory will be arch/arm/boot/xipImage. 2015 2016 If unsure, say N. 2017 2018config XIP_PHYS_ADDR 2019 hex "XIP Kernel Physical Location" 2020 depends on XIP_KERNEL 2021 default "0x00080000" 2022 help 2023 This is the physical address in your flash memory the kernel will 2024 be linked for and stored to. This address is dependent on your 2025 own flash usage. 2026 2027config KEXEC 2028 bool "Kexec system call (EXPERIMENTAL)" 2029 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU) 2030 help 2031 kexec is a system call that implements the ability to shutdown your 2032 current kernel, and to start another kernel. It is like a reboot 2033 but it is independent of the system firmware. And like a reboot 2034 you can start any kernel with it, not just Linux. 2035 2036 It is an ongoing process to be certain the hardware in a machine 2037 is properly shutdown, so do not be surprised if this code does not 2038 initially work for you. It may help to enable device hotplugging 2039 support. 2040 2041config ATAGS_PROC 2042 bool "Export atags in procfs" 2043 depends on KEXEC 2044 default y 2045 help 2046 Should the atags used to boot the kernel be exported in an "atags" 2047 file in procfs. Useful with kexec. 2048 2049config CRASH_DUMP 2050 bool "Build kdump crash kernel (EXPERIMENTAL)" 2051 depends on EXPERIMENTAL 2052 help 2053 Generate crash dump after being started by kexec. This should 2054 be normally only set in special crash dump kernels which are 2055 loaded in the main kernel with kexec-tools into a specially 2056 reserved region and then later executed after a crash by 2057 kdump/kexec. The crash dump kernel must be compiled to a 2058 memory address not used by the main kernel 2059 2060 For more details see Documentation/kdump/kdump.txt 2061 2062config AUTO_ZRELADDR 2063 bool "Auto calculation of the decompressed kernel image address" 2064 depends on !ZBOOT_ROM && !ARCH_U300 2065 help 2066 ZRELADDR is the physical address where the decompressed kernel 2067 image will be placed. If AUTO_ZRELADDR is selected, the address 2068 will be determined at run-time by masking the current IP with 2069 0xf8000000. This assumes the zImage being placed in the first 128MB 2070 from start of memory. 2071 2072endmenu 2073 2074menu "CPU Power Management" 2075 2076if ARCH_HAS_CPUFREQ 2077 2078source "drivers/cpufreq/Kconfig" 2079 2080config CPU_FREQ_IMX 2081 tristate "CPUfreq driver for i.MX CPUs" 2082 depends on ARCH_MXC && CPU_FREQ 2083 help 2084 This enables the CPUfreq driver for i.MX CPUs. 2085 2086config CPU_FREQ_SA1100 2087 bool 2088 2089config CPU_FREQ_SA1110 2090 bool 2091 2092config CPU_FREQ_INTEGRATOR 2093 tristate "CPUfreq driver for ARM Integrator CPUs" 2094 depends on ARCH_INTEGRATOR && CPU_FREQ 2095 default y 2096 help 2097 This enables the CPUfreq driver for ARM Integrator CPUs. 2098 2099 For details, take a look at <file:Documentation/cpu-freq>. 2100 2101 If in doubt, say Y. 2102 2103config CPU_FREQ_PXA 2104 bool 2105 depends on CPU_FREQ && ARCH_PXA && PXA25x 2106 default y 2107 select CPU_FREQ_TABLE 2108 select CPU_FREQ_DEFAULT_GOV_USERSPACE 2109 2110config CPU_FREQ_S3C 2111 bool 2112 help 2113 Internal configuration node for common cpufreq on Samsung SoC 2114 2115config CPU_FREQ_S3C24XX 2116 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)" 2117 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL 2118 select CPU_FREQ_S3C 2119 help 2120 This enables the CPUfreq driver for the Samsung S3C24XX family 2121 of CPUs. 2122 2123 For details, take a look at <file:Documentation/cpu-freq>. 2124 2125 If in doubt, say N. 2126 2127config CPU_FREQ_S3C24XX_PLL 2128 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" 2129 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL 2130 help 2131 Compile in support for changing the PLL frequency from the 2132 S3C24XX series CPUfreq driver. The PLL takes time to settle 2133 after a frequency change, so by default it is not enabled. 2134 2135 This also means that the PLL tables for the selected CPU(s) will 2136 be built which may increase the size of the kernel image. 2137 2138config CPU_FREQ_S3C24XX_DEBUG 2139 bool "Debug CPUfreq Samsung driver core" 2140 depends on CPU_FREQ_S3C24XX 2141 help 2142 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core 2143 2144config CPU_FREQ_S3C24XX_IODEBUG 2145 bool "Debug CPUfreq Samsung driver IO timing" 2146 depends on CPU_FREQ_S3C24XX 2147 help 2148 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core 2149 2150config CPU_FREQ_S3C24XX_DEBUGFS 2151 bool "Export debugfs for CPUFreq" 2152 depends on CPU_FREQ_S3C24XX && DEBUG_FS 2153 help 2154 Export status information via debugfs. 2155 2156endif 2157 2158source "drivers/cpuidle/Kconfig" 2159 2160endmenu 2161 2162menu "Floating point emulation" 2163 2164comment "At least one emulation must be selected" 2165 2166config FPE_NWFPE 2167 bool "NWFPE math emulation" 2168 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2169 ---help--- 2170 Say Y to include the NWFPE floating point emulator in the kernel. 2171 This is necessary to run most binaries. Linux does not currently 2172 support floating point hardware so you need to say Y here even if 2173 your machine has an FPA or floating point co-processor podule. 2174 2175 You may say N here if you are going to load the Acorn FPEmulator 2176 early in the bootup. 2177 2178config FPE_NWFPE_XP 2179 bool "Support extended precision" 2180 depends on FPE_NWFPE 2181 help 2182 Say Y to include 80-bit support in the kernel floating-point 2183 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2184 Note that gcc does not generate 80-bit operations by default, 2185 so in most cases this option only enlarges the size of the 2186 floating point emulator without any good reason. 2187 2188 You almost surely want to say N here. 2189 2190config FPE_FASTFPE 2191 bool "FastFPE math emulation (EXPERIMENTAL)" 2192 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL 2193 ---help--- 2194 Say Y here to include the FAST floating point emulator in the kernel. 2195 This is an experimental much faster emulator which now also has full 2196 precision for the mantissa. It does not support any exceptions. 2197 It is very simple, and approximately 3-6 times faster than NWFPE. 2198 2199 It should be sufficient for most programs. It may be not suitable 2200 for scientific calculations, but you have to check this for yourself. 2201 If you do not feel you need a faster FP emulation you should better 2202 choose NWFPE. 2203 2204config VFP 2205 bool "VFP-format floating point maths" 2206 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2207 help 2208 Say Y to include VFP support code in the kernel. This is needed 2209 if your hardware includes a VFP unit. 2210 2211 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2212 release notes and additional status information. 2213 2214 Say N if your target does not have VFP hardware. 2215 2216config VFPv3 2217 bool 2218 depends on VFP 2219 default y if CPU_V7 2220 2221config NEON 2222 bool "Advanced SIMD (NEON) Extension support" 2223 depends on VFPv3 && CPU_V7 2224 help 2225 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2226 Extension. 2227 2228endmenu 2229 2230menu "Userspace binary formats" 2231 2232source "fs/Kconfig.binfmt" 2233 2234config ARTHUR 2235 tristate "RISC OS personality" 2236 depends on !AEABI 2237 help 2238 Say Y here to include the kernel code necessary if you want to run 2239 Acorn RISC OS/Arthur binaries under Linux. This code is still very 2240 experimental; if this sounds frightening, say N and sleep in peace. 2241 You can also say M here to compile this support as a module (which 2242 will be called arthur). 2243 2244endmenu 2245 2246menu "Power management options" 2247 2248source "kernel/power/Kconfig" 2249 2250config ARCH_SUSPEND_POSSIBLE 2251 depends on !ARCH_S5PC100 2252 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ 2253 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE 2254 def_bool y 2255 2256config ARM_CPU_SUSPEND 2257 def_bool PM_SLEEP 2258 2259endmenu 2260 2261source "net/Kconfig" 2262 2263source "drivers/Kconfig" 2264 2265source "fs/Kconfig" 2266 2267source "arch/arm/Kconfig.debug" 2268 2269source "security/Kconfig" 2270 2271source "crypto/Kconfig" 2272 2273source "lib/Kconfig" 2274