1* ARM Performance Monitor Units
2
3ARM cores often have a PMU for counting cpu and cache events like cache misses
4and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
5representation in the device tree should be done as under:-
6
7Required properties:
8
9- compatible : should be one of
10	"arm,cortex-a9-pmu"
11	"arm,cortex-a8-pmu"
12	"arm,arm1176-pmu"
13	"arm,arm1136-pmu"
14- interrupts : 1 combined interrupt or 1 per core.
15
16Example:
17
18pmu {
19        compatible = "arm,cortex-a9-pmu";
20        interrupts = <100 101>;
21};
22