1* ARM L2 Cache Controller
2
3ARM cores often have a separate level 2 cache controller. There are various
4implementations of the L2 cache controller with compatible programming models.
5The ARM L2 cache representation in the device tree should be done as follows:
6
7Required properties:
8
9- compatible : should be one of:
10	"arm,pl310-cache"
11	"arm,l220-cache"
12	"arm,l210-cache"
13- cache-unified : Specifies the cache is a unified cache.
14- cache-level : Should be set to 2 for a level 2 cache.
15- reg : Physical base address and size of cache controller's memory mapped
16  registers.
17
18Optional properties:
19
20- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of
21  read, write and setup latencies. Minimum valid values are 1. Controllers
22  without setup latency control should use a value of 0.
23- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of
24  read, write and setup latencies. Controllers without setup latency control
25  should use 0. Controllers without separate read and write Tag RAM latency
26  values should only use the first cell.
27- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
28- arm,filter-ranges : <start length> Starting address and length of window to
29  filter. Addresses in the filter window are directed to the M1 port. Other
30  addresses will go to the M0 port.
31- interrupts : 1 combined interrupt.
32
33Example:
34
35L2: cache-controller {
36        compatible = "arm,pl310-cache";
37        reg = <0xfff12000 0x1000>;
38        arm,data-latency = <1 1 1>;
39        arm,tag-latency = <2 2 2>;
40        arm,filter-latency = <0x80000000 0x8000000>;
41        cache-unified;
42        cache-level = <2>;
43	interrupts = <45>;
44};
45