1 #include "kvm/devices.h" 2 #include "kvm/pci.h" 3 #include "kvm/ioport.h" 4 #include "kvm/irq.h" 5 #include "kvm/util.h" 6 #include "kvm/kvm.h" 7 8 #include <linux/err.h> 9 #include <assert.h> 10 11 static u32 pci_config_address_bits; 12 13 /* This is within our PCI gap - in an unused area. 14 * Note this is a PCI *bus address*, is used to assign BARs etc.! 15 * (That's why it can still 32bit even with 64bit guests-- 64bit 16 * PCI isn't currently supported.) 17 */ 18 static u32 io_space_blocks = KVM_PCI_MMIO_AREA; 19 20 /* 21 * BARs must be naturally aligned, so enforce this in the allocator. 22 */ 23 u32 pci_get_io_space_block(u32 size) 24 { 25 u32 block = ALIGN(io_space_blocks, size); 26 io_space_blocks = block + size; 27 return block; 28 } 29 30 void *pci_find_cap(struct pci_device_header *hdr, u8 cap_type) 31 { 32 u8 pos; 33 struct pci_cap_hdr *cap; 34 35 pci_for_each_cap(pos, cap, hdr) { 36 if (cap->type == cap_type) 37 return cap; 38 } 39 40 return NULL; 41 } 42 43 void pci__assign_irq(struct device_header *dev_hdr) 44 { 45 struct pci_device_header *pci_hdr = dev_hdr->data; 46 47 /* 48 * PCI supports only INTA#,B#,C#,D# per device. 49 * 50 * A#,B#,C#,D# are allowed for multifunctional devices so stick 51 * with A# for our single function devices. 52 */ 53 pci_hdr->irq_pin = 1; 54 pci_hdr->irq_line = irq__alloc_line(); 55 56 if (!pci_hdr->irq_type) 57 pci_hdr->irq_type = IRQ_TYPE_EDGE_RISING; 58 } 59 60 static void *pci_config_address_ptr(u16 port) 61 { 62 unsigned long offset; 63 void *base; 64 65 offset = port - PCI_CONFIG_ADDRESS; 66 base = &pci_config_address_bits; 67 68 return base + offset; 69 } 70 71 static bool pci_config_address_out(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size) 72 { 73 void *p = pci_config_address_ptr(port); 74 75 memcpy(p, data, size); 76 77 return true; 78 } 79 80 static bool pci_config_address_in(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size) 81 { 82 void *p = pci_config_address_ptr(port); 83 84 memcpy(data, p, size); 85 86 return true; 87 } 88 89 static struct ioport_operations pci_config_address_ops = { 90 .io_in = pci_config_address_in, 91 .io_out = pci_config_address_out, 92 }; 93 94 static bool pci_device_exists(u8 bus_number, u8 device_number, u8 function_number) 95 { 96 union pci_config_address pci_config_address; 97 98 pci_config_address.w = ioport__read32(&pci_config_address_bits); 99 100 if (pci_config_address.bus_number != bus_number) 101 return false; 102 103 if (pci_config_address.function_number != function_number) 104 return false; 105 106 return !IS_ERR_OR_NULL(device__find_dev(DEVICE_BUS_PCI, device_number)); 107 } 108 109 static bool pci_config_data_out(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size) 110 { 111 union pci_config_address pci_config_address; 112 113 pci_config_address.w = ioport__read32(&pci_config_address_bits); 114 /* 115 * If someone accesses PCI configuration space offsets that are not 116 * aligned to 4 bytes, it uses ioports to signify that. 117 */ 118 pci_config_address.reg_offset = port - PCI_CONFIG_DATA; 119 120 pci__config_wr(vcpu->kvm, pci_config_address, data, size); 121 122 return true; 123 } 124 125 static bool pci_config_data_in(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size) 126 { 127 union pci_config_address pci_config_address; 128 129 pci_config_address.w = ioport__read32(&pci_config_address_bits); 130 /* 131 * If someone accesses PCI configuration space offsets that are not 132 * aligned to 4 bytes, it uses ioports to signify that. 133 */ 134 pci_config_address.reg_offset = port - PCI_CONFIG_DATA; 135 136 pci__config_rd(vcpu->kvm, pci_config_address, data, size); 137 138 return true; 139 } 140 141 static struct ioport_operations pci_config_data_ops = { 142 .io_in = pci_config_data_in, 143 .io_out = pci_config_data_out, 144 }; 145 146 void pci__config_wr(struct kvm *kvm, union pci_config_address addr, void *data, int size) 147 { 148 void *base; 149 u8 bar, offset; 150 struct pci_device_header *pci_hdr; 151 u8 dev_num = addr.device_number; 152 u32 value = 0; 153 u32 mask; 154 155 if (!pci_device_exists(addr.bus_number, dev_num, 0)) 156 return; 157 158 offset = addr.w & PCI_DEV_CFG_MASK; 159 base = pci_hdr = device__find_dev(DEVICE_BUS_PCI, dev_num)->data; 160 161 if (pci_hdr->cfg_ops.write) 162 pci_hdr->cfg_ops.write(kvm, pci_hdr, offset, data, size); 163 164 /* 165 * legacy hack: ignore writes to uninitialized regions (e.g. ROM BAR). 166 * Not very nice but has been working so far. 167 */ 168 if (*(u32 *)(base + offset) == 0) 169 return; 170 171 bar = (offset - PCI_BAR_OFFSET(0)) / sizeof(u32); 172 173 /* 174 * If the kernel masks the BAR, it will expect to find the size of the 175 * BAR there next time it reads from it. After the kernel reads the 176 * size, it will write the address back. 177 */ 178 if (bar < 6) { 179 if (pci_hdr->bar[bar] & PCI_BASE_ADDRESS_SPACE_IO) 180 mask = (u32)PCI_BASE_ADDRESS_IO_MASK; 181 else 182 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; 183 /* 184 * According to the PCI local bus specification REV 3.0: 185 * The number of upper bits that a device actually implements 186 * depends on how much of the address space the device will 187 * respond to. A device that wants a 1 MB memory address space 188 * (using a 32-bit base address register) would build the top 189 * 12 bits of the address register, hardwiring the other bits 190 * to 0. 191 * 192 * Furthermore, software can determine how much address space 193 * the device requires by writing a value of all 1's to the 194 * register and then reading the value back. The device will 195 * return 0's in all don't-care address bits, effectively 196 * specifying the address space required. 197 * 198 * Software computes the size of the address space with the 199 * formula S = ~B + 1, where S is the memory size and B is the 200 * value read from the BAR. This means that the BAR value that 201 * kvmtool should return is B = ~(S - 1). 202 */ 203 memcpy(&value, data, size); 204 if (value == 0xffffffff) 205 value = ~(pci_hdr->bar_size[bar] - 1); 206 /* Preserve the special bits. */ 207 value = (value & mask) | (pci_hdr->bar[bar] & ~mask); 208 memcpy(base + offset, &value, size); 209 } else { 210 memcpy(base + offset, data, size); 211 } 212 } 213 214 void pci__config_rd(struct kvm *kvm, union pci_config_address addr, void *data, int size) 215 { 216 u8 offset; 217 struct pci_device_header *pci_hdr; 218 u8 dev_num = addr.device_number; 219 220 if (pci_device_exists(addr.bus_number, dev_num, 0)) { 221 pci_hdr = device__find_dev(DEVICE_BUS_PCI, dev_num)->data; 222 offset = addr.w & PCI_DEV_CFG_MASK; 223 224 if (pci_hdr->cfg_ops.read) 225 pci_hdr->cfg_ops.read(kvm, pci_hdr, offset, data, size); 226 227 memcpy(data, (void *)pci_hdr + offset, size); 228 } else { 229 memset(data, 0xff, size); 230 } 231 } 232 233 static void pci_config_mmio_access(struct kvm_cpu *vcpu, u64 addr, u8 *data, 234 u32 len, u8 is_write, void *kvm) 235 { 236 union pci_config_address cfg_addr; 237 238 addr -= KVM_PCI_CFG_AREA; 239 cfg_addr.w = (u32)addr; 240 cfg_addr.enable_bit = 1; 241 242 if (is_write) 243 pci__config_wr(kvm, cfg_addr, data, len); 244 else 245 pci__config_rd(kvm, cfg_addr, data, len); 246 } 247 248 struct pci_device_header *pci__find_dev(u8 dev_num) 249 { 250 struct device_header *hdr = device__find_dev(DEVICE_BUS_PCI, dev_num); 251 252 if (IS_ERR_OR_NULL(hdr)) 253 return NULL; 254 255 return hdr->data; 256 } 257 258 int pci__init(struct kvm *kvm) 259 { 260 int r; 261 262 r = ioport__register(kvm, PCI_CONFIG_DATA + 0, &pci_config_data_ops, 4, NULL); 263 if (r < 0) 264 return r; 265 266 r = ioport__register(kvm, PCI_CONFIG_ADDRESS + 0, &pci_config_address_ops, 4, NULL); 267 if (r < 0) 268 goto err_unregister_data; 269 270 r = kvm__register_mmio(kvm, KVM_PCI_CFG_AREA, PCI_CFG_SIZE, false, 271 pci_config_mmio_access, kvm); 272 if (r < 0) 273 goto err_unregister_addr; 274 275 return 0; 276 277 err_unregister_addr: 278 ioport__unregister(kvm, PCI_CONFIG_ADDRESS); 279 err_unregister_data: 280 ioport__unregister(kvm, PCI_CONFIG_DATA); 281 return r; 282 } 283 dev_base_init(pci__init); 284 285 int pci__exit(struct kvm *kvm) 286 { 287 ioport__unregister(kvm, PCI_CONFIG_DATA); 288 ioport__unregister(kvm, PCI_CONFIG_ADDRESS); 289 290 return 0; 291 } 292 dev_base_exit(pci__exit); 293