1 #include "kvm/devices.h" 2 #include "kvm/pci.h" 3 #include "kvm/ioport.h" 4 #include "kvm/irq.h" 5 #include "kvm/util.h" 6 #include "kvm/kvm.h" 7 8 #include <linux/err.h> 9 #include <assert.h> 10 11 static u32 pci_config_address_bits; 12 13 /* This is within our PCI gap - in an unused area. 14 * Note this is a PCI *bus address*, is used to assign BARs etc.! 15 * (That's why it can still 32bit even with 64bit guests-- 64bit 16 * PCI isn't currently supported.) 17 */ 18 static u32 mmio_blocks = KVM_PCI_MMIO_AREA; 19 static u16 io_port_blocks = PCI_IOPORT_START; 20 21 u16 pci_get_io_port_block(u32 size) 22 { 23 u16 port = ALIGN(io_port_blocks, PCI_IO_SIZE); 24 25 io_port_blocks = port + size; 26 return port; 27 } 28 29 /* 30 * BARs must be naturally aligned, so enforce this in the allocator. 31 */ 32 u32 pci_get_mmio_block(u32 size) 33 { 34 u32 block = ALIGN(mmio_blocks, size); 35 mmio_blocks = block + size; 36 return block; 37 } 38 39 void *pci_find_cap(struct pci_device_header *hdr, u8 cap_type) 40 { 41 u8 pos; 42 struct pci_cap_hdr *cap; 43 44 pci_for_each_cap(pos, cap, hdr) { 45 if (cap->type == cap_type) 46 return cap; 47 } 48 49 return NULL; 50 } 51 52 int pci__assign_irq(struct pci_device_header *pci_hdr) 53 { 54 /* 55 * PCI supports only INTA#,B#,C#,D# per device. 56 * 57 * A#,B#,C#,D# are allowed for multifunctional devices so stick 58 * with A# for our single function devices. 59 */ 60 pci_hdr->irq_pin = 1; 61 pci_hdr->irq_line = irq__alloc_line(); 62 63 if (!pci_hdr->irq_type) 64 pci_hdr->irq_type = IRQ_TYPE_EDGE_RISING; 65 66 return pci_hdr->irq_line; 67 } 68 69 static void *pci_config_address_ptr(u16 port) 70 { 71 unsigned long offset; 72 void *base; 73 74 offset = port - PCI_CONFIG_ADDRESS; 75 base = &pci_config_address_bits; 76 77 return base + offset; 78 } 79 80 static bool pci_config_address_out(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size) 81 { 82 void *p = pci_config_address_ptr(port); 83 84 memcpy(p, data, size); 85 86 return true; 87 } 88 89 static bool pci_config_address_in(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size) 90 { 91 void *p = pci_config_address_ptr(port); 92 93 memcpy(data, p, size); 94 95 return true; 96 } 97 98 static struct ioport_operations pci_config_address_ops = { 99 .io_in = pci_config_address_in, 100 .io_out = pci_config_address_out, 101 }; 102 103 static bool pci_device_exists(u8 bus_number, u8 device_number, u8 function_number) 104 { 105 union pci_config_address pci_config_address; 106 107 pci_config_address.w = ioport__read32(&pci_config_address_bits); 108 109 if (pci_config_address.bus_number != bus_number) 110 return false; 111 112 if (pci_config_address.function_number != function_number) 113 return false; 114 115 return !IS_ERR_OR_NULL(device__find_dev(DEVICE_BUS_PCI, device_number)); 116 } 117 118 static bool pci_config_data_out(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size) 119 { 120 union pci_config_address pci_config_address; 121 122 if (size > 4) 123 size = 4; 124 125 pci_config_address.w = ioport__read32(&pci_config_address_bits); 126 /* 127 * If someone accesses PCI configuration space offsets that are not 128 * aligned to 4 bytes, it uses ioports to signify that. 129 */ 130 pci_config_address.reg_offset = port - PCI_CONFIG_DATA; 131 132 pci__config_wr(vcpu->kvm, pci_config_address, data, size); 133 134 return true; 135 } 136 137 static bool pci_config_data_in(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size) 138 { 139 union pci_config_address pci_config_address; 140 141 if (size > 4) 142 size = 4; 143 144 pci_config_address.w = ioport__read32(&pci_config_address_bits); 145 /* 146 * If someone accesses PCI configuration space offsets that are not 147 * aligned to 4 bytes, it uses ioports to signify that. 148 */ 149 pci_config_address.reg_offset = port - PCI_CONFIG_DATA; 150 151 pci__config_rd(vcpu->kvm, pci_config_address, data, size); 152 153 return true; 154 } 155 156 static struct ioport_operations pci_config_data_ops = { 157 .io_in = pci_config_data_in, 158 .io_out = pci_config_data_out, 159 }; 160 161 void pci__config_wr(struct kvm *kvm, union pci_config_address addr, void *data, int size) 162 { 163 void *base; 164 u8 bar, offset; 165 struct pci_device_header *pci_hdr; 166 u8 dev_num = addr.device_number; 167 u32 value = 0; 168 u32 mask; 169 170 if (!pci_device_exists(addr.bus_number, dev_num, 0)) 171 return; 172 173 offset = addr.w & PCI_DEV_CFG_MASK; 174 base = pci_hdr = device__find_dev(DEVICE_BUS_PCI, dev_num)->data; 175 176 if (pci_hdr->cfg_ops.write) 177 pci_hdr->cfg_ops.write(kvm, pci_hdr, offset, data, size); 178 179 /* 180 * legacy hack: ignore writes to uninitialized regions (e.g. ROM BAR). 181 * Not very nice but has been working so far. 182 */ 183 if (*(u32 *)(base + offset) == 0) 184 return; 185 186 bar = (offset - PCI_BAR_OFFSET(0)) / sizeof(u32); 187 188 /* 189 * If the kernel masks the BAR, it will expect to find the size of the 190 * BAR there next time it reads from it. After the kernel reads the 191 * size, it will write the address back. 192 */ 193 if (bar < 6) { 194 if (pci__bar_is_io(pci_hdr, bar)) 195 mask = (u32)PCI_BASE_ADDRESS_IO_MASK; 196 else 197 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; 198 /* 199 * According to the PCI local bus specification REV 3.0: 200 * The number of upper bits that a device actually implements 201 * depends on how much of the address space the device will 202 * respond to. A device that wants a 1 MB memory address space 203 * (using a 32-bit base address register) would build the top 204 * 12 bits of the address register, hardwiring the other bits 205 * to 0. 206 * 207 * Furthermore, software can determine how much address space 208 * the device requires by writing a value of all 1's to the 209 * register and then reading the value back. The device will 210 * return 0's in all don't-care address bits, effectively 211 * specifying the address space required. 212 * 213 * Software computes the size of the address space with the 214 * formula S = ~B + 1, where S is the memory size and B is the 215 * value read from the BAR. This means that the BAR value that 216 * kvmtool should return is B = ~(S - 1). 217 */ 218 memcpy(&value, data, size); 219 if (value == 0xffffffff) 220 value = ~(pci__bar_size(pci_hdr, bar) - 1); 221 /* Preserve the special bits. */ 222 value = (value & mask) | (pci_hdr->bar[bar] & ~mask); 223 memcpy(base + offset, &value, size); 224 } else { 225 memcpy(base + offset, data, size); 226 } 227 } 228 229 void pci__config_rd(struct kvm *kvm, union pci_config_address addr, void *data, int size) 230 { 231 u8 offset; 232 struct pci_device_header *pci_hdr; 233 u8 dev_num = addr.device_number; 234 235 if (pci_device_exists(addr.bus_number, dev_num, 0)) { 236 pci_hdr = device__find_dev(DEVICE_BUS_PCI, dev_num)->data; 237 offset = addr.w & PCI_DEV_CFG_MASK; 238 239 if (pci_hdr->cfg_ops.read) 240 pci_hdr->cfg_ops.read(kvm, pci_hdr, offset, data, size); 241 242 memcpy(data, (void *)pci_hdr + offset, size); 243 } else { 244 memset(data, 0xff, size); 245 } 246 } 247 248 static void pci_config_mmio_access(struct kvm_cpu *vcpu, u64 addr, u8 *data, 249 u32 len, u8 is_write, void *kvm) 250 { 251 union pci_config_address cfg_addr; 252 253 addr -= KVM_PCI_CFG_AREA; 254 cfg_addr.w = (u32)addr; 255 cfg_addr.enable_bit = 1; 256 257 if (len > 4) 258 len = 4; 259 260 if (is_write) 261 pci__config_wr(kvm, cfg_addr, data, len); 262 else 263 pci__config_rd(kvm, cfg_addr, data, len); 264 } 265 266 struct pci_device_header *pci__find_dev(u8 dev_num) 267 { 268 struct device_header *hdr = device__find_dev(DEVICE_BUS_PCI, dev_num); 269 270 if (IS_ERR_OR_NULL(hdr)) 271 return NULL; 272 273 return hdr->data; 274 } 275 276 int pci__init(struct kvm *kvm) 277 { 278 int r; 279 280 r = ioport__register(kvm, PCI_CONFIG_DATA + 0, &pci_config_data_ops, 4, NULL); 281 if (r < 0) 282 return r; 283 284 r = ioport__register(kvm, PCI_CONFIG_ADDRESS + 0, &pci_config_address_ops, 4, NULL); 285 if (r < 0) 286 goto err_unregister_data; 287 288 r = kvm__register_mmio(kvm, KVM_PCI_CFG_AREA, PCI_CFG_SIZE, false, 289 pci_config_mmio_access, kvm); 290 if (r < 0) 291 goto err_unregister_addr; 292 293 return 0; 294 295 err_unregister_addr: 296 ioport__unregister(kvm, PCI_CONFIG_ADDRESS); 297 err_unregister_data: 298 ioport__unregister(kvm, PCI_CONFIG_DATA); 299 return r; 300 } 301 dev_base_init(pci__init); 302 303 int pci__exit(struct kvm *kvm) 304 { 305 ioport__unregister(kvm, PCI_CONFIG_DATA); 306 ioport__unregister(kvm, PCI_CONFIG_ADDRESS); 307 308 return 0; 309 } 310 dev_base_exit(pci__exit); 311