1 #include "kvm/devices.h" 2 #include "kvm/pci.h" 3 #include "kvm/ioport.h" 4 #include "kvm/irq.h" 5 #include "kvm/util.h" 6 #include "kvm/kvm.h" 7 8 #include <linux/err.h> 9 #include <assert.h> 10 11 static u32 pci_config_address_bits; 12 13 /* This is within our PCI gap - in an unused area. 14 * Note this is a PCI *bus address*, is used to assign BARs etc.! 15 * (That's why it can still 32bit even with 64bit guests-- 64bit 16 * PCI isn't currently supported.) 17 */ 18 static u32 mmio_blocks = KVM_PCI_MMIO_AREA; 19 static u16 io_port_blocks = PCI_IOPORT_START; 20 21 u16 pci_get_io_port_block(u32 size) 22 { 23 u16 port = ALIGN(io_port_blocks, PCI_IO_SIZE); 24 25 io_port_blocks = port + size; 26 return port; 27 } 28 29 /* 30 * BARs must be naturally aligned, so enforce this in the allocator. 31 */ 32 u32 pci_get_mmio_block(u32 size) 33 { 34 u32 block = ALIGN(mmio_blocks, size); 35 mmio_blocks = block + size; 36 return block; 37 } 38 39 void *pci_find_cap(struct pci_device_header *hdr, u8 cap_type) 40 { 41 u8 pos; 42 struct pci_cap_hdr *cap; 43 44 pci_for_each_cap(pos, cap, hdr) { 45 if (cap->type == cap_type) 46 return cap; 47 } 48 49 return NULL; 50 } 51 52 int pci__assign_irq(struct pci_device_header *pci_hdr) 53 { 54 /* 55 * PCI supports only INTA#,B#,C#,D# per device. 56 * 57 * A#,B#,C#,D# are allowed for multifunctional devices so stick 58 * with A# for our single function devices. 59 */ 60 pci_hdr->irq_pin = 1; 61 pci_hdr->irq_line = irq__alloc_line(); 62 63 if (!pci_hdr->irq_type) 64 pci_hdr->irq_type = IRQ_TYPE_EDGE_RISING; 65 66 return pci_hdr->irq_line; 67 } 68 69 static bool pci_bar_is_implemented(struct pci_device_header *pci_hdr, int bar_num) 70 { 71 return pci__bar_size(pci_hdr, bar_num); 72 } 73 74 static void *pci_config_address_ptr(u16 port) 75 { 76 unsigned long offset; 77 void *base; 78 79 offset = port - PCI_CONFIG_ADDRESS; 80 base = &pci_config_address_bits; 81 82 return base + offset; 83 } 84 85 static bool pci_config_address_out(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size) 86 { 87 void *p = pci_config_address_ptr(port); 88 89 memcpy(p, data, size); 90 91 return true; 92 } 93 94 static bool pci_config_address_in(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size) 95 { 96 void *p = pci_config_address_ptr(port); 97 98 memcpy(data, p, size); 99 100 return true; 101 } 102 103 static struct ioport_operations pci_config_address_ops = { 104 .io_in = pci_config_address_in, 105 .io_out = pci_config_address_out, 106 }; 107 108 static bool pci_device_exists(u8 bus_number, u8 device_number, u8 function_number) 109 { 110 union pci_config_address pci_config_address; 111 112 pci_config_address.w = ioport__read32(&pci_config_address_bits); 113 114 if (pci_config_address.bus_number != bus_number) 115 return false; 116 117 if (pci_config_address.function_number != function_number) 118 return false; 119 120 return !IS_ERR_OR_NULL(device__find_dev(DEVICE_BUS_PCI, device_number)); 121 } 122 123 static bool pci_config_data_out(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size) 124 { 125 union pci_config_address pci_config_address; 126 127 if (size > 4) 128 size = 4; 129 130 pci_config_address.w = ioport__read32(&pci_config_address_bits); 131 /* 132 * If someone accesses PCI configuration space offsets that are not 133 * aligned to 4 bytes, it uses ioports to signify that. 134 */ 135 pci_config_address.reg_offset = port - PCI_CONFIG_DATA; 136 137 pci__config_wr(vcpu->kvm, pci_config_address, data, size); 138 139 return true; 140 } 141 142 static bool pci_config_data_in(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size) 143 { 144 union pci_config_address pci_config_address; 145 146 if (size > 4) 147 size = 4; 148 149 pci_config_address.w = ioport__read32(&pci_config_address_bits); 150 /* 151 * If someone accesses PCI configuration space offsets that are not 152 * aligned to 4 bytes, it uses ioports to signify that. 153 */ 154 pci_config_address.reg_offset = port - PCI_CONFIG_DATA; 155 156 pci__config_rd(vcpu->kvm, pci_config_address, data, size); 157 158 return true; 159 } 160 161 static struct ioport_operations pci_config_data_ops = { 162 .io_in = pci_config_data_in, 163 .io_out = pci_config_data_out, 164 }; 165 166 void pci__config_wr(struct kvm *kvm, union pci_config_address addr, void *data, int size) 167 { 168 void *base; 169 u8 bar, offset; 170 struct pci_device_header *pci_hdr; 171 u8 dev_num = addr.device_number; 172 u32 value = 0; 173 u32 mask; 174 175 if (!pci_device_exists(addr.bus_number, dev_num, 0)) 176 return; 177 178 offset = addr.w & PCI_DEV_CFG_MASK; 179 base = pci_hdr = device__find_dev(DEVICE_BUS_PCI, dev_num)->data; 180 181 if (pci_hdr->cfg_ops.write) 182 pci_hdr->cfg_ops.write(kvm, pci_hdr, offset, data, size); 183 184 /* 185 * legacy hack: ignore writes to uninitialized regions (e.g. ROM BAR). 186 * Not very nice but has been working so far. 187 */ 188 if (*(u32 *)(base + offset) == 0) 189 return; 190 191 bar = (offset - PCI_BAR_OFFSET(0)) / sizeof(u32); 192 193 /* 194 * If the kernel masks the BAR, it will expect to find the size of the 195 * BAR there next time it reads from it. After the kernel reads the 196 * size, it will write the address back. 197 */ 198 if (bar < 6) { 199 if (pci__bar_is_io(pci_hdr, bar)) 200 mask = (u32)PCI_BASE_ADDRESS_IO_MASK; 201 else 202 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; 203 /* 204 * According to the PCI local bus specification REV 3.0: 205 * The number of upper bits that a device actually implements 206 * depends on how much of the address space the device will 207 * respond to. A device that wants a 1 MB memory address space 208 * (using a 32-bit base address register) would build the top 209 * 12 bits of the address register, hardwiring the other bits 210 * to 0. 211 * 212 * Furthermore, software can determine how much address space 213 * the device requires by writing a value of all 1's to the 214 * register and then reading the value back. The device will 215 * return 0's in all don't-care address bits, effectively 216 * specifying the address space required. 217 * 218 * Software computes the size of the address space with the 219 * formula S = ~B + 1, where S is the memory size and B is the 220 * value read from the BAR. This means that the BAR value that 221 * kvmtool should return is B = ~(S - 1). 222 */ 223 memcpy(&value, data, size); 224 if (value == 0xffffffff) 225 value = ~(pci__bar_size(pci_hdr, bar) - 1); 226 /* Preserve the special bits. */ 227 value = (value & mask) | (pci_hdr->bar[bar] & ~mask); 228 memcpy(base + offset, &value, size); 229 } else { 230 memcpy(base + offset, data, size); 231 } 232 } 233 234 void pci__config_rd(struct kvm *kvm, union pci_config_address addr, void *data, int size) 235 { 236 u8 offset; 237 struct pci_device_header *pci_hdr; 238 u8 dev_num = addr.device_number; 239 240 if (pci_device_exists(addr.bus_number, dev_num, 0)) { 241 pci_hdr = device__find_dev(DEVICE_BUS_PCI, dev_num)->data; 242 offset = addr.w & PCI_DEV_CFG_MASK; 243 244 if (pci_hdr->cfg_ops.read) 245 pci_hdr->cfg_ops.read(kvm, pci_hdr, offset, data, size); 246 247 memcpy(data, (void *)pci_hdr + offset, size); 248 } else { 249 memset(data, 0xff, size); 250 } 251 } 252 253 static void pci_config_mmio_access(struct kvm_cpu *vcpu, u64 addr, u8 *data, 254 u32 len, u8 is_write, void *kvm) 255 { 256 union pci_config_address cfg_addr; 257 258 addr -= KVM_PCI_CFG_AREA; 259 cfg_addr.w = (u32)addr; 260 cfg_addr.enable_bit = 1; 261 262 if (len > 4) 263 len = 4; 264 265 if (is_write) 266 pci__config_wr(kvm, cfg_addr, data, len); 267 else 268 pci__config_rd(kvm, cfg_addr, data, len); 269 } 270 271 struct pci_device_header *pci__find_dev(u8 dev_num) 272 { 273 struct device_header *hdr = device__find_dev(DEVICE_BUS_PCI, dev_num); 274 275 if (IS_ERR_OR_NULL(hdr)) 276 return NULL; 277 278 return hdr->data; 279 } 280 281 int pci__register_bar_regions(struct kvm *kvm, struct pci_device_header *pci_hdr, 282 bar_activate_fn_t bar_activate_fn, 283 bar_deactivate_fn_t bar_deactivate_fn, void *data) 284 { 285 int i, r; 286 287 assert(bar_activate_fn && bar_deactivate_fn); 288 289 pci_hdr->bar_activate_fn = bar_activate_fn; 290 pci_hdr->bar_deactivate_fn = bar_deactivate_fn; 291 pci_hdr->data = data; 292 293 for (i = 0; i < 6; i++) { 294 if (!pci_bar_is_implemented(pci_hdr, i)) 295 continue; 296 297 if (pci__bar_is_io(pci_hdr, i) && 298 pci__io_space_enabled(pci_hdr)) { 299 r = bar_activate_fn(kvm, pci_hdr, i, data); 300 if (r < 0) 301 return r; 302 } 303 304 if (pci__bar_is_memory(pci_hdr, i) && 305 pci__memory_space_enabled(pci_hdr)) { 306 r = bar_activate_fn(kvm, pci_hdr, i, data); 307 if (r < 0) 308 return r; 309 } 310 } 311 312 return 0; 313 } 314 315 int pci__init(struct kvm *kvm) 316 { 317 int r; 318 319 r = ioport__register(kvm, PCI_CONFIG_DATA + 0, &pci_config_data_ops, 4, NULL); 320 if (r < 0) 321 return r; 322 323 r = ioport__register(kvm, PCI_CONFIG_ADDRESS + 0, &pci_config_address_ops, 4, NULL); 324 if (r < 0) 325 goto err_unregister_data; 326 327 r = kvm__register_mmio(kvm, KVM_PCI_CFG_AREA, PCI_CFG_SIZE, false, 328 pci_config_mmio_access, kvm); 329 if (r < 0) 330 goto err_unregister_addr; 331 332 return 0; 333 334 err_unregister_addr: 335 ioport__unregister(kvm, PCI_CONFIG_ADDRESS); 336 err_unregister_data: 337 ioport__unregister(kvm, PCI_CONFIG_DATA); 338 return r; 339 } 340 dev_base_init(pci__init); 341 342 int pci__exit(struct kvm *kvm) 343 { 344 ioport__unregister(kvm, PCI_CONFIG_DATA); 345 ioport__unregister(kvm, PCI_CONFIG_ADDRESS); 346 347 return 0; 348 } 349 dev_base_exit(pci__exit); 350