xref: /kvmtool/pci.c (revision 4123ca555b1d466b08c630763a378b4d53de9ec5)
1 #include "kvm/devices.h"
2 #include "kvm/pci.h"
3 #include "kvm/ioport.h"
4 #include "kvm/irq.h"
5 #include "kvm/util.h"
6 #include "kvm/kvm.h"
7 
8 #include <linux/err.h>
9 #include <assert.h>
10 
11 #define PCI_BAR_OFFSET(b)		(offsetof(struct pci_device_header, bar[b]))
12 
13 static union pci_config_address		pci_config_address;
14 
15 /* This is within our PCI gap - in an unused area.
16  * Note this is a PCI *bus address*, is used to assign BARs etc.!
17  * (That's why it can still 32bit even with 64bit guests-- 64bit
18  * PCI isn't currently supported.)
19  */
20 static u32 io_space_blocks		= KVM_PCI_MMIO_AREA;
21 
22 /*
23  * BARs must be naturally aligned, so enforce this in the allocator.
24  */
25 u32 pci_get_io_space_block(u32 size)
26 {
27 	u32 block = ALIGN(io_space_blocks, size);
28 	io_space_blocks = block + size;
29 	return block;
30 }
31 
32 void pci__assign_irq(struct device_header *dev_hdr)
33 {
34 	struct pci_device_header *pci_hdr = dev_hdr->data;
35 
36 	/*
37 	 * PCI supports only INTA#,B#,C#,D# per device.
38 	 *
39 	 * A#,B#,C#,D# are allowed for multifunctional devices so stick
40 	 * with A# for our single function devices.
41 	 */
42 	pci_hdr->irq_pin	= 1;
43 	pci_hdr->irq_line	= irq__alloc_line();
44 }
45 
46 static void *pci_config_address_ptr(u16 port)
47 {
48 	unsigned long offset;
49 	void *base;
50 
51 	offset	= port - PCI_CONFIG_ADDRESS;
52 	base	= &pci_config_address;
53 
54 	return base + offset;
55 }
56 
57 static bool pci_config_address_out(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size)
58 {
59 	void *p = pci_config_address_ptr(port);
60 
61 	memcpy(p, data, size);
62 
63 	return true;
64 }
65 
66 static bool pci_config_address_in(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size)
67 {
68 	void *p = pci_config_address_ptr(port);
69 
70 	memcpy(data, p, size);
71 
72 	return true;
73 }
74 
75 static struct ioport_operations pci_config_address_ops = {
76 	.io_in	= pci_config_address_in,
77 	.io_out	= pci_config_address_out,
78 };
79 
80 static bool pci_device_exists(u8 bus_number, u8 device_number, u8 function_number)
81 {
82 	if (pci_config_address.bus_number != bus_number)
83 		return false;
84 
85 	if (pci_config_address.function_number != function_number)
86 		return false;
87 
88 	return !IS_ERR_OR_NULL(device__find_dev(DEVICE_BUS_PCI, device_number));
89 }
90 
91 static bool pci_config_data_out(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size)
92 {
93 	/*
94 	 * If someone accesses PCI configuration space offsets that are not
95 	 * aligned to 4 bytes, it uses ioports to signify that.
96 	 */
97 	pci_config_address.reg_offset = port - PCI_CONFIG_DATA;
98 
99 	pci__config_wr(vcpu->kvm, pci_config_address, data, size);
100 
101 	return true;
102 }
103 
104 static bool pci_config_data_in(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size)
105 {
106 	/*
107 	 * If someone accesses PCI configuration space offsets that are not
108 	 * aligned to 4 bytes, it uses ioports to signify that.
109 	 */
110 	pci_config_address.reg_offset = port - PCI_CONFIG_DATA;
111 
112 	pci__config_rd(vcpu->kvm, pci_config_address, data, size);
113 
114 	return true;
115 }
116 
117 static struct ioport_operations pci_config_data_ops = {
118 	.io_in	= pci_config_data_in,
119 	.io_out	= pci_config_data_out,
120 };
121 
122 void pci__config_wr(struct kvm *kvm, union pci_config_address addr, void *data, int size)
123 {
124 	u8 dev_num;
125 
126 	dev_num	= addr.device_number;
127 
128 	if (pci_device_exists(0, dev_num, 0)) {
129 		unsigned long offset;
130 
131 		offset = addr.w & 0xff;
132 		if (offset < sizeof(struct pci_device_header)) {
133 			void *p = device__find_dev(DEVICE_BUS_PCI, dev_num)->data;
134 			struct pci_device_header *hdr = p;
135 			u8 bar = (offset - PCI_BAR_OFFSET(0)) / (sizeof(u32));
136 			u32 sz = PCI_IO_SIZE;
137 
138 			if (bar < 6 && hdr->bar_size[bar])
139 				sz = hdr->bar_size[bar];
140 
141 			/*
142 			 * If the kernel masks the BAR it would expect to find the
143 			 * size of the BAR there next time it reads from it.
144 			 * When the kernel got the size it would write the address
145 			 * back.
146 			 */
147 			if (*(u32 *)(p + offset)) {
148 				/* See if kernel tries to mask one of the BARs */
149 				if ((offset >= PCI_BAR_OFFSET(0)) &&
150 				    (offset <= PCI_BAR_OFFSET(6)) &&
151 				    (ioport__read32(data)  == 0xFFFFFFFF))
152 					memcpy(p + offset, &sz, sizeof(sz));
153 				    else
154 					memcpy(p + offset, data, size);
155 			}
156 		}
157 	}
158 }
159 
160 void pci__config_rd(struct kvm *kvm, union pci_config_address addr, void *data, int size)
161 {
162 	u8 dev_num;
163 
164 	dev_num	= addr.device_number;
165 
166 	if (pci_device_exists(0, dev_num, 0)) {
167 		unsigned long offset;
168 
169 		offset = addr.w & 0xff;
170 		if (offset < sizeof(struct pci_device_header)) {
171 			void *p = device__find_dev(DEVICE_BUS_PCI, dev_num)->data;
172 
173 			memcpy(data, p + offset, size);
174 		} else {
175 			memset(data, 0x00, size);
176 		}
177 	} else {
178 		memset(data, 0xff, size);
179 	}
180 }
181 
182 static void pci_config_mmio_access(struct kvm_cpu *vcpu, u64 addr, u8 *data,
183 				   u32 len, u8 is_write, void *kvm)
184 {
185 	union pci_config_address cfg_addr;
186 
187 	addr			-= KVM_PCI_CFG_AREA;
188 	cfg_addr.w		= (u32)addr;
189 	cfg_addr.enable_bit	= 1;
190 
191 	if (is_write)
192 		pci__config_wr(kvm, cfg_addr, data, len);
193 	else
194 		pci__config_rd(kvm, cfg_addr, data, len);
195 }
196 
197 struct pci_device_header *pci__find_dev(u8 dev_num)
198 {
199 	struct device_header *hdr = device__find_dev(DEVICE_BUS_PCI, dev_num);
200 
201 	if (IS_ERR_OR_NULL(hdr))
202 		return NULL;
203 
204 	return hdr->data;
205 }
206 
207 int pci__init(struct kvm *kvm)
208 {
209 	int r;
210 
211 	r = ioport__register(kvm, PCI_CONFIG_DATA + 0, &pci_config_data_ops, 4, NULL);
212 	if (r < 0)
213 		return r;
214 
215 	r = ioport__register(kvm, PCI_CONFIG_ADDRESS + 0, &pci_config_address_ops, 4, NULL);
216 	if (r < 0)
217 		goto err_unregister_data;
218 
219 	r = kvm__register_mmio(kvm, KVM_PCI_CFG_AREA, PCI_CFG_SIZE, false,
220 			       pci_config_mmio_access, kvm);
221 	if (r < 0)
222 		goto err_unregister_addr;
223 
224 	return 0;
225 
226 err_unregister_addr:
227 	ioport__unregister(kvm, PCI_CONFIG_ADDRESS);
228 err_unregister_data:
229 	ioport__unregister(kvm, PCI_CONFIG_DATA);
230 	return r;
231 }
232 dev_base_init(pci__init);
233 
234 int pci__exit(struct kvm *kvm)
235 {
236 	ioport__unregister(kvm, PCI_CONFIG_DATA);
237 	ioport__unregister(kvm, PCI_CONFIG_ADDRESS);
238 
239 	return 0;
240 }
241 dev_base_exit(pci__exit);
242