1 #include "kvm/devices.h" 2 #include "kvm/pci.h" 3 #include "kvm/ioport.h" 4 #include "kvm/irq.h" 5 #include "kvm/util.h" 6 #include "kvm/kvm.h" 7 8 #include <linux/err.h> 9 #include <assert.h> 10 11 static u32 pci_config_address_bits; 12 13 /* This is within our PCI gap - in an unused area. 14 * Note this is a PCI *bus address*, is used to assign BARs etc.! 15 * (That's why it can still 32bit even with 64bit guests-- 64bit 16 * PCI isn't currently supported.) 17 */ 18 static u32 mmio_blocks = KVM_PCI_MMIO_AREA; 19 static u16 io_port_blocks = PCI_IOPORT_START; 20 21 u16 pci_get_io_port_block(u32 size) 22 { 23 u16 port = ALIGN(io_port_blocks, PCI_IO_SIZE); 24 25 io_port_blocks = port + size; 26 return port; 27 } 28 29 /* 30 * BARs must be naturally aligned, so enforce this in the allocator. 31 */ 32 u32 pci_get_mmio_block(u32 size) 33 { 34 u32 block = ALIGN(mmio_blocks, size); 35 mmio_blocks = block + size; 36 return block; 37 } 38 39 void *pci_find_cap(struct pci_device_header *hdr, u8 cap_type) 40 { 41 u8 pos; 42 struct pci_cap_hdr *cap; 43 44 pci_for_each_cap(pos, cap, hdr) { 45 if (cap->type == cap_type) 46 return cap; 47 } 48 49 return NULL; 50 } 51 52 int pci__assign_irq(struct pci_device_header *pci_hdr) 53 { 54 /* 55 * PCI supports only INTA#,B#,C#,D# per device. 56 * 57 * A#,B#,C#,D# are allowed for multifunctional devices so stick 58 * with A# for our single function devices. 59 */ 60 pci_hdr->irq_pin = 1; 61 pci_hdr->irq_line = irq__alloc_line(); 62 63 if (!pci_hdr->irq_type) 64 pci_hdr->irq_type = IRQ_TYPE_EDGE_RISING; 65 66 return pci_hdr->irq_line; 67 } 68 69 static void *pci_config_address_ptr(u16 port) 70 { 71 unsigned long offset; 72 void *base; 73 74 offset = port - PCI_CONFIG_ADDRESS; 75 base = &pci_config_address_bits; 76 77 return base + offset; 78 } 79 80 static bool pci_config_address_out(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size) 81 { 82 void *p = pci_config_address_ptr(port); 83 84 memcpy(p, data, size); 85 86 return true; 87 } 88 89 static bool pci_config_address_in(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size) 90 { 91 void *p = pci_config_address_ptr(port); 92 93 memcpy(data, p, size); 94 95 return true; 96 } 97 98 static struct ioport_operations pci_config_address_ops = { 99 .io_in = pci_config_address_in, 100 .io_out = pci_config_address_out, 101 }; 102 103 static bool pci_device_exists(u8 bus_number, u8 device_number, u8 function_number) 104 { 105 union pci_config_address pci_config_address; 106 107 pci_config_address.w = ioport__read32(&pci_config_address_bits); 108 109 if (pci_config_address.bus_number != bus_number) 110 return false; 111 112 if (pci_config_address.function_number != function_number) 113 return false; 114 115 return !IS_ERR_OR_NULL(device__find_dev(DEVICE_BUS_PCI, device_number)); 116 } 117 118 static bool pci_config_data_out(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size) 119 { 120 union pci_config_address pci_config_address; 121 122 pci_config_address.w = ioport__read32(&pci_config_address_bits); 123 /* 124 * If someone accesses PCI configuration space offsets that are not 125 * aligned to 4 bytes, it uses ioports to signify that. 126 */ 127 pci_config_address.reg_offset = port - PCI_CONFIG_DATA; 128 129 pci__config_wr(vcpu->kvm, pci_config_address, data, size); 130 131 return true; 132 } 133 134 static bool pci_config_data_in(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size) 135 { 136 union pci_config_address pci_config_address; 137 138 pci_config_address.w = ioport__read32(&pci_config_address_bits); 139 /* 140 * If someone accesses PCI configuration space offsets that are not 141 * aligned to 4 bytes, it uses ioports to signify that. 142 */ 143 pci_config_address.reg_offset = port - PCI_CONFIG_DATA; 144 145 pci__config_rd(vcpu->kvm, pci_config_address, data, size); 146 147 return true; 148 } 149 150 static struct ioport_operations pci_config_data_ops = { 151 .io_in = pci_config_data_in, 152 .io_out = pci_config_data_out, 153 }; 154 155 void pci__config_wr(struct kvm *kvm, union pci_config_address addr, void *data, int size) 156 { 157 void *base; 158 u8 bar, offset; 159 struct pci_device_header *pci_hdr; 160 u8 dev_num = addr.device_number; 161 u32 value = 0; 162 u32 mask; 163 164 if (!pci_device_exists(addr.bus_number, dev_num, 0)) 165 return; 166 167 offset = addr.w & PCI_DEV_CFG_MASK; 168 base = pci_hdr = device__find_dev(DEVICE_BUS_PCI, dev_num)->data; 169 170 if (pci_hdr->cfg_ops.write) 171 pci_hdr->cfg_ops.write(kvm, pci_hdr, offset, data, size); 172 173 /* 174 * legacy hack: ignore writes to uninitialized regions (e.g. ROM BAR). 175 * Not very nice but has been working so far. 176 */ 177 if (*(u32 *)(base + offset) == 0) 178 return; 179 180 bar = (offset - PCI_BAR_OFFSET(0)) / sizeof(u32); 181 182 /* 183 * If the kernel masks the BAR, it will expect to find the size of the 184 * BAR there next time it reads from it. After the kernel reads the 185 * size, it will write the address back. 186 */ 187 if (bar < 6) { 188 if (pci__bar_is_io(pci_hdr, bar)) 189 mask = (u32)PCI_BASE_ADDRESS_IO_MASK; 190 else 191 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; 192 /* 193 * According to the PCI local bus specification REV 3.0: 194 * The number of upper bits that a device actually implements 195 * depends on how much of the address space the device will 196 * respond to. A device that wants a 1 MB memory address space 197 * (using a 32-bit base address register) would build the top 198 * 12 bits of the address register, hardwiring the other bits 199 * to 0. 200 * 201 * Furthermore, software can determine how much address space 202 * the device requires by writing a value of all 1's to the 203 * register and then reading the value back. The device will 204 * return 0's in all don't-care address bits, effectively 205 * specifying the address space required. 206 * 207 * Software computes the size of the address space with the 208 * formula S = ~B + 1, where S is the memory size and B is the 209 * value read from the BAR. This means that the BAR value that 210 * kvmtool should return is B = ~(S - 1). 211 */ 212 memcpy(&value, data, size); 213 if (value == 0xffffffff) 214 value = ~(pci__bar_size(pci_hdr, bar) - 1); 215 /* Preserve the special bits. */ 216 value = (value & mask) | (pci_hdr->bar[bar] & ~mask); 217 memcpy(base + offset, &value, size); 218 } else { 219 memcpy(base + offset, data, size); 220 } 221 } 222 223 void pci__config_rd(struct kvm *kvm, union pci_config_address addr, void *data, int size) 224 { 225 u8 offset; 226 struct pci_device_header *pci_hdr; 227 u8 dev_num = addr.device_number; 228 229 if (pci_device_exists(addr.bus_number, dev_num, 0)) { 230 pci_hdr = device__find_dev(DEVICE_BUS_PCI, dev_num)->data; 231 offset = addr.w & PCI_DEV_CFG_MASK; 232 233 if (pci_hdr->cfg_ops.read) 234 pci_hdr->cfg_ops.read(kvm, pci_hdr, offset, data, size); 235 236 memcpy(data, (void *)pci_hdr + offset, size); 237 } else { 238 memset(data, 0xff, size); 239 } 240 } 241 242 static void pci_config_mmio_access(struct kvm_cpu *vcpu, u64 addr, u8 *data, 243 u32 len, u8 is_write, void *kvm) 244 { 245 union pci_config_address cfg_addr; 246 247 addr -= KVM_PCI_CFG_AREA; 248 cfg_addr.w = (u32)addr; 249 cfg_addr.enable_bit = 1; 250 251 if (is_write) 252 pci__config_wr(kvm, cfg_addr, data, len); 253 else 254 pci__config_rd(kvm, cfg_addr, data, len); 255 } 256 257 struct pci_device_header *pci__find_dev(u8 dev_num) 258 { 259 struct device_header *hdr = device__find_dev(DEVICE_BUS_PCI, dev_num); 260 261 if (IS_ERR_OR_NULL(hdr)) 262 return NULL; 263 264 return hdr->data; 265 } 266 267 int pci__init(struct kvm *kvm) 268 { 269 int r; 270 271 r = ioport__register(kvm, PCI_CONFIG_DATA + 0, &pci_config_data_ops, 4, NULL); 272 if (r < 0) 273 return r; 274 275 r = ioport__register(kvm, PCI_CONFIG_ADDRESS + 0, &pci_config_address_ops, 4, NULL); 276 if (r < 0) 277 goto err_unregister_data; 278 279 r = kvm__register_mmio(kvm, KVM_PCI_CFG_AREA, PCI_CFG_SIZE, false, 280 pci_config_mmio_access, kvm); 281 if (r < 0) 282 goto err_unregister_addr; 283 284 return 0; 285 286 err_unregister_addr: 287 ioport__unregister(kvm, PCI_CONFIG_ADDRESS); 288 err_unregister_data: 289 ioport__unregister(kvm, PCI_CONFIG_DATA); 290 return r; 291 } 292 dev_base_init(pci__init); 293 294 int pci__exit(struct kvm *kvm) 295 { 296 ioport__unregister(kvm, PCI_CONFIG_DATA); 297 ioport__unregister(kvm, PCI_CONFIG_ADDRESS); 298 299 return 0; 300 } 301 dev_base_exit(pci__exit); 302