17c0e8b0cSWill Deacon #ifndef ARM_COMMON__GIC_H 27c0e8b0cSWill Deacon #define ARM_COMMON__GIC_H 37c0e8b0cSWill Deacon 47c0e8b0cSWill Deacon #define GIC_SGI_IRQ_BASE 0 57c0e8b0cSWill Deacon #define GIC_PPI_IRQ_BASE 16 67c0e8b0cSWill Deacon #define GIC_SPI_IRQ_BASE 32 77c0e8b0cSWill Deacon 87c0e8b0cSWill Deacon #define GIC_FDT_IRQ_NUM_CELLS 3 97c0e8b0cSWill Deacon 107c0e8b0cSWill Deacon #define GIC_FDT_IRQ_TYPE_SPI 0 117c0e8b0cSWill Deacon #define GIC_FDT_IRQ_TYPE_PPI 1 127c0e8b0cSWill Deacon 137c0e8b0cSWill Deacon #define GIC_FDT_IRQ_PPI_CPU_SHIFT 8 147c0e8b0cSWill Deacon #define GIC_FDT_IRQ_PPI_CPU_MASK (0xff << GIC_FDT_IRQ_PPI_CPU_SHIFT) 157c0e8b0cSWill Deacon 167c0e8b0cSWill Deacon #define GIC_CPUI_CTLR_EN (1 << 0) 17f5ec570aSMarc Zyngier #define GIC_CPUI_PMR_MIN_PRIO 0xff 18f5ec570aSMarc Zyngier 19f5ec570aSMarc Zyngier #define GIC_CPUI_OFF_PMR 4 207c0e8b0cSWill Deacon 217c0e8b0cSWill Deacon #define GIC_MAX_CPUS 8 227c0e8b0cSWill Deacon #define GIC_MAX_IRQ 255 237c0e8b0cSWill Deacon 2402017c1dSAndre Przywara enum irqchip_type { 2502017c1dSAndre Przywara IRQCHIP_GICV2, 26*f6108d72SJean-Philippe Brucker IRQCHIP_GICV2M, 27bfb2c703SAndre Przywara IRQCHIP_GICV3, 2812ca1401SAndre Przywara IRQCHIP_GICV3_ITS, 2902017c1dSAndre Przywara }; 3002017c1dSAndre Przywara 317c0e8b0cSWill Deacon struct kvm; 327c0e8b0cSWill Deacon 337c0e8b0cSWill Deacon int gic__alloc_irqnum(void); 3402017c1dSAndre Przywara int gic__create(struct kvm *kvm, enum irqchip_type type); 35*f6108d72SJean-Philippe Brucker int gic__create_gicv2m_frame(struct kvm *kvm, u64 msi_frame_addr); 360063d50cSAndre Przywara void gic__generate_fdt_nodes(void *fdt, enum irqchip_type type); 377c0e8b0cSWill Deacon 387c0e8b0cSWill Deacon #endif /* ARM_COMMON__GIC_H */ 39