1 #ifndef ARM_COMMON__GIC_H 2 #define ARM_COMMON__GIC_H 3 4 #define GIC_SGI_IRQ_BASE 0 5 #define GIC_PPI_IRQ_BASE 16 6 #define GIC_SPI_IRQ_BASE 32 7 8 #define GIC_FDT_IRQ_NUM_CELLS 3 9 10 #define GIC_FDT_IRQ_TYPE_SPI 0 11 #define GIC_FDT_IRQ_TYPE_PPI 1 12 13 #define GIC_FDT_IRQ_PPI_CPU_SHIFT 8 14 #define GIC_FDT_IRQ_PPI_CPU_MASK (0xff << GIC_FDT_IRQ_PPI_CPU_SHIFT) 15 16 #define GIC_CPUI_CTLR_EN (1 << 0) 17 #define GIC_CPUI_PMR_MIN_PRIO 0xff 18 19 #define GIC_CPUI_OFF_PMR 4 20 21 #define GIC_MAX_CPUS 8 22 #define GIC_MAX_IRQ 255 23 24 #define KVM_VGIC_V2M_SIZE 0x1000 25 26 enum irqchip_type { 27 IRQCHIP_AUTO, 28 IRQCHIP_GICV2, 29 IRQCHIP_GICV2M, 30 IRQCHIP_GICV3, 31 IRQCHIP_GICV3_ITS, 32 }; 33 34 struct kvm; 35 36 int gic__alloc_irqnum(void); 37 int gic__create(struct kvm *kvm, enum irqchip_type type); 38 int gic__create_gicv2m_frame(struct kvm *kvm, u64 msi_frame_addr); 39 void gic__generate_fdt_nodes(void *fdt, enum irqchip_type type); 40 u32 gic__get_fdt_irq_cpumask(struct kvm *kvm); 41 42 int gic__add_irqfd(struct kvm *kvm, unsigned int gsi, int trigger_fd, 43 int resample_fd); 44 void gic__del_irqfd(struct kvm *kvm, unsigned int gsi, int trigger_fd); 45 #define irq__add_irqfd gic__add_irqfd 46 #define irq__del_irqfd gic__del_irqfd 47 48 #endif /* ARM_COMMON__GIC_H */ 49