1*7c0e8b0cSWill Deacon #ifndef ARM_COMMON__GIC_H 2*7c0e8b0cSWill Deacon #define ARM_COMMON__GIC_H 3*7c0e8b0cSWill Deacon 4*7c0e8b0cSWill Deacon #define GIC_SGI_IRQ_BASE 0 5*7c0e8b0cSWill Deacon #define GIC_PPI_IRQ_BASE 16 6*7c0e8b0cSWill Deacon #define GIC_SPI_IRQ_BASE 32 7*7c0e8b0cSWill Deacon 8*7c0e8b0cSWill Deacon #define GIC_FDT_IRQ_NUM_CELLS 3 9*7c0e8b0cSWill Deacon 10*7c0e8b0cSWill Deacon #define GIC_FDT_IRQ_TYPE_SPI 0 11*7c0e8b0cSWill Deacon #define GIC_FDT_IRQ_TYPE_PPI 1 12*7c0e8b0cSWill Deacon 13*7c0e8b0cSWill Deacon #define GIC_FDT_IRQ_FLAGS_EDGE_LO_HI 1 14*7c0e8b0cSWill Deacon #define GIC_FDT_IRQ_FLAGS_EDGE_HI_LO 2 15*7c0e8b0cSWill Deacon #define GIC_FDT_IRQ_FLAGS_LEVEL_HI 4 16*7c0e8b0cSWill Deacon #define GIC_FDT_IRQ_FLAGS_LEVEL_LO 8 17*7c0e8b0cSWill Deacon 18*7c0e8b0cSWill Deacon #define GIC_FDT_IRQ_PPI_CPU_SHIFT 8 19*7c0e8b0cSWill Deacon #define GIC_FDT_IRQ_PPI_CPU_MASK (0xff << GIC_FDT_IRQ_PPI_CPU_SHIFT) 20*7c0e8b0cSWill Deacon 21*7c0e8b0cSWill Deacon #define GIC_CPUI_CTLR_EN (1 << 0) 22*7c0e8b0cSWill Deacon 23*7c0e8b0cSWill Deacon #define GIC_MAX_CPUS 8 24*7c0e8b0cSWill Deacon #define GIC_MAX_IRQ 255 25*7c0e8b0cSWill Deacon 26*7c0e8b0cSWill Deacon #ifndef __ASSEMBLY__ 27*7c0e8b0cSWill Deacon struct kvm; 28*7c0e8b0cSWill Deacon 29*7c0e8b0cSWill Deacon int gic__alloc_irqnum(void); 30*7c0e8b0cSWill Deacon int gic__init_irqchip(struct kvm *kvm); 31*7c0e8b0cSWill Deacon void gic__generate_fdt_nodes(void *fdt, u32 phandle); 32*7c0e8b0cSWill Deacon 33*7c0e8b0cSWill Deacon #endif /* __ASSEMBLY__ */ 34*7c0e8b0cSWill Deacon #endif /* ARM_COMMON__GIC_H */ 35