1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "vm.h" 13 #include "pci.h" 14 #include "fwcfg.h" 15 #include "isr.h" 16 #include "desc.h" 17 #include "apic.h" 18 #include "types.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 24 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 25 26 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 27 28 u64 ia32_pat; 29 u64 ia32_efer; 30 void *io_bitmap_a, *io_bitmap_b; 31 u16 ioport; 32 33 unsigned long *pml4; 34 u64 eptp; 35 void *data_page1, *data_page2; 36 37 phys_addr_t pci_physaddr; 38 39 void *pml_log; 40 #define PML_INDEX 512 41 42 static inline unsigned ffs(unsigned x) 43 { 44 int pos = -1; 45 46 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 47 : "+r"(pos) : "rm"(x) : "eax"); 48 return pos + 1; 49 } 50 51 static inline void vmcall(void) 52 { 53 asm volatile("vmcall"); 54 } 55 56 static void basic_guest_main(void) 57 { 58 report("Basic VMX test", 1); 59 } 60 61 static int basic_exit_handler(void) 62 { 63 report("Basic VMX test", 0); 64 print_vmexit_info(); 65 return VMX_TEST_EXIT; 66 } 67 68 static void vmenter_main(void) 69 { 70 u64 rax; 71 u64 rsp, resume_rsp; 72 73 report("test vmlaunch", 1); 74 75 asm volatile( 76 "mov %%rsp, %0\n\t" 77 "mov %3, %%rax\n\t" 78 "vmcall\n\t" 79 "mov %%rax, %1\n\t" 80 "mov %%rsp, %2\n\t" 81 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 82 : "g"(0xABCD)); 83 report("test vmresume", (rax == 0xFFFF) && (rsp == resume_rsp)); 84 } 85 86 static int vmenter_exit_handler(void) 87 { 88 u64 guest_rip; 89 ulong reason; 90 91 guest_rip = vmcs_read(GUEST_RIP); 92 reason = vmcs_read(EXI_REASON) & 0xff; 93 switch (reason) { 94 case VMX_VMCALL: 95 if (regs.rax != 0xABCD) { 96 report("test vmresume", 0); 97 return VMX_TEST_VMEXIT; 98 } 99 regs.rax = 0xFFFF; 100 vmcs_write(GUEST_RIP, guest_rip + 3); 101 return VMX_TEST_RESUME; 102 default: 103 report("test vmresume", 0); 104 print_vmexit_info(); 105 } 106 return VMX_TEST_VMEXIT; 107 } 108 109 u32 preempt_scale; 110 volatile unsigned long long tsc_val; 111 volatile u32 preempt_val; 112 u64 saved_rip; 113 114 static int preemption_timer_init(struct vmcs *vmcs) 115 { 116 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 117 printf("\tPreemption timer is not supported\n"); 118 return VMX_TEST_EXIT; 119 } 120 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 121 preempt_val = 10000000; 122 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 123 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 124 125 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 126 printf("\tSave preemption value is not supported\n"); 127 128 return VMX_TEST_START; 129 } 130 131 static void preemption_timer_main(void) 132 { 133 tsc_val = rdtsc(); 134 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 135 vmx_set_test_stage(0); 136 vmcall(); 137 if (vmx_get_test_stage() == 1) 138 vmcall(); 139 } 140 vmx_set_test_stage(1); 141 while (vmx_get_test_stage() == 1) { 142 if (((rdtsc() - tsc_val) >> preempt_scale) 143 > 10 * preempt_val) { 144 vmx_set_test_stage(2); 145 vmcall(); 146 } 147 } 148 tsc_val = rdtsc(); 149 asm volatile ("hlt"); 150 vmcall(); 151 vmx_set_test_stage(5); 152 vmcall(); 153 } 154 155 static int preemption_timer_exit_handler(void) 156 { 157 bool guest_halted; 158 u64 guest_rip; 159 ulong reason; 160 u32 insn_len; 161 u32 ctrl_exit; 162 163 guest_rip = vmcs_read(GUEST_RIP); 164 reason = vmcs_read(EXI_REASON) & 0xff; 165 insn_len = vmcs_read(EXI_INST_LEN); 166 switch (reason) { 167 case VMX_PREEMPT: 168 switch (vmx_get_test_stage()) { 169 case 1: 170 case 2: 171 report("busy-wait for preemption timer", 172 ((rdtsc() - tsc_val) >> preempt_scale) >= 173 preempt_val); 174 vmx_set_test_stage(3); 175 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 176 return VMX_TEST_RESUME; 177 case 3: 178 guest_halted = 179 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 180 report("preemption timer during hlt", 181 ((rdtsc() - tsc_val) >> preempt_scale) >= 182 preempt_val && guest_halted); 183 vmx_set_test_stage(4); 184 vmcs_write(PIN_CONTROLS, 185 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 186 vmcs_write(EXI_CONTROLS, 187 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 188 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 189 return VMX_TEST_RESUME; 190 case 4: 191 report("preemption timer with 0 value", 192 saved_rip == guest_rip); 193 break; 194 default: 195 report("Invalid stage.", false); 196 print_vmexit_info(); 197 break; 198 } 199 break; 200 case VMX_VMCALL: 201 vmcs_write(GUEST_RIP, guest_rip + insn_len); 202 switch (vmx_get_test_stage()) { 203 case 0: 204 report("Keep preemption value", 205 vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val); 206 vmx_set_test_stage(1); 207 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 208 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 209 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 210 vmcs_write(EXI_CONTROLS, ctrl_exit); 211 return VMX_TEST_RESUME; 212 case 1: 213 report("Save preemption value", 214 vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val); 215 return VMX_TEST_RESUME; 216 case 2: 217 report("busy-wait for preemption timer", 0); 218 vmx_set_test_stage(3); 219 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 220 return VMX_TEST_RESUME; 221 case 3: 222 report("preemption timer during hlt", 0); 223 vmx_set_test_stage(4); 224 /* fall through */ 225 case 4: 226 vmcs_write(PIN_CONTROLS, 227 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 228 vmcs_write(PREEMPT_TIMER_VALUE, 0); 229 saved_rip = guest_rip + insn_len; 230 return VMX_TEST_RESUME; 231 case 5: 232 report("preemption timer with 0 value (vmcall stage 5)", 0); 233 break; 234 default: 235 // Should not reach here 236 report("unexpected stage, %d", false, 237 vmx_get_test_stage()); 238 print_vmexit_info(); 239 return VMX_TEST_VMEXIT; 240 } 241 break; 242 default: 243 report("Unknown exit reason, %ld", false, reason); 244 print_vmexit_info(); 245 } 246 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 247 return VMX_TEST_VMEXIT; 248 } 249 250 static void msr_bmp_init(void) 251 { 252 void *msr_bitmap; 253 u32 ctrl_cpu0; 254 255 msr_bitmap = alloc_page(); 256 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 257 ctrl_cpu0 |= CPU_MSR_BITMAP; 258 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 259 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 260 } 261 262 static void *get_msr_bitmap(void) 263 { 264 void *msr_bitmap; 265 266 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 267 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 268 } else { 269 msr_bitmap = alloc_page(); 270 memset(msr_bitmap, 0xff, PAGE_SIZE); 271 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 272 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 273 } 274 275 return msr_bitmap; 276 } 277 278 static void disable_intercept_for_x2apic_msrs(void) 279 { 280 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 281 u32 msr; 282 283 for (msr = APIC_BASE_MSR; 284 msr < (APIC_BASE_MSR+0xff); 285 msr += BITS_PER_LONG) { 286 unsigned int word = msr / BITS_PER_LONG; 287 288 msr_bitmap[word] = 0; 289 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 290 } 291 } 292 293 static int test_ctrl_pat_init(struct vmcs *vmcs) 294 { 295 u64 ctrl_ent; 296 u64 ctrl_exi; 297 298 msr_bmp_init(); 299 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 300 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 301 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 302 printf("\tSave/load PAT is not supported\n"); 303 return 1; 304 } 305 306 ctrl_ent = vmcs_read(ENT_CONTROLS); 307 ctrl_exi = vmcs_read(EXI_CONTROLS); 308 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 309 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 310 vmcs_write(ENT_CONTROLS, ctrl_ent); 311 vmcs_write(EXI_CONTROLS, ctrl_exi); 312 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 313 vmcs_write(GUEST_PAT, 0x0); 314 vmcs_write(HOST_PAT, ia32_pat); 315 return VMX_TEST_START; 316 } 317 318 static void test_ctrl_pat_main(void) 319 { 320 u64 guest_ia32_pat; 321 322 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 323 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 324 printf("\tENT_LOAD_PAT is not supported.\n"); 325 else { 326 if (guest_ia32_pat != 0) { 327 report("Entry load PAT", 0); 328 return; 329 } 330 } 331 wrmsr(MSR_IA32_CR_PAT, 0x6); 332 vmcall(); 333 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 334 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 335 report("Entry load PAT", guest_ia32_pat == ia32_pat); 336 } 337 338 static int test_ctrl_pat_exit_handler(void) 339 { 340 u64 guest_rip; 341 ulong reason; 342 u64 guest_pat; 343 344 guest_rip = vmcs_read(GUEST_RIP); 345 reason = vmcs_read(EXI_REASON) & 0xff; 346 switch (reason) { 347 case VMX_VMCALL: 348 guest_pat = vmcs_read(GUEST_PAT); 349 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 350 printf("\tEXI_SAVE_PAT is not supported\n"); 351 vmcs_write(GUEST_PAT, 0x6); 352 } else { 353 report("Exit save PAT", guest_pat == 0x6); 354 } 355 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 356 printf("\tEXI_LOAD_PAT is not supported\n"); 357 else 358 report("Exit load PAT", rdmsr(MSR_IA32_CR_PAT) == ia32_pat); 359 vmcs_write(GUEST_PAT, ia32_pat); 360 vmcs_write(GUEST_RIP, guest_rip + 3); 361 return VMX_TEST_RESUME; 362 default: 363 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 364 break; 365 } 366 return VMX_TEST_VMEXIT; 367 } 368 369 static int test_ctrl_efer_init(struct vmcs *vmcs) 370 { 371 u64 ctrl_ent; 372 u64 ctrl_exi; 373 374 msr_bmp_init(); 375 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 376 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 377 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 378 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 379 ia32_efer = rdmsr(MSR_EFER); 380 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 381 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 382 return VMX_TEST_START; 383 } 384 385 static void test_ctrl_efer_main(void) 386 { 387 u64 guest_ia32_efer; 388 389 guest_ia32_efer = rdmsr(MSR_EFER); 390 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 391 printf("\tENT_LOAD_EFER is not supported.\n"); 392 else { 393 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 394 report("Entry load EFER", 0); 395 return; 396 } 397 } 398 wrmsr(MSR_EFER, ia32_efer); 399 vmcall(); 400 guest_ia32_efer = rdmsr(MSR_EFER); 401 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 402 report("Entry load EFER", guest_ia32_efer == ia32_efer); 403 } 404 405 static int test_ctrl_efer_exit_handler(void) 406 { 407 u64 guest_rip; 408 ulong reason; 409 u64 guest_efer; 410 411 guest_rip = vmcs_read(GUEST_RIP); 412 reason = vmcs_read(EXI_REASON) & 0xff; 413 switch (reason) { 414 case VMX_VMCALL: 415 guest_efer = vmcs_read(GUEST_EFER); 416 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 417 printf("\tEXI_SAVE_EFER is not supported\n"); 418 vmcs_write(GUEST_EFER, ia32_efer); 419 } else { 420 report("Exit save EFER", guest_efer == ia32_efer); 421 } 422 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 423 printf("\tEXI_LOAD_EFER is not supported\n"); 424 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 425 } else { 426 report("Exit load EFER", rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX)); 427 } 428 vmcs_write(GUEST_PAT, ia32_efer); 429 vmcs_write(GUEST_RIP, guest_rip + 3); 430 return VMX_TEST_RESUME; 431 default: 432 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 433 break; 434 } 435 return VMX_TEST_VMEXIT; 436 } 437 438 u32 guest_cr0, guest_cr4; 439 440 static void cr_shadowing_main(void) 441 { 442 u32 cr0, cr4, tmp; 443 444 // Test read through 445 vmx_set_test_stage(0); 446 guest_cr0 = read_cr0(); 447 if (vmx_get_test_stage() == 1) 448 report("Read through CR0", 0); 449 else 450 vmcall(); 451 vmx_set_test_stage(1); 452 guest_cr4 = read_cr4(); 453 if (vmx_get_test_stage() == 2) 454 report("Read through CR4", 0); 455 else 456 vmcall(); 457 // Test write through 458 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 459 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 460 vmx_set_test_stage(2); 461 write_cr0(guest_cr0); 462 if (vmx_get_test_stage() == 3) 463 report("Write throuth CR0", 0); 464 else 465 vmcall(); 466 vmx_set_test_stage(3); 467 write_cr4(guest_cr4); 468 if (vmx_get_test_stage() == 4) 469 report("Write through CR4", 0); 470 else 471 vmcall(); 472 // Test read shadow 473 vmx_set_test_stage(4); 474 vmcall(); 475 cr0 = read_cr0(); 476 if (vmx_get_test_stage() != 5) 477 report("Read shadowing CR0", cr0 == guest_cr0); 478 vmx_set_test_stage(5); 479 cr4 = read_cr4(); 480 if (vmx_get_test_stage() != 6) 481 report("Read shadowing CR4", cr4 == guest_cr4); 482 // Test write shadow (same value with shadow) 483 vmx_set_test_stage(6); 484 write_cr0(guest_cr0); 485 if (vmx_get_test_stage() == 7) 486 report("Write shadowing CR0 (same value with shadow)", 0); 487 else 488 vmcall(); 489 vmx_set_test_stage(7); 490 write_cr4(guest_cr4); 491 if (vmx_get_test_stage() == 8) 492 report("Write shadowing CR4 (same value with shadow)", 0); 493 else 494 vmcall(); 495 // Test write shadow (different value) 496 vmx_set_test_stage(8); 497 tmp = guest_cr0 ^ X86_CR0_TS; 498 asm volatile("mov %0, %%rsi\n\t" 499 "mov %%rsi, %%cr0\n\t" 500 ::"m"(tmp) 501 :"rsi", "memory", "cc"); 502 report("Write shadowing different X86_CR0_TS", vmx_get_test_stage() == 9); 503 vmx_set_test_stage(9); 504 tmp = guest_cr0 ^ X86_CR0_MP; 505 asm volatile("mov %0, %%rsi\n\t" 506 "mov %%rsi, %%cr0\n\t" 507 ::"m"(tmp) 508 :"rsi", "memory", "cc"); 509 report("Write shadowing different X86_CR0_MP", vmx_get_test_stage() == 10); 510 vmx_set_test_stage(10); 511 tmp = guest_cr4 ^ X86_CR4_TSD; 512 asm volatile("mov %0, %%rsi\n\t" 513 "mov %%rsi, %%cr4\n\t" 514 ::"m"(tmp) 515 :"rsi", "memory", "cc"); 516 report("Write shadowing different X86_CR4_TSD", vmx_get_test_stage() == 11); 517 vmx_set_test_stage(11); 518 tmp = guest_cr4 ^ X86_CR4_DE; 519 asm volatile("mov %0, %%rsi\n\t" 520 "mov %%rsi, %%cr4\n\t" 521 ::"m"(tmp) 522 :"rsi", "memory", "cc"); 523 report("Write shadowing different X86_CR4_DE", vmx_get_test_stage() == 12); 524 } 525 526 static int cr_shadowing_exit_handler(void) 527 { 528 u64 guest_rip; 529 ulong reason; 530 u32 insn_len; 531 u32 exit_qual; 532 533 guest_rip = vmcs_read(GUEST_RIP); 534 reason = vmcs_read(EXI_REASON) & 0xff; 535 insn_len = vmcs_read(EXI_INST_LEN); 536 exit_qual = vmcs_read(EXI_QUALIFICATION); 537 switch (reason) { 538 case VMX_VMCALL: 539 switch (vmx_get_test_stage()) { 540 case 0: 541 report("Read through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 542 break; 543 case 1: 544 report("Read through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 545 break; 546 case 2: 547 report("Write through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 548 break; 549 case 3: 550 report("Write through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 551 break; 552 case 4: 553 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 554 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 555 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 556 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 557 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 558 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 559 break; 560 case 6: 561 report("Write shadowing CR0 (same value)", 562 guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP))); 563 break; 564 case 7: 565 report("Write shadowing CR4 (same value)", 566 guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE))); 567 break; 568 default: 569 // Should not reach here 570 report("unexpected stage, %d", false, 571 vmx_get_test_stage()); 572 print_vmexit_info(); 573 return VMX_TEST_VMEXIT; 574 } 575 vmcs_write(GUEST_RIP, guest_rip + insn_len); 576 return VMX_TEST_RESUME; 577 case VMX_CR: 578 switch (vmx_get_test_stage()) { 579 case 4: 580 report("Read shadowing CR0", 0); 581 vmx_inc_test_stage(); 582 break; 583 case 5: 584 report("Read shadowing CR4", 0); 585 vmx_inc_test_stage(); 586 break; 587 case 6: 588 report("Write shadowing CR0 (same value)", 0); 589 vmx_inc_test_stage(); 590 break; 591 case 7: 592 report("Write shadowing CR4 (same value)", 0); 593 vmx_inc_test_stage(); 594 break; 595 case 8: 596 case 9: 597 // 0x600 encodes "mov %esi, %cr0" 598 if (exit_qual == 0x600) 599 vmx_inc_test_stage(); 600 break; 601 case 10: 602 case 11: 603 // 0x604 encodes "mov %esi, %cr4" 604 if (exit_qual == 0x604) 605 vmx_inc_test_stage(); 606 break; 607 default: 608 // Should not reach here 609 report("unexpected stage, %d", false, 610 vmx_get_test_stage()); 611 print_vmexit_info(); 612 return VMX_TEST_VMEXIT; 613 } 614 vmcs_write(GUEST_RIP, guest_rip + insn_len); 615 return VMX_TEST_RESUME; 616 default: 617 report("Unknown exit reason, %ld", false, reason); 618 print_vmexit_info(); 619 } 620 return VMX_TEST_VMEXIT; 621 } 622 623 static int iobmp_init(struct vmcs *vmcs) 624 { 625 u32 ctrl_cpu0; 626 627 io_bitmap_a = alloc_page(); 628 io_bitmap_b = alloc_page(); 629 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 630 ctrl_cpu0 |= CPU_IO_BITMAP; 631 ctrl_cpu0 &= (~CPU_IO); 632 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 633 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 634 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 635 return VMX_TEST_START; 636 } 637 638 static void iobmp_main(void) 639 { 640 // stage 0, test IO pass 641 vmx_set_test_stage(0); 642 inb(0x5000); 643 outb(0x0, 0x5000); 644 report("I/O bitmap - I/O pass", vmx_get_test_stage() == 0); 645 // test IO width, in/out 646 ((u8 *)io_bitmap_a)[0] = 0xFF; 647 vmx_set_test_stage(2); 648 inb(0x0); 649 report("I/O bitmap - trap in", vmx_get_test_stage() == 3); 650 vmx_set_test_stage(3); 651 outw(0x0, 0x0); 652 report("I/O bitmap - trap out", vmx_get_test_stage() == 4); 653 vmx_set_test_stage(4); 654 inl(0x0); 655 report("I/O bitmap - I/O width, long", vmx_get_test_stage() == 5); 656 // test low/high IO port 657 vmx_set_test_stage(5); 658 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 659 inb(0x5000); 660 report("I/O bitmap - I/O port, low part", vmx_get_test_stage() == 6); 661 vmx_set_test_stage(6); 662 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 663 inb(0x9000); 664 report("I/O bitmap - I/O port, high part", vmx_get_test_stage() == 7); 665 // test partial pass 666 vmx_set_test_stage(7); 667 inl(0x4FFF); 668 report("I/O bitmap - partial pass", vmx_get_test_stage() == 8); 669 // test overrun 670 vmx_set_test_stage(8); 671 memset(io_bitmap_a, 0x0, PAGE_SIZE); 672 memset(io_bitmap_b, 0x0, PAGE_SIZE); 673 inl(0xFFFF); 674 report("I/O bitmap - overrun", vmx_get_test_stage() == 9); 675 vmx_set_test_stage(9); 676 vmcall(); 677 outb(0x0, 0x0); 678 report("I/O bitmap - ignore unconditional exiting", 679 vmx_get_test_stage() == 9); 680 vmx_set_test_stage(10); 681 vmcall(); 682 outb(0x0, 0x0); 683 report("I/O bitmap - unconditional exiting", 684 vmx_get_test_stage() == 11); 685 } 686 687 static int iobmp_exit_handler(void) 688 { 689 u64 guest_rip; 690 ulong reason, exit_qual; 691 u32 insn_len, ctrl_cpu0; 692 693 guest_rip = vmcs_read(GUEST_RIP); 694 reason = vmcs_read(EXI_REASON) & 0xff; 695 exit_qual = vmcs_read(EXI_QUALIFICATION); 696 insn_len = vmcs_read(EXI_INST_LEN); 697 switch (reason) { 698 case VMX_IO: 699 switch (vmx_get_test_stage()) { 700 case 0: 701 case 1: 702 vmx_inc_test_stage(); 703 break; 704 case 2: 705 report("I/O bitmap - I/O width, byte", 706 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE); 707 report("I/O bitmap - I/O direction, in", exit_qual & VMX_IO_IN); 708 vmx_inc_test_stage(); 709 break; 710 case 3: 711 report("I/O bitmap - I/O width, word", 712 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD); 713 report("I/O bitmap - I/O direction, out", 714 !(exit_qual & VMX_IO_IN)); 715 vmx_inc_test_stage(); 716 break; 717 case 4: 718 report("I/O bitmap - I/O width, long", 719 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG); 720 vmx_inc_test_stage(); 721 break; 722 case 5: 723 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 724 vmx_inc_test_stage(); 725 break; 726 case 6: 727 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 728 vmx_inc_test_stage(); 729 break; 730 case 7: 731 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 732 vmx_inc_test_stage(); 733 break; 734 case 8: 735 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 736 vmx_inc_test_stage(); 737 break; 738 case 9: 739 case 10: 740 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 741 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 742 vmx_inc_test_stage(); 743 break; 744 default: 745 // Should not reach here 746 report("unexpected stage, %d", false, 747 vmx_get_test_stage()); 748 print_vmexit_info(); 749 return VMX_TEST_VMEXIT; 750 } 751 vmcs_write(GUEST_RIP, guest_rip + insn_len); 752 return VMX_TEST_RESUME; 753 case VMX_VMCALL: 754 switch (vmx_get_test_stage()) { 755 case 9: 756 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 757 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 758 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 759 break; 760 case 10: 761 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 762 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 763 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 764 break; 765 default: 766 // Should not reach here 767 report("unexpected stage, %d", false, 768 vmx_get_test_stage()); 769 print_vmexit_info(); 770 return VMX_TEST_VMEXIT; 771 } 772 vmcs_write(GUEST_RIP, guest_rip + insn_len); 773 return VMX_TEST_RESUME; 774 default: 775 printf("guest_rip = %#lx\n", guest_rip); 776 printf("\tERROR : Undefined exit reason, reason = %ld.\n", reason); 777 break; 778 } 779 return VMX_TEST_VMEXIT; 780 } 781 782 #define INSN_CPU0 0 783 #define INSN_CPU1 1 784 #define INSN_ALWAYS_TRAP 2 785 786 #define FIELD_EXIT_QUAL (1 << 0) 787 #define FIELD_INSN_INFO (1 << 1) 788 789 asm( 790 "insn_hlt: hlt;ret\n\t" 791 "insn_invlpg: invlpg 0x12345678;ret\n\t" 792 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 793 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 794 "insn_rdtsc: rdtsc;ret\n\t" 795 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 796 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 797 #ifdef __x86_64__ 798 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 799 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 800 #endif 801 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 802 "insn_pause: pause;ret\n\t" 803 "insn_wbinvd: wbinvd;ret\n\t" 804 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 805 "insn_invd: invd;ret\n\t" 806 "insn_sgdt: sgdt gdt64_desc;ret\n\t" 807 "insn_lgdt: lgdt gdt64_desc;ret\n\t" 808 "insn_sidt: sidt idt_descr;ret\n\t" 809 "insn_lidt: lidt idt_descr;ret\n\t" 810 "insn_sldt: sldt %ax;ret\n\t" 811 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 812 "insn_str: str %ax;ret\n\t" 813 "insn_rdrand: rdrand %rax;ret\n\t" 814 "insn_rdseed: rdseed %rax;ret\n\t" 815 ); 816 extern void insn_hlt(void); 817 extern void insn_invlpg(void); 818 extern void insn_mwait(void); 819 extern void insn_rdpmc(void); 820 extern void insn_rdtsc(void); 821 extern void insn_cr3_load(void); 822 extern void insn_cr3_store(void); 823 #ifdef __x86_64__ 824 extern void insn_cr8_load(void); 825 extern void insn_cr8_store(void); 826 #endif 827 extern void insn_monitor(void); 828 extern void insn_pause(void); 829 extern void insn_wbinvd(void); 830 extern void insn_sgdt(void); 831 extern void insn_lgdt(void); 832 extern void insn_sidt(void); 833 extern void insn_lidt(void); 834 extern void insn_sldt(void); 835 extern void insn_lldt(void); 836 extern void insn_str(void); 837 extern void insn_cpuid(void); 838 extern void insn_invd(void); 839 extern void insn_rdrand(void); 840 extern void insn_rdseed(void); 841 842 u32 cur_insn; 843 u64 cr3; 844 845 #define X86_FEATURE_MONITOR (1 << 3) 846 847 typedef bool (*supported_fn)(void); 848 849 static bool monitor_supported(void) 850 { 851 return this_cpu_has(X86_FEATURE_MWAIT); 852 } 853 854 struct insn_table { 855 const char *name; 856 u32 flag; 857 void (*insn_func)(void); 858 u32 type; 859 u32 reason; 860 ulong exit_qual; 861 u32 insn_info; 862 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 863 // which field need to be tested, reason is always tested 864 u32 test_field; 865 const supported_fn supported_fn; 866 u8 disabled; 867 }; 868 869 /* 870 * Add more test cases of instruction intercept here. Elements in this 871 * table is: 872 * name/control flag/insn function/type/exit reason/exit qulification/ 873 * instruction info/field to test 874 * The last field defines which fields (exit_qual and insn_info) need to be 875 * tested in exit handler. If set to 0, only "reason" is checked. 876 */ 877 static struct insn_table insn_table[] = { 878 // Flags for Primary Processor-Based VM-Execution Controls 879 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 880 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 881 0x12345678, 0, FIELD_EXIT_QUAL}, 882 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0, &monitor_supported}, 883 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 884 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 885 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 886 FIELD_EXIT_QUAL}, 887 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 888 FIELD_EXIT_QUAL}, 889 #ifdef __x86_64__ 890 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 891 FIELD_EXIT_QUAL}, 892 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 893 FIELD_EXIT_QUAL}, 894 #endif 895 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0, &monitor_supported}, 896 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 897 // Flags for Secondary Processor-Based VM-Execution Controls 898 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 899 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 900 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 901 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 902 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 903 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 904 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 905 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 906 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 907 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 908 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 909 // Instructions always trap 910 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 911 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 912 // Instructions never trap 913 {NULL}, 914 }; 915 916 static int insn_intercept_init(struct vmcs *vmcs) 917 { 918 u32 ctrl_cpu, cur_insn; 919 920 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 921 ctrl_cpu &= ctrl_cpu_rev[0].clr; 922 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 923 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 924 cr3 = read_cr3(); 925 926 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 927 if (insn_table[cur_insn].supported_fn == NULL) 928 continue; 929 insn_table[cur_insn].disabled = !insn_table[cur_insn].supported_fn(); 930 } 931 return VMX_TEST_START; 932 } 933 934 static void insn_intercept_main(void) 935 { 936 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 937 vmx_set_test_stage(cur_insn * 2); 938 if ((insn_table[cur_insn].type == INSN_CPU0 && 939 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 940 (insn_table[cur_insn].type == INSN_CPU1 && 941 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 942 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 943 insn_table[cur_insn].type - INSN_CPU0, 944 insn_table[cur_insn].name); 945 continue; 946 } 947 948 if (insn_table[cur_insn].disabled) { 949 printf("\tFeature required for %s is not supported.\n", 950 insn_table[cur_insn].name); 951 continue; 952 } 953 954 if ((insn_table[cur_insn].type == INSN_CPU0 && 955 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 956 (insn_table[cur_insn].type == INSN_CPU1 && 957 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 958 /* skip hlt, it stalls the guest and is tested below */ 959 if (insn_table[cur_insn].insn_func != insn_hlt) 960 insn_table[cur_insn].insn_func(); 961 report("execute %s", vmx_get_test_stage() == cur_insn * 2, 962 insn_table[cur_insn].name); 963 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 964 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 965 insn_table[cur_insn].type - INSN_CPU0, 966 insn_table[cur_insn].name); 967 968 vmcall(); 969 970 insn_table[cur_insn].insn_func(); 971 report("intercept %s", vmx_get_test_stage() == cur_insn * 2 + 1, 972 insn_table[cur_insn].name); 973 974 vmx_set_test_stage(cur_insn * 2 + 1); 975 vmcall(); 976 } 977 } 978 979 static int insn_intercept_exit_handler(void) 980 { 981 u64 guest_rip; 982 u32 reason; 983 ulong exit_qual; 984 u32 insn_len; 985 u32 insn_info; 986 bool pass; 987 988 guest_rip = vmcs_read(GUEST_RIP); 989 reason = vmcs_read(EXI_REASON) & 0xff; 990 exit_qual = vmcs_read(EXI_QUALIFICATION); 991 insn_len = vmcs_read(EXI_INST_LEN); 992 insn_info = vmcs_read(EXI_INST_INFO); 993 994 if (reason == VMX_VMCALL) { 995 u32 val = 0; 996 997 if (insn_table[cur_insn].type == INSN_CPU0) 998 val = vmcs_read(CPU_EXEC_CTRL0); 999 else if (insn_table[cur_insn].type == INSN_CPU1) 1000 val = vmcs_read(CPU_EXEC_CTRL1); 1001 1002 if (vmx_get_test_stage() & 1) 1003 val &= ~insn_table[cur_insn].flag; 1004 else 1005 val |= insn_table[cur_insn].flag; 1006 1007 if (insn_table[cur_insn].type == INSN_CPU0) 1008 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 1009 else if (insn_table[cur_insn].type == INSN_CPU1) 1010 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 1011 } else { 1012 pass = (cur_insn * 2 == vmx_get_test_stage()) && 1013 insn_table[cur_insn].reason == reason; 1014 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 1015 insn_table[cur_insn].exit_qual != exit_qual) 1016 pass = false; 1017 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 1018 insn_table[cur_insn].insn_info != insn_info) 1019 pass = false; 1020 if (pass) 1021 vmx_inc_test_stage(); 1022 } 1023 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1024 return VMX_TEST_RESUME; 1025 } 1026 1027 /** 1028 * __setup_ept - Setup the VMCS fields to enable Extended Page Tables (EPT) 1029 * @hpa: Host physical address of the top-level, a.k.a. root, EPT table 1030 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1031 * 1032 * Returns 0 on success, 1 on failure. 1033 * 1034 * Note that @hpa doesn't need to point at actual memory if VM-Launch is 1035 * expected to fail, e.g. setup_dummy_ept() arbitrarily passes '0' to satisfy 1036 * the various EPTP consistency checks, but doesn't ensure backing for HPA '0'. 1037 */ 1038 static int __setup_ept(u64 hpa, bool enable_ad) 1039 { 1040 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1041 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1042 printf("\tEPT is not supported"); 1043 return 1; 1044 } 1045 if (!(ept_vpid.val & EPT_CAP_WB)) { 1046 printf("WB memtype for EPT walks not supported\n"); 1047 return 1; 1048 } 1049 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1050 printf("\tPWL4 is not supported\n"); 1051 return 1; 1052 } 1053 1054 eptp = EPT_MEM_TYPE_WB; 1055 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1056 eptp |= hpa; 1057 if (enable_ad) 1058 eptp |= EPTP_AD_FLAG; 1059 1060 vmcs_write(EPTP, eptp); 1061 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1062 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1063 1064 return 0; 1065 } 1066 1067 /** 1068 * setup_ept - Enable Extended Page Tables (EPT) and setup an identity map 1069 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1070 * 1071 * Returns 0 on success, 1 on failure. 1072 * 1073 * This is the "real" function for setting up EPT tables, i.e. use this for 1074 * tests that need to run code in the guest with EPT enabled. 1075 */ 1076 static int setup_ept(bool enable_ad) 1077 { 1078 unsigned long end_of_memory; 1079 1080 pml4 = alloc_page(); 1081 1082 if (__setup_ept(virt_to_phys(pml4), enable_ad)) 1083 return 1; 1084 1085 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1086 if (end_of_memory < (1ul << 32)) 1087 end_of_memory = (1ul << 32); 1088 /* Cannot use large EPT pages if we need to track EPT 1089 * accessed/dirty bits at 4K granularity. 1090 */ 1091 setup_ept_range(pml4, 0, end_of_memory, 0, 1092 !enable_ad && ept_2m_supported(), 1093 EPT_WA | EPT_RA | EPT_EA); 1094 return 0; 1095 } 1096 1097 /** 1098 * setup_dummy_ept - Enable Extended Page Tables (EPT) with a dummy root HPA 1099 * 1100 * Setup EPT using a semi-arbitrary dummy root HPA. This function is intended 1101 * for use by tests that need EPT enabled to verify dependent VMCS controls 1102 * but never expect to fully enter the guest, i.e. don't need setup the actual 1103 * EPT tables. 1104 */ 1105 static void setup_dummy_ept(void) 1106 { 1107 if (__setup_ept(0, false)) 1108 report_abort("EPT setup unexpectedly failed"); 1109 } 1110 1111 static int enable_unrestricted_guest(void) 1112 { 1113 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1114 !(ctrl_cpu_rev[1].clr & CPU_URG) || 1115 !(ctrl_cpu_rev[1].clr & CPU_EPT)) 1116 return 1; 1117 1118 setup_dummy_ept(); 1119 1120 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 1121 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 1122 1123 return 0; 1124 } 1125 1126 static void ept_enable_ad_bits(void) 1127 { 1128 eptp |= EPTP_AD_FLAG; 1129 vmcs_write(EPTP, eptp); 1130 } 1131 1132 static void ept_disable_ad_bits(void) 1133 { 1134 eptp &= ~EPTP_AD_FLAG; 1135 vmcs_write(EPTP, eptp); 1136 } 1137 1138 static void ept_enable_ad_bits_or_skip_test(void) 1139 { 1140 if (!ept_ad_bits_supported()) 1141 test_skip("EPT AD bits not supported."); 1142 ept_enable_ad_bits(); 1143 } 1144 1145 static int apic_version; 1146 1147 static int ept_init_common(bool have_ad) 1148 { 1149 int ret; 1150 struct pci_dev pcidev; 1151 1152 if (setup_ept(have_ad)) 1153 return VMX_TEST_EXIT; 1154 data_page1 = alloc_page(); 1155 data_page2 = alloc_page(); 1156 *((u32 *)data_page1) = MAGIC_VAL_1; 1157 *((u32 *)data_page2) = MAGIC_VAL_2; 1158 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1159 EPT_RA | EPT_WA | EPT_EA); 1160 1161 apic_version = apic_read(APIC_LVR); 1162 1163 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1164 if (ret != PCIDEVADDR_INVALID) { 1165 pci_dev_init(&pcidev, ret); 1166 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1167 } 1168 1169 return VMX_TEST_START; 1170 } 1171 1172 static int ept_init(struct vmcs *vmcs) 1173 { 1174 return ept_init_common(false); 1175 } 1176 1177 static void ept_common(void) 1178 { 1179 vmx_set_test_stage(0); 1180 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1181 *((u32 *)data_page1) != MAGIC_VAL_1) 1182 report("EPT basic framework - read", 0); 1183 else { 1184 *((u32 *)data_page2) = MAGIC_VAL_3; 1185 vmcall(); 1186 if (vmx_get_test_stage() == 1) { 1187 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1188 *((u32 *)data_page2) == MAGIC_VAL_2) 1189 report("EPT basic framework", 1); 1190 else 1191 report("EPT basic framework - remap", 1); 1192 } 1193 } 1194 // Test EPT Misconfigurations 1195 vmx_set_test_stage(1); 1196 vmcall(); 1197 *((u32 *)data_page1) = MAGIC_VAL_1; 1198 if (vmx_get_test_stage() != 2) { 1199 report("EPT misconfigurations", 0); 1200 goto t1; 1201 } 1202 vmx_set_test_stage(2); 1203 vmcall(); 1204 *((u32 *)data_page1) = MAGIC_VAL_1; 1205 report("EPT misconfigurations", vmx_get_test_stage() == 3); 1206 t1: 1207 // Test EPT violation 1208 vmx_set_test_stage(3); 1209 vmcall(); 1210 *((u32 *)data_page1) = MAGIC_VAL_1; 1211 report("EPT violation - page permission", vmx_get_test_stage() == 4); 1212 // Violation caused by EPT paging structure 1213 vmx_set_test_stage(4); 1214 vmcall(); 1215 *((u32 *)data_page1) = MAGIC_VAL_2; 1216 report("EPT violation - paging structure", vmx_get_test_stage() == 5); 1217 1218 // MMIO Read/Write 1219 vmx_set_test_stage(5); 1220 vmcall(); 1221 1222 *(u32 volatile *)pci_physaddr; 1223 report("MMIO EPT violation - read", vmx_get_test_stage() == 6); 1224 1225 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1226 report("MMIO EPT violation - write", vmx_get_test_stage() == 7); 1227 } 1228 1229 static void ept_main(void) 1230 { 1231 ept_common(); 1232 1233 // Test EPT access to L1 MMIO 1234 vmx_set_test_stage(7); 1235 report("EPT - MMIO access", *((u32 *)0xfee00030UL) == apic_version); 1236 1237 // Test invalid operand for INVEPT 1238 vmcall(); 1239 report("EPT - unsupported INVEPT", vmx_get_test_stage() == 8); 1240 } 1241 1242 static bool invept_test(int type, u64 eptp) 1243 { 1244 bool ret, supported; 1245 1246 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1247 ret = invept(type, eptp); 1248 1249 if (ret == !supported) 1250 return false; 1251 1252 if (!supported) 1253 printf("WARNING: unsupported invept passed!\n"); 1254 else 1255 printf("WARNING: invept failed!\n"); 1256 1257 return true; 1258 } 1259 1260 static int pml_exit_handler(void) 1261 { 1262 u16 index, count; 1263 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1264 u64 *pmlbuf = pml_log; 1265 u64 guest_rip = vmcs_read(GUEST_RIP);; 1266 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1267 u32 insn_len = vmcs_read(EXI_INST_LEN); 1268 1269 switch (reason) { 1270 case VMX_VMCALL: 1271 switch (vmx_get_test_stage()) { 1272 case 0: 1273 index = vmcs_read(GUEST_PML_INDEX); 1274 for (count = index + 1; count < PML_INDEX; count++) { 1275 if (pmlbuf[count] == (u64)data_page2) { 1276 vmx_inc_test_stage(); 1277 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1278 break; 1279 } 1280 } 1281 break; 1282 case 1: 1283 index = vmcs_read(GUEST_PML_INDEX); 1284 /* Keep clearing the dirty bit till a overflow */ 1285 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1286 break; 1287 default: 1288 report("unexpected stage, %d.", false, 1289 vmx_get_test_stage()); 1290 print_vmexit_info(); 1291 return VMX_TEST_VMEXIT; 1292 } 1293 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1294 return VMX_TEST_RESUME; 1295 case VMX_PML_FULL: 1296 vmx_inc_test_stage(); 1297 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1298 return VMX_TEST_RESUME; 1299 default: 1300 report("Unknown exit reason, %ld", false, reason); 1301 print_vmexit_info(); 1302 } 1303 return VMX_TEST_VMEXIT; 1304 } 1305 1306 static int ept_exit_handler_common(bool have_ad) 1307 { 1308 u64 guest_rip; 1309 u64 guest_cr3; 1310 ulong reason; 1311 u32 insn_len; 1312 u32 exit_qual; 1313 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte; 1314 1315 guest_rip = vmcs_read(GUEST_RIP); 1316 guest_cr3 = vmcs_read(GUEST_CR3); 1317 reason = vmcs_read(EXI_REASON) & 0xff; 1318 insn_len = vmcs_read(EXI_INST_LEN); 1319 exit_qual = vmcs_read(EXI_QUALIFICATION); 1320 switch (reason) { 1321 case VMX_VMCALL: 1322 switch (vmx_get_test_stage()) { 1323 case 0: 1324 check_ept_ad(pml4, guest_cr3, 1325 (unsigned long)data_page1, 1326 have_ad ? EPT_ACCESS_FLAG : 0, 1327 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1328 check_ept_ad(pml4, guest_cr3, 1329 (unsigned long)data_page2, 1330 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1331 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1332 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1333 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1334 if (have_ad) 1335 ept_sync(INVEPT_SINGLE, eptp);; 1336 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1337 *((u32 *)data_page2) == MAGIC_VAL_2) { 1338 vmx_inc_test_stage(); 1339 install_ept(pml4, (unsigned long)data_page2, 1340 (unsigned long)data_page2, 1341 EPT_RA | EPT_WA | EPT_EA); 1342 } else 1343 report("EPT basic framework - write", 0); 1344 break; 1345 case 1: 1346 install_ept(pml4, (unsigned long)data_page1, 1347 (unsigned long)data_page1, EPT_WA); 1348 ept_sync(INVEPT_SINGLE, eptp); 1349 break; 1350 case 2: 1351 install_ept(pml4, (unsigned long)data_page1, 1352 (unsigned long)data_page1, 1353 EPT_RA | EPT_WA | EPT_EA | 1354 (2 << EPT_MEM_TYPE_SHIFT)); 1355 ept_sync(INVEPT_SINGLE, eptp); 1356 break; 1357 case 3: 1358 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1359 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1360 1, &data_page1_pte)); 1361 set_ept_pte(pml4, (unsigned long)data_page1, 1362 1, data_page1_pte & ~EPT_PRESENT); 1363 ept_sync(INVEPT_SINGLE, eptp); 1364 break; 1365 case 4: 1366 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1367 2, &data_page1_pte)); 1368 data_page1_pte &= PAGE_MASK; 1369 TEST_ASSERT(get_ept_pte(pml4, data_page1_pte, 1370 2, &data_page1_pte_pte)); 1371 set_ept_pte(pml4, data_page1_pte, 2, 1372 data_page1_pte_pte & ~EPT_PRESENT); 1373 ept_sync(INVEPT_SINGLE, eptp); 1374 break; 1375 case 5: 1376 install_ept(pml4, (unsigned long)pci_physaddr, 1377 (unsigned long)pci_physaddr, 0); 1378 ept_sync(INVEPT_SINGLE, eptp); 1379 break; 1380 case 7: 1381 if (!invept_test(0, eptp)) 1382 vmx_inc_test_stage(); 1383 break; 1384 // Should not reach here 1385 default: 1386 report("ERROR - unexpected stage, %d.", false, 1387 vmx_get_test_stage()); 1388 print_vmexit_info(); 1389 return VMX_TEST_VMEXIT; 1390 } 1391 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1392 return VMX_TEST_RESUME; 1393 case VMX_EPT_MISCONFIG: 1394 switch (vmx_get_test_stage()) { 1395 case 1: 1396 case 2: 1397 vmx_inc_test_stage(); 1398 install_ept(pml4, (unsigned long)data_page1, 1399 (unsigned long)data_page1, 1400 EPT_RA | EPT_WA | EPT_EA); 1401 ept_sync(INVEPT_SINGLE, eptp); 1402 break; 1403 // Should not reach here 1404 default: 1405 report("ERROR - unexpected stage, %d.", false, 1406 vmx_get_test_stage()); 1407 print_vmexit_info(); 1408 return VMX_TEST_VMEXIT; 1409 } 1410 return VMX_TEST_RESUME; 1411 case VMX_EPT_VIOLATION: 1412 /* 1413 * Exit-qualifications are masked not to account for advanced 1414 * VM-exit information. Once KVM supports this feature, this 1415 * masking should be removed. 1416 */ 1417 exit_qual &= ~EPT_VLT_GUEST_MASK; 1418 1419 switch(vmx_get_test_stage()) { 1420 case 3: 1421 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1422 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1423 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1424 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1425 EPT_VLT_PADDR)) 1426 vmx_inc_test_stage(); 1427 set_ept_pte(pml4, (unsigned long)data_page1, 1428 1, data_page1_pte | (EPT_PRESENT)); 1429 ept_sync(INVEPT_SINGLE, eptp); 1430 break; 1431 case 4: 1432 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1433 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1434 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1435 if (exit_qual == (EPT_VLT_RD | 1436 (have_ad ? EPT_VLT_WR : 0) | 1437 EPT_VLT_LADDR_VLD)) 1438 vmx_inc_test_stage(); 1439 set_ept_pte(pml4, data_page1_pte, 2, 1440 data_page1_pte_pte | (EPT_PRESENT)); 1441 ept_sync(INVEPT_SINGLE, eptp); 1442 break; 1443 case 5: 1444 if (exit_qual & EPT_VLT_RD) 1445 vmx_inc_test_stage(); 1446 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1447 1, &memaddr_pte)); 1448 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1449 ept_sync(INVEPT_SINGLE, eptp); 1450 break; 1451 case 6: 1452 if (exit_qual & EPT_VLT_WR) 1453 vmx_inc_test_stage(); 1454 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1455 1, &memaddr_pte)); 1456 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1457 ept_sync(INVEPT_SINGLE, eptp); 1458 break; 1459 default: 1460 // Should not reach here 1461 report("ERROR : unexpected stage, %d", false, 1462 vmx_get_test_stage()); 1463 print_vmexit_info(); 1464 return VMX_TEST_VMEXIT; 1465 } 1466 return VMX_TEST_RESUME; 1467 default: 1468 report("Unknown exit reason, %ld", false, reason); 1469 print_vmexit_info(); 1470 } 1471 return VMX_TEST_VMEXIT; 1472 } 1473 1474 static int ept_exit_handler(void) 1475 { 1476 return ept_exit_handler_common(false); 1477 } 1478 1479 static int eptad_init(struct vmcs *vmcs) 1480 { 1481 int r = ept_init_common(true); 1482 1483 if (r == VMX_TEST_EXIT) 1484 return r; 1485 1486 if ((rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & EPT_CAP_AD_FLAG) == 0) { 1487 printf("\tEPT A/D bits are not supported"); 1488 return VMX_TEST_EXIT; 1489 } 1490 1491 return r; 1492 } 1493 1494 static int pml_init(struct vmcs *vmcs) 1495 { 1496 u32 ctrl_cpu; 1497 int r = eptad_init(vmcs); 1498 1499 if (r == VMX_TEST_EXIT) 1500 return r; 1501 1502 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1503 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1504 printf("\tPML is not supported"); 1505 return VMX_TEST_EXIT; 1506 } 1507 1508 pml_log = alloc_page(); 1509 vmcs_write(PMLADDR, (u64)pml_log); 1510 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1511 1512 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1513 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1514 1515 return VMX_TEST_START; 1516 } 1517 1518 static void pml_main(void) 1519 { 1520 int count = 0; 1521 1522 vmx_set_test_stage(0); 1523 *((u32 *)data_page2) = 0x1; 1524 vmcall(); 1525 report("PML - Dirty GPA Logging", vmx_get_test_stage() == 1); 1526 1527 while (vmx_get_test_stage() == 1) { 1528 vmcall(); 1529 *((u32 *)data_page2) = 0x1; 1530 if (count++ > PML_INDEX) 1531 break; 1532 } 1533 report("PML Full Event", vmx_get_test_stage() == 2); 1534 } 1535 1536 static void eptad_main(void) 1537 { 1538 ept_common(); 1539 } 1540 1541 static int eptad_exit_handler(void) 1542 { 1543 return ept_exit_handler_common(true); 1544 } 1545 1546 static bool invvpid_test(int type, u16 vpid) 1547 { 1548 bool ret, supported; 1549 1550 supported = ept_vpid.val & 1551 (VPID_CAP_INVVPID_ADDR >> INVVPID_ADDR << type); 1552 ret = invvpid(type, vpid, 0); 1553 1554 if (ret == !supported) 1555 return false; 1556 1557 if (!supported) 1558 printf("WARNING: unsupported invvpid passed!\n"); 1559 else 1560 printf("WARNING: invvpid failed!\n"); 1561 1562 return true; 1563 } 1564 1565 static int vpid_init(struct vmcs *vmcs) 1566 { 1567 u32 ctrl_cpu1; 1568 1569 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1570 !(ctrl_cpu_rev[1].clr & CPU_VPID)) { 1571 printf("\tVPID is not supported"); 1572 return VMX_TEST_EXIT; 1573 } 1574 1575 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1576 ctrl_cpu1 |= CPU_VPID; 1577 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1578 return VMX_TEST_START; 1579 } 1580 1581 static void vpid_main(void) 1582 { 1583 vmx_set_test_stage(0); 1584 vmcall(); 1585 report("INVVPID SINGLE ADDRESS", vmx_get_test_stage() == 1); 1586 vmx_set_test_stage(2); 1587 vmcall(); 1588 report("INVVPID SINGLE", vmx_get_test_stage() == 3); 1589 vmx_set_test_stage(4); 1590 vmcall(); 1591 report("INVVPID ALL", vmx_get_test_stage() == 5); 1592 } 1593 1594 static int vpid_exit_handler(void) 1595 { 1596 u64 guest_rip; 1597 ulong reason; 1598 u32 insn_len; 1599 1600 guest_rip = vmcs_read(GUEST_RIP); 1601 reason = vmcs_read(EXI_REASON) & 0xff; 1602 insn_len = vmcs_read(EXI_INST_LEN); 1603 1604 switch (reason) { 1605 case VMX_VMCALL: 1606 switch(vmx_get_test_stage()) { 1607 case 0: 1608 if (!invvpid_test(INVVPID_ADDR, 1)) 1609 vmx_inc_test_stage(); 1610 break; 1611 case 2: 1612 if (!invvpid_test(INVVPID_CONTEXT_GLOBAL, 1)) 1613 vmx_inc_test_stage(); 1614 break; 1615 case 4: 1616 if (!invvpid_test(INVVPID_ALL, 1)) 1617 vmx_inc_test_stage(); 1618 break; 1619 default: 1620 report("ERROR: unexpected stage, %d", false, 1621 vmx_get_test_stage()); 1622 print_vmexit_info(); 1623 return VMX_TEST_VMEXIT; 1624 } 1625 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1626 return VMX_TEST_RESUME; 1627 default: 1628 report("Unknown exit reason, %ld", false, reason); 1629 print_vmexit_info(); 1630 } 1631 return VMX_TEST_VMEXIT; 1632 } 1633 1634 #define TIMER_VECTOR 222 1635 1636 static volatile bool timer_fired; 1637 1638 static void timer_isr(isr_regs_t *regs) 1639 { 1640 timer_fired = true; 1641 apic_write(APIC_EOI, 0); 1642 } 1643 1644 static int interrupt_init(struct vmcs *vmcs) 1645 { 1646 msr_bmp_init(); 1647 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1648 handle_irq(TIMER_VECTOR, timer_isr); 1649 return VMX_TEST_START; 1650 } 1651 1652 static void interrupt_main(void) 1653 { 1654 long long start, loops; 1655 1656 vmx_set_test_stage(0); 1657 1658 apic_write(APIC_LVTT, TIMER_VECTOR); 1659 irq_enable(); 1660 1661 apic_write(APIC_TMICT, 1); 1662 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1663 asm volatile ("nop"); 1664 report("direct interrupt while running guest", timer_fired); 1665 1666 apic_write(APIC_TMICT, 0); 1667 irq_disable(); 1668 vmcall(); 1669 timer_fired = false; 1670 apic_write(APIC_TMICT, 1); 1671 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1672 asm volatile ("nop"); 1673 report("intercepted interrupt while running guest", timer_fired); 1674 1675 irq_enable(); 1676 apic_write(APIC_TMICT, 0); 1677 irq_disable(); 1678 vmcall(); 1679 timer_fired = false; 1680 start = rdtsc(); 1681 apic_write(APIC_TMICT, 1000000); 1682 1683 asm volatile ("sti; hlt"); 1684 1685 report("direct interrupt + hlt", 1686 rdtsc() - start > 1000000 && timer_fired); 1687 1688 apic_write(APIC_TMICT, 0); 1689 irq_disable(); 1690 vmcall(); 1691 timer_fired = false; 1692 start = rdtsc(); 1693 apic_write(APIC_TMICT, 1000000); 1694 1695 asm volatile ("sti; hlt"); 1696 1697 report("intercepted interrupt + hlt", 1698 rdtsc() - start > 10000 && timer_fired); 1699 1700 apic_write(APIC_TMICT, 0); 1701 irq_disable(); 1702 vmcall(); 1703 timer_fired = false; 1704 start = rdtsc(); 1705 apic_write(APIC_TMICT, 1000000); 1706 1707 irq_enable(); 1708 asm volatile ("nop"); 1709 vmcall(); 1710 1711 report("direct interrupt + activity state hlt", 1712 rdtsc() - start > 10000 && timer_fired); 1713 1714 apic_write(APIC_TMICT, 0); 1715 irq_disable(); 1716 vmcall(); 1717 timer_fired = false; 1718 start = rdtsc(); 1719 apic_write(APIC_TMICT, 1000000); 1720 1721 irq_enable(); 1722 asm volatile ("nop"); 1723 vmcall(); 1724 1725 report("intercepted interrupt + activity state hlt", 1726 rdtsc() - start > 10000 && timer_fired); 1727 1728 apic_write(APIC_TMICT, 0); 1729 irq_disable(); 1730 vmx_set_test_stage(7); 1731 vmcall(); 1732 timer_fired = false; 1733 apic_write(APIC_TMICT, 1); 1734 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1735 asm volatile ("nop"); 1736 report("running a guest with interrupt acknowledgement set", timer_fired); 1737 1738 apic_write(APIC_TMICT, 0); 1739 irq_enable(); 1740 timer_fired = false; 1741 vmcall(); 1742 report("Inject an event to a halted guest", timer_fired); 1743 } 1744 1745 static int interrupt_exit_handler(void) 1746 { 1747 u64 guest_rip = vmcs_read(GUEST_RIP); 1748 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1749 u32 insn_len = vmcs_read(EXI_INST_LEN); 1750 1751 switch (reason) { 1752 case VMX_VMCALL: 1753 switch (vmx_get_test_stage()) { 1754 case 0: 1755 case 2: 1756 case 5: 1757 vmcs_write(PIN_CONTROLS, 1758 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1759 break; 1760 case 7: 1761 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1762 vmcs_write(PIN_CONTROLS, 1763 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1764 break; 1765 case 1: 1766 case 3: 1767 vmcs_write(PIN_CONTROLS, 1768 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1769 break; 1770 case 4: 1771 case 6: 1772 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1773 break; 1774 1775 case 8: 1776 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1777 vmcs_write(ENT_INTR_INFO, 1778 TIMER_VECTOR | 1779 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1780 INTR_INFO_VALID_MASK); 1781 break; 1782 } 1783 vmx_inc_test_stage(); 1784 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1785 return VMX_TEST_RESUME; 1786 case VMX_EXTINT: 1787 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1788 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1789 handle_external_interrupt(vector); 1790 } else { 1791 irq_enable(); 1792 asm volatile ("nop"); 1793 irq_disable(); 1794 } 1795 if (vmx_get_test_stage() >= 2) 1796 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1797 return VMX_TEST_RESUME; 1798 default: 1799 report("Unknown exit reason, %ld", false, reason); 1800 print_vmexit_info(); 1801 } 1802 1803 return VMX_TEST_VMEXIT; 1804 } 1805 1806 static int dbgctls_init(struct vmcs *vmcs) 1807 { 1808 u64 dr7 = 0x402; 1809 u64 zero = 0; 1810 1811 msr_bmp_init(); 1812 asm volatile( 1813 "mov %0,%%dr0\n\t" 1814 "mov %0,%%dr1\n\t" 1815 "mov %0,%%dr2\n\t" 1816 "mov %1,%%dr7\n\t" 1817 : : "r" (zero), "r" (dr7)); 1818 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1819 vmcs_write(GUEST_DR7, 0x404); 1820 vmcs_write(GUEST_DEBUGCTL, 0x2); 1821 1822 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1823 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1824 1825 return VMX_TEST_START; 1826 } 1827 1828 static void dbgctls_main(void) 1829 { 1830 u64 dr7, debugctl; 1831 1832 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1833 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1834 /* Commented out: KVM does not support DEBUGCTL so far */ 1835 (void)debugctl; 1836 report("Load debug controls", dr7 == 0x404 /* && debugctl == 0x2 */); 1837 1838 dr7 = 0x408; 1839 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1840 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1841 1842 vmx_set_test_stage(0); 1843 vmcall(); 1844 report("Save debug controls", vmx_get_test_stage() == 1); 1845 1846 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1847 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1848 printf("\tDebug controls are always loaded/saved\n"); 1849 return; 1850 } 1851 vmx_set_test_stage(2); 1852 vmcall(); 1853 1854 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1855 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1856 /* Commented out: KVM does not support DEBUGCTL so far */ 1857 (void)debugctl; 1858 report("Guest=host debug controls", dr7 == 0x402 /* && debugctl == 0x1 */); 1859 1860 dr7 = 0x408; 1861 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1862 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1863 1864 vmx_set_test_stage(3); 1865 vmcall(); 1866 report("Don't save debug controls", vmx_get_test_stage() == 4); 1867 } 1868 1869 static int dbgctls_exit_handler(void) 1870 { 1871 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 1872 u32 insn_len = vmcs_read(EXI_INST_LEN); 1873 u64 guest_rip = vmcs_read(GUEST_RIP); 1874 u64 dr7, debugctl; 1875 1876 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1877 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1878 1879 switch (reason) { 1880 case VMX_VMCALL: 1881 switch (vmx_get_test_stage()) { 1882 case 0: 1883 if (dr7 == 0x400 && debugctl == 0 && 1884 vmcs_read(GUEST_DR7) == 0x408 /* && 1885 Commented out: KVM does not support DEBUGCTL so far 1886 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1887 vmx_inc_test_stage(); 1888 break; 1889 case 2: 1890 dr7 = 0x402; 1891 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1892 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1893 vmcs_write(GUEST_DR7, 0x404); 1894 vmcs_write(GUEST_DEBUGCTL, 0x2); 1895 1896 vmcs_write(ENT_CONTROLS, 1897 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1898 vmcs_write(EXI_CONTROLS, 1899 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1900 break; 1901 case 3: 1902 if (dr7 == 0x400 && debugctl == 0 && 1903 vmcs_read(GUEST_DR7) == 0x404 /* && 1904 Commented out: KVM does not support DEBUGCTL so far 1905 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1906 vmx_inc_test_stage(); 1907 break; 1908 } 1909 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1910 return VMX_TEST_RESUME; 1911 default: 1912 report("Unknown exit reason, %d", false, reason); 1913 print_vmexit_info(); 1914 } 1915 return VMX_TEST_VMEXIT; 1916 } 1917 1918 struct vmx_msr_entry { 1919 u32 index; 1920 u32 reserved; 1921 u64 value; 1922 } __attribute__((packed)); 1923 1924 #define MSR_MAGIC 0x31415926 1925 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1926 1927 static int msr_switch_init(struct vmcs *vmcs) 1928 { 1929 msr_bmp_init(); 1930 exit_msr_store = alloc_page(); 1931 exit_msr_load = alloc_page(); 1932 entry_msr_load = alloc_page(); 1933 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1934 entry_msr_load[0].value = MSR_MAGIC; 1935 1936 vmx_set_test_stage(1); 1937 vmcs_write(ENT_MSR_LD_CNT, 1); 1938 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1939 vmcs_write(EXI_MSR_ST_CNT, 1); 1940 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1941 vmcs_write(EXI_MSR_LD_CNT, 1); 1942 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1943 return VMX_TEST_START; 1944 } 1945 1946 static void msr_switch_main(void) 1947 { 1948 if (vmx_get_test_stage() == 1) { 1949 report("VM entry MSR load", 1950 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC); 1951 vmx_set_test_stage(2); 1952 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1953 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1954 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1955 exit_msr_load[0].value = MSR_MAGIC + 2; 1956 } 1957 vmcall(); 1958 } 1959 1960 static int msr_switch_exit_handler(void) 1961 { 1962 ulong reason; 1963 1964 reason = vmcs_read(EXI_REASON); 1965 if (reason == VMX_VMCALL && vmx_get_test_stage() == 2) { 1966 report("VM exit MSR store", 1967 exit_msr_store[0].value == MSR_MAGIC + 1); 1968 report("VM exit MSR load", 1969 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2); 1970 vmx_set_test_stage(3); 1971 entry_msr_load[0].index = MSR_FS_BASE; 1972 return VMX_TEST_RESUME; 1973 } 1974 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1975 __func__, vmx_get_test_stage(), reason); 1976 return VMX_TEST_EXIT; 1977 } 1978 1979 static int msr_switch_entry_failure(struct vmentry_failure *failure) 1980 { 1981 ulong reason; 1982 1983 if (failure->early) { 1984 printf("ERROR %s: early exit\n", __func__); 1985 return VMX_TEST_EXIT; 1986 } 1987 1988 reason = vmcs_read(EXI_REASON); 1989 if (reason == (VMX_ENTRY_FAILURE | VMX_FAIL_MSR) && 1990 vmx_get_test_stage() == 3) { 1991 report("VM entry MSR load: try to load FS_BASE", 1992 vmcs_read(EXI_QUALIFICATION) == 1); 1993 return VMX_TEST_VMEXIT; 1994 } 1995 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1996 __func__, vmx_get_test_stage(), reason); 1997 return VMX_TEST_EXIT; 1998 } 1999 2000 static int vmmcall_init(struct vmcs *vmcs) 2001 { 2002 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 2003 return VMX_TEST_START; 2004 } 2005 2006 static void vmmcall_main(void) 2007 { 2008 asm volatile( 2009 "mov $0xABCD, %%rax\n\t" 2010 "vmmcall\n\t" 2011 ::: "rax"); 2012 2013 report("VMMCALL", 0); 2014 } 2015 2016 static int vmmcall_exit_handler(void) 2017 { 2018 ulong reason; 2019 2020 reason = vmcs_read(EXI_REASON); 2021 switch (reason) { 2022 case VMX_VMCALL: 2023 printf("here\n"); 2024 report("VMMCALL triggers #UD", 0); 2025 break; 2026 case VMX_EXC_NMI: 2027 report("VMMCALL triggers #UD", 2028 (vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR); 2029 break; 2030 default: 2031 report("Unknown exit reason, %ld", false, reason); 2032 print_vmexit_info(); 2033 } 2034 2035 return VMX_TEST_VMEXIT; 2036 } 2037 2038 static int disable_rdtscp_init(struct vmcs *vmcs) 2039 { 2040 u32 ctrl_cpu1; 2041 2042 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 2043 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 2044 ctrl_cpu1 &= ~CPU_RDTSCP; 2045 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 2046 } 2047 2048 return VMX_TEST_START; 2049 } 2050 2051 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 2052 { 2053 switch (vmx_get_test_stage()) { 2054 case 0: 2055 report("RDTSCP triggers #UD", true); 2056 vmx_inc_test_stage(); 2057 regs->rip += 3; 2058 break; 2059 case 2: 2060 report("RDPID triggers #UD", true); 2061 vmx_inc_test_stage(); 2062 regs->rip += 4; 2063 break; 2064 } 2065 return; 2066 2067 } 2068 2069 static void disable_rdtscp_main(void) 2070 { 2071 /* Test that #UD is properly injected in L2. */ 2072 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2073 2074 vmx_set_test_stage(0); 2075 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2076 vmcall(); 2077 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2078 2079 handle_exception(UD_VECTOR, 0); 2080 vmcall(); 2081 } 2082 2083 static int disable_rdtscp_exit_handler(void) 2084 { 2085 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 2086 2087 switch (reason) { 2088 case VMX_VMCALL: 2089 switch (vmx_get_test_stage()) { 2090 case 0: 2091 report("RDTSCP triggers #UD", false); 2092 vmx_inc_test_stage(); 2093 /* fallthrough */ 2094 case 1: 2095 vmx_inc_test_stage(); 2096 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2097 return VMX_TEST_RESUME; 2098 case 2: 2099 report("RDPID triggers #UD", false); 2100 break; 2101 } 2102 break; 2103 2104 default: 2105 report("Unknown exit reason, %d", false, reason); 2106 print_vmexit_info(); 2107 } 2108 return VMX_TEST_VMEXIT; 2109 } 2110 2111 static int int3_init(struct vmcs *vmcs) 2112 { 2113 vmcs_write(EXC_BITMAP, ~0u); 2114 return VMX_TEST_START; 2115 } 2116 2117 static void int3_guest_main(void) 2118 { 2119 asm volatile ("int3"); 2120 } 2121 2122 static int int3_exit_handler(void) 2123 { 2124 u32 reason = vmcs_read(EXI_REASON); 2125 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2126 2127 report("L1 intercepts #BP", reason == VMX_EXC_NMI && 2128 (intr_info & INTR_INFO_VALID_MASK) && 2129 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2130 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2131 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2132 2133 return VMX_TEST_VMEXIT; 2134 } 2135 2136 static int into_init(struct vmcs *vmcs) 2137 { 2138 vmcs_write(EXC_BITMAP, ~0u); 2139 return VMX_TEST_START; 2140 } 2141 2142 static void into_guest_main(void) 2143 { 2144 struct far_pointer32 fp = { 2145 .offset = (uintptr_t)&&into, 2146 .selector = KERNEL_CS32, 2147 }; 2148 register uintptr_t rsp asm("rsp"); 2149 2150 if (fp.offset != (uintptr_t)&&into) { 2151 printf("Code address too high.\n"); 2152 return; 2153 } 2154 if ((u32)rsp != rsp) { 2155 printf("Stack address too high.\n"); 2156 return; 2157 } 2158 2159 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2160 return; 2161 into: 2162 asm volatile (".code32;" 2163 "movl $0x7fffffff, %eax;" 2164 "addl %eax, %eax;" 2165 "into;" 2166 "lret;" 2167 ".code64"); 2168 __builtin_unreachable(); 2169 } 2170 2171 static int into_exit_handler(void) 2172 { 2173 u32 reason = vmcs_read(EXI_REASON); 2174 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2175 2176 report("L1 intercepts #OF", reason == VMX_EXC_NMI && 2177 (intr_info & INTR_INFO_VALID_MASK) && 2178 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2179 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2180 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2181 2182 return VMX_TEST_VMEXIT; 2183 } 2184 2185 static void exit_monitor_from_l2_main(void) 2186 { 2187 printf("Calling exit(0) from l2...\n"); 2188 exit(0); 2189 } 2190 2191 static int exit_monitor_from_l2_handler(void) 2192 { 2193 report("The guest should have killed the VMM", false); 2194 return VMX_TEST_EXIT; 2195 } 2196 2197 static void assert_exit_reason(u64 expected) 2198 { 2199 u64 actual = vmcs_read(EXI_REASON); 2200 2201 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2202 exit_reason_description(expected), 2203 exit_reason_description(actual)); 2204 } 2205 2206 static void skip_exit_insn(void) 2207 { 2208 u64 guest_rip = vmcs_read(GUEST_RIP); 2209 u32 insn_len = vmcs_read(EXI_INST_LEN); 2210 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2211 } 2212 2213 static void skip_exit_vmcall(void) 2214 { 2215 assert_exit_reason(VMX_VMCALL); 2216 skip_exit_insn(); 2217 } 2218 2219 static void v2_null_test_guest(void) 2220 { 2221 } 2222 2223 static void v2_null_test(void) 2224 { 2225 test_set_guest(v2_null_test_guest); 2226 enter_guest(); 2227 report(__func__, 1); 2228 } 2229 2230 static void v2_multiple_entries_test_guest(void) 2231 { 2232 vmx_set_test_stage(1); 2233 vmcall(); 2234 vmx_set_test_stage(2); 2235 } 2236 2237 static void v2_multiple_entries_test(void) 2238 { 2239 test_set_guest(v2_multiple_entries_test_guest); 2240 enter_guest(); 2241 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2242 skip_exit_vmcall(); 2243 enter_guest(); 2244 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2245 report(__func__, 1); 2246 } 2247 2248 static int fixture_test_data = 1; 2249 2250 static void fixture_test_teardown(void *data) 2251 { 2252 *((int *) data) = 1; 2253 } 2254 2255 static void fixture_test_guest(void) 2256 { 2257 fixture_test_data++; 2258 } 2259 2260 2261 static void fixture_test_setup(void) 2262 { 2263 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2264 "fixture_test_teardown didn't run?!"); 2265 fixture_test_data = 2; 2266 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2267 test_set_guest(fixture_test_guest); 2268 } 2269 2270 static void fixture_test_case1(void) 2271 { 2272 fixture_test_setup(); 2273 TEST_ASSERT_EQ(2, fixture_test_data); 2274 enter_guest(); 2275 TEST_ASSERT_EQ(3, fixture_test_data); 2276 report(__func__, 1); 2277 } 2278 2279 static void fixture_test_case2(void) 2280 { 2281 fixture_test_setup(); 2282 TEST_ASSERT_EQ(2, fixture_test_data); 2283 enter_guest(); 2284 TEST_ASSERT_EQ(3, fixture_test_data); 2285 report(__func__, 1); 2286 } 2287 2288 enum ept_access_op { 2289 OP_READ, 2290 OP_WRITE, 2291 OP_EXEC, 2292 OP_FLUSH_TLB, 2293 OP_EXIT, 2294 }; 2295 2296 static struct ept_access_test_data { 2297 unsigned long gpa; 2298 unsigned long *gva; 2299 unsigned long hpa; 2300 unsigned long *hva; 2301 enum ept_access_op op; 2302 } ept_access_test_data; 2303 2304 extern unsigned char ret42_start; 2305 extern unsigned char ret42_end; 2306 2307 /* Returns 42. */ 2308 asm( 2309 ".align 64\n" 2310 "ret42_start:\n" 2311 "mov $42, %eax\n" 2312 "ret\n" 2313 "ret42_end:\n" 2314 ); 2315 2316 static void 2317 diagnose_ept_violation_qual(u64 expected, u64 actual) 2318 { 2319 2320 #define DIAGNOSE(flag) \ 2321 do { \ 2322 if ((expected & flag) != (actual & flag)) \ 2323 printf(#flag " %sexpected\n", \ 2324 (expected & flag) ? "" : "un"); \ 2325 } while (0) 2326 2327 DIAGNOSE(EPT_VLT_RD); 2328 DIAGNOSE(EPT_VLT_WR); 2329 DIAGNOSE(EPT_VLT_FETCH); 2330 DIAGNOSE(EPT_VLT_PERM_RD); 2331 DIAGNOSE(EPT_VLT_PERM_WR); 2332 DIAGNOSE(EPT_VLT_PERM_EX); 2333 DIAGNOSE(EPT_VLT_LADDR_VLD); 2334 DIAGNOSE(EPT_VLT_PADDR); 2335 2336 #undef DIAGNOSE 2337 } 2338 2339 static void do_ept_access_op(enum ept_access_op op) 2340 { 2341 ept_access_test_data.op = op; 2342 enter_guest(); 2343 } 2344 2345 /* 2346 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2347 * needed by tests that modify guest PTEs. 2348 */ 2349 static void ept_access_test_guest_flush_tlb(void) 2350 { 2351 do_ept_access_op(OP_FLUSH_TLB); 2352 skip_exit_vmcall(); 2353 } 2354 2355 /* 2356 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2357 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2358 * a huge page. 2359 */ 2360 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2361 unsigned long clear, unsigned long set) 2362 { 2363 struct ept_access_test_data *data = &ept_access_test_data; 2364 unsigned long orig_pte; 2365 unsigned long pte; 2366 2367 /* Screw with the mapping at the requested level. */ 2368 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2369 pte = orig_pte; 2370 if (mkhuge) 2371 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2372 else 2373 pte = orig_pte; 2374 pte = (pte & ~clear) | set; 2375 set_ept_pte(pml4, gpa, level, pte); 2376 ept_sync(INVEPT_SINGLE, eptp); 2377 2378 return orig_pte; 2379 } 2380 2381 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2382 { 2383 set_ept_pte(pml4, gpa, level, orig_pte); 2384 ept_sync(INVEPT_SINGLE, eptp); 2385 } 2386 2387 static void do_ept_violation(bool leaf, enum ept_access_op op, 2388 u64 expected_qual, u64 expected_paddr) 2389 { 2390 u64 qual; 2391 2392 /* Try the access and observe the violation. */ 2393 do_ept_access_op(op); 2394 2395 assert_exit_reason(VMX_EPT_VIOLATION); 2396 2397 qual = vmcs_read(EXI_QUALIFICATION); 2398 2399 /* Mask undefined bits (which may later be defined in certain cases). */ 2400 qual &= ~(EPT_VLT_GUEST_USER | EPT_VLT_GUEST_RW | EPT_VLT_GUEST_EX | 2401 EPT_VLT_PERM_USER_EX); 2402 2403 diagnose_ept_violation_qual(expected_qual, qual); 2404 TEST_EXPECT_EQ(expected_qual, qual); 2405 2406 #if 0 2407 /* Disable for now otherwise every test will fail */ 2408 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2409 (unsigned long) ( 2410 op == OP_EXEC ? data->gva + 1 : data->gva)); 2411 #endif 2412 /* 2413 * TODO: tests that probe expected_paddr in pages other than the one at 2414 * the beginning of the 1g region. 2415 */ 2416 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2417 } 2418 2419 static void 2420 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2421 unsigned long set, enum ept_access_op op, 2422 u64 expected_qual) 2423 { 2424 struct ept_access_test_data *data = &ept_access_test_data; 2425 unsigned long orig_pte; 2426 2427 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2428 2429 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2430 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2431 data->gpa); 2432 2433 /* Fix the violation and resume the op loop. */ 2434 ept_untwiddle(data->gpa, level, orig_pte); 2435 enter_guest(); 2436 skip_exit_vmcall(); 2437 } 2438 2439 static void 2440 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2441 enum ept_access_op op, u64 expected_qual) 2442 { 2443 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2444 expected_qual); 2445 if (ept_huge_pages_supported(level)) 2446 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2447 expected_qual); 2448 } 2449 2450 static void ept_violation(unsigned long clear, unsigned long set, 2451 enum ept_access_op op, u64 expected_qual) 2452 { 2453 ept_violation_at_level(1, clear, set, op, expected_qual); 2454 ept_violation_at_level(2, clear, set, op, expected_qual); 2455 ept_violation_at_level(3, clear, set, op, expected_qual); 2456 ept_violation_at_level(4, clear, set, op, expected_qual); 2457 } 2458 2459 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2460 u64 expected_qual) 2461 { 2462 ept_violation(EPT_PRESENT, access, op, 2463 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2464 } 2465 2466 /* 2467 * For translations that don't involve a GVA, that is physical address (paddr) 2468 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2469 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2470 * translations don't involve GVAs, such as when the hardware does the guest 2471 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2472 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2473 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2474 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2475 * 2476 * Note that paddr violations can also be triggered by loading PAE page tables 2477 * with wonky addresses. We don't test that yet. 2478 * 2479 * This function modifies the EPT entry that maps the GPA that the guest page 2480 * table entry mapping ept_access_test_data.gva resides on. 2481 * 2482 * @ept_access EPT permissions to set. Other permissions are cleared. 2483 * 2484 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2485 * 2486 * @op Guest operation to perform with 2487 * ept_access_test_data.gva. 2488 * 2489 * @expect_violation 2490 * Is a violation expected during the paddr access? 2491 * 2492 * @expected_qual Expected qualification for the EPT violation. 2493 * EPT_VLT_PADDR should be clear. 2494 */ 2495 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2496 enum ept_access_op op, bool expect_violation, 2497 u64 expected_qual) 2498 { 2499 struct ept_access_test_data *data = &ept_access_test_data; 2500 unsigned long *ptep; 2501 unsigned long gpa; 2502 unsigned long orig_epte; 2503 2504 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2505 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2506 TEST_ASSERT(ptep); 2507 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2508 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2509 ept_access_test_guest_flush_tlb(); 2510 2511 /* 2512 * Now modify the access bits on the EPT entry for the GPA that the 2513 * guest PTE resides on. Note that by modifying a single EPT entry, 2514 * we're potentially affecting 512 guest PTEs. However, we've carefully 2515 * constructed our test such that those other 511 PTEs aren't used by 2516 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2517 * PTE we're modifying is at the beginning of a 4K page and the 2518 * following 511 entires are also under our control (and not touched by 2519 * the guest). 2520 */ 2521 gpa = virt_to_phys(ptep); 2522 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2523 /* 2524 * Make sure the guest page table page is mapped with a 4K EPT entry, 2525 * otherwise our level=1 twiddling below will fail. We use the 2526 * identity map (gpa = gpa) since page tables are shared with the host. 2527 */ 2528 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2529 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2530 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2531 2532 if (expect_violation) { 2533 do_ept_violation(/*leaf=*/true, op, 2534 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2535 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2536 do_ept_access_op(op); 2537 } else { 2538 do_ept_access_op(op); 2539 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2540 } 2541 2542 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2543 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2544 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2545 2546 skip_exit_vmcall(); 2547 } 2548 2549 static void ept_access_allowed_paddr(unsigned long ept_access, 2550 unsigned long pte_ad, 2551 enum ept_access_op op) 2552 { 2553 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2554 /*expected_qual=*/-1); 2555 } 2556 2557 static void ept_access_violation_paddr(unsigned long ept_access, 2558 unsigned long pte_ad, 2559 enum ept_access_op op, 2560 u64 expected_qual) 2561 { 2562 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2563 expected_qual); 2564 } 2565 2566 2567 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2568 unsigned long clear, 2569 unsigned long set, 2570 enum ept_access_op op) 2571 { 2572 struct ept_access_test_data *data = &ept_access_test_data; 2573 unsigned long orig_pte; 2574 2575 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2576 2577 /* No violation. Should proceed to vmcall. */ 2578 do_ept_access_op(op); 2579 skip_exit_vmcall(); 2580 2581 ept_untwiddle(data->gpa, level, orig_pte); 2582 } 2583 2584 static void ept_allowed_at_level(int level, unsigned long clear, 2585 unsigned long set, enum ept_access_op op) 2586 { 2587 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2588 if (ept_huge_pages_supported(level)) 2589 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2590 } 2591 2592 static void ept_allowed(unsigned long clear, unsigned long set, 2593 enum ept_access_op op) 2594 { 2595 ept_allowed_at_level(1, clear, set, op); 2596 ept_allowed_at_level(2, clear, set, op); 2597 ept_allowed_at_level(3, clear, set, op); 2598 ept_allowed_at_level(4, clear, set, op); 2599 } 2600 2601 static void ept_ignored_bit(int bit) 2602 { 2603 /* Set the bit. */ 2604 ept_allowed(0, 1ul << bit, OP_READ); 2605 ept_allowed(0, 1ul << bit, OP_WRITE); 2606 ept_allowed(0, 1ul << bit, OP_EXEC); 2607 2608 /* Clear the bit. */ 2609 ept_allowed(1ul << bit, 0, OP_READ); 2610 ept_allowed(1ul << bit, 0, OP_WRITE); 2611 ept_allowed(1ul << bit, 0, OP_EXEC); 2612 } 2613 2614 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2615 { 2616 ept_allowed(EPT_PRESENT, access, op); 2617 } 2618 2619 2620 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2621 unsigned long clear, 2622 unsigned long set, 2623 enum ept_access_op op) 2624 { 2625 struct ept_access_test_data *data = &ept_access_test_data; 2626 unsigned long orig_pte; 2627 2628 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2629 2630 do_ept_access_op(op); 2631 assert_exit_reason(VMX_EPT_MISCONFIG); 2632 2633 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2634 #if 0 2635 /* broken: */ 2636 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2637 #endif 2638 #if 0 2639 /* 2640 * broken: 2641 * According to description of exit qual for EPT violation, 2642 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2643 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2644 * to be set for msiconfig. 2645 */ 2646 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2647 (unsigned long) ( 2648 op == OP_EXEC ? data->gva + 1 : data->gva)); 2649 #endif 2650 2651 /* Fix the violation and resume the op loop. */ 2652 ept_untwiddle(data->gpa, level, orig_pte); 2653 enter_guest(); 2654 skip_exit_vmcall(); 2655 } 2656 2657 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2658 unsigned long clear, 2659 unsigned long set) 2660 { 2661 /* The op shouldn't matter (read, write, exec), so try them all! */ 2662 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2663 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2664 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2665 } 2666 2667 static void ept_misconfig_at_level(int level, unsigned long clear, 2668 unsigned long set) 2669 { 2670 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2671 if (ept_huge_pages_supported(level)) 2672 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2673 } 2674 2675 static void ept_misconfig(unsigned long clear, unsigned long set) 2676 { 2677 ept_misconfig_at_level(1, clear, set); 2678 ept_misconfig_at_level(2, clear, set); 2679 ept_misconfig_at_level(3, clear, set); 2680 ept_misconfig_at_level(4, clear, set); 2681 } 2682 2683 static void ept_access_misconfig(unsigned long access) 2684 { 2685 ept_misconfig(EPT_PRESENT, access); 2686 } 2687 2688 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2689 { 2690 /* Setting the bit causes a misconfig. */ 2691 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2692 2693 /* Making the entry non-present turns reserved bits into ignored. */ 2694 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2695 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2696 } 2697 2698 static void ept_reserved_bit_at_level_huge(int level, int bit) 2699 { 2700 /* Setting the bit causes a misconfig. */ 2701 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2702 2703 /* Making the entry non-present turns reserved bits into ignored. */ 2704 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2705 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2706 } 2707 2708 static void ept_reserved_bit_at_level(int level, int bit) 2709 { 2710 /* Setting the bit causes a misconfig. */ 2711 ept_misconfig_at_level(level, 0, 1ul << bit); 2712 2713 /* Making the entry non-present turns reserved bits into ignored. */ 2714 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2715 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2716 } 2717 2718 static void ept_reserved_bit(int bit) 2719 { 2720 ept_reserved_bit_at_level(1, bit); 2721 ept_reserved_bit_at_level(2, bit); 2722 ept_reserved_bit_at_level(3, bit); 2723 ept_reserved_bit_at_level(4, bit); 2724 } 2725 2726 #define PAGE_2M_ORDER 9 2727 #define PAGE_1G_ORDER 18 2728 2729 static void *get_1g_page(void) 2730 { 2731 static void *alloc; 2732 2733 if (!alloc) 2734 alloc = alloc_pages(PAGE_1G_ORDER); 2735 return alloc; 2736 } 2737 2738 static void ept_access_test_teardown(void *unused) 2739 { 2740 /* Exit the guest cleanly. */ 2741 do_ept_access_op(OP_EXIT); 2742 } 2743 2744 static void ept_access_test_guest(void) 2745 { 2746 struct ept_access_test_data *data = &ept_access_test_data; 2747 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2748 2749 while (true) { 2750 switch (data->op) { 2751 case OP_READ: 2752 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2753 break; 2754 case OP_WRITE: 2755 *data->gva = MAGIC_VAL_2; 2756 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2757 *data->gva = MAGIC_VAL_1; 2758 break; 2759 case OP_EXEC: 2760 TEST_ASSERT_EQ(42, code()); 2761 break; 2762 case OP_FLUSH_TLB: 2763 write_cr3(read_cr3()); 2764 break; 2765 case OP_EXIT: 2766 return; 2767 default: 2768 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2769 } 2770 vmcall(); 2771 } 2772 } 2773 2774 static void ept_access_test_setup(void) 2775 { 2776 struct ept_access_test_data *data = &ept_access_test_data; 2777 unsigned long npages = 1ul << PAGE_1G_ORDER; 2778 unsigned long size = npages * PAGE_SIZE; 2779 unsigned long *page_table = current_page_table(); 2780 unsigned long pte; 2781 2782 if (setup_ept(false)) 2783 test_skip("EPT not supported"); 2784 2785 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2786 if (cpuid_maxphyaddr() < 40) 2787 test_skip("Test needs MAXPHYADDR >= 40"); 2788 2789 test_set_guest(ept_access_test_guest); 2790 test_add_teardown(ept_access_test_teardown, NULL); 2791 2792 data->hva = get_1g_page(); 2793 TEST_ASSERT(data->hva); 2794 data->hpa = virt_to_phys(data->hva); 2795 2796 data->gpa = 1ul << 39; 2797 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2798 size); 2799 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2800 install_pages(page_table, data->gpa, size, data->gva); 2801 2802 /* 2803 * Make sure nothing's mapped here so the tests that screw with the 2804 * pml4 entry don't inadvertently break something. 2805 */ 2806 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2807 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2808 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2809 2810 data->hva[0] = MAGIC_VAL_1; 2811 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2812 } 2813 2814 static void ept_access_test_not_present(void) 2815 { 2816 ept_access_test_setup(); 2817 /* --- */ 2818 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2819 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2820 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2821 } 2822 2823 static void ept_access_test_read_only(void) 2824 { 2825 ept_access_test_setup(); 2826 2827 /* r-- */ 2828 ept_access_allowed(EPT_RA, OP_READ); 2829 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2830 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2831 } 2832 2833 static void ept_access_test_write_only(void) 2834 { 2835 ept_access_test_setup(); 2836 /* -w- */ 2837 ept_access_misconfig(EPT_WA); 2838 } 2839 2840 static void ept_access_test_read_write(void) 2841 { 2842 ept_access_test_setup(); 2843 /* rw- */ 2844 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2845 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2846 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2847 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2848 } 2849 2850 2851 static void ept_access_test_execute_only(void) 2852 { 2853 ept_access_test_setup(); 2854 /* --x */ 2855 if (ept_execute_only_supported()) { 2856 ept_access_violation(EPT_EA, OP_READ, 2857 EPT_VLT_RD | EPT_VLT_PERM_EX); 2858 ept_access_violation(EPT_EA, OP_WRITE, 2859 EPT_VLT_WR | EPT_VLT_PERM_EX); 2860 ept_access_allowed(EPT_EA, OP_EXEC); 2861 } else { 2862 ept_access_misconfig(EPT_EA); 2863 } 2864 } 2865 2866 static void ept_access_test_read_execute(void) 2867 { 2868 ept_access_test_setup(); 2869 /* r-x */ 2870 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2871 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2872 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2873 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2874 } 2875 2876 static void ept_access_test_write_execute(void) 2877 { 2878 ept_access_test_setup(); 2879 /* -wx */ 2880 ept_access_misconfig(EPT_WA | EPT_EA); 2881 } 2882 2883 static void ept_access_test_read_write_execute(void) 2884 { 2885 ept_access_test_setup(); 2886 /* rwx */ 2887 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2888 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2889 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2890 } 2891 2892 static void ept_access_test_reserved_bits(void) 2893 { 2894 int i; 2895 int maxphyaddr; 2896 2897 ept_access_test_setup(); 2898 2899 /* Reserved bits above maxphyaddr. */ 2900 maxphyaddr = cpuid_maxphyaddr(); 2901 for (i = maxphyaddr; i <= 51; i++) { 2902 report_prefix_pushf("reserved_bit=%d", i); 2903 ept_reserved_bit(i); 2904 report_prefix_pop(); 2905 } 2906 2907 /* Level-specific reserved bits. */ 2908 ept_reserved_bit_at_level_nohuge(2, 3); 2909 ept_reserved_bit_at_level_nohuge(2, 4); 2910 ept_reserved_bit_at_level_nohuge(2, 5); 2911 ept_reserved_bit_at_level_nohuge(2, 6); 2912 /* 2M alignment. */ 2913 for (i = 12; i < 20; i++) { 2914 report_prefix_pushf("reserved_bit=%d", i); 2915 ept_reserved_bit_at_level_huge(2, i); 2916 report_prefix_pop(); 2917 } 2918 ept_reserved_bit_at_level_nohuge(3, 3); 2919 ept_reserved_bit_at_level_nohuge(3, 4); 2920 ept_reserved_bit_at_level_nohuge(3, 5); 2921 ept_reserved_bit_at_level_nohuge(3, 6); 2922 /* 1G alignment. */ 2923 for (i = 12; i < 29; i++) { 2924 report_prefix_pushf("reserved_bit=%d", i); 2925 ept_reserved_bit_at_level_huge(3, i); 2926 report_prefix_pop(); 2927 } 2928 ept_reserved_bit_at_level(4, 3); 2929 ept_reserved_bit_at_level(4, 4); 2930 ept_reserved_bit_at_level(4, 5); 2931 ept_reserved_bit_at_level(4, 6); 2932 ept_reserved_bit_at_level(4, 7); 2933 } 2934 2935 static void ept_access_test_ignored_bits(void) 2936 { 2937 ept_access_test_setup(); 2938 /* 2939 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2940 * far as translation is concerned even if AD bits are enabled in the 2941 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2942 * control is 0. 2943 */ 2944 ept_ignored_bit(8); 2945 ept_ignored_bit(9); 2946 ept_ignored_bit(10); 2947 ept_ignored_bit(11); 2948 ept_ignored_bit(52); 2949 ept_ignored_bit(53); 2950 ept_ignored_bit(54); 2951 ept_ignored_bit(55); 2952 ept_ignored_bit(56); 2953 ept_ignored_bit(57); 2954 ept_ignored_bit(58); 2955 ept_ignored_bit(59); 2956 ept_ignored_bit(60); 2957 ept_ignored_bit(61); 2958 ept_ignored_bit(62); 2959 ept_ignored_bit(63); 2960 } 2961 2962 static void ept_access_test_paddr_not_present_ad_disabled(void) 2963 { 2964 ept_access_test_setup(); 2965 ept_disable_ad_bits(); 2966 2967 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 2968 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 2969 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 2970 } 2971 2972 static void ept_access_test_paddr_not_present_ad_enabled(void) 2973 { 2974 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 2975 2976 ept_access_test_setup(); 2977 ept_enable_ad_bits_or_skip_test(); 2978 2979 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 2980 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 2981 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 2982 } 2983 2984 static void ept_access_test_paddr_read_only_ad_disabled(void) 2985 { 2986 /* 2987 * When EPT AD bits are disabled, all accesses to guest paging 2988 * structures are reported separately as a read and (after 2989 * translation of the GPA to host physical address) a read+write 2990 * if the A/D bits have to be set. 2991 */ 2992 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2993 2994 ept_access_test_setup(); 2995 ept_disable_ad_bits(); 2996 2997 /* Can't update A bit, so all accesses fail. */ 2998 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2999 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3000 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3001 /* AD bits disabled, so only writes try to update the D bit. */ 3002 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 3003 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3004 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 3005 /* Both A and D already set, so read-only is OK. */ 3006 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 3007 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 3008 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 3009 } 3010 3011 static void ept_access_test_paddr_read_only_ad_enabled(void) 3012 { 3013 /* 3014 * When EPT AD bits are enabled, all accesses to guest paging 3015 * structures are considered writes as far as EPT translation 3016 * is concerned. 3017 */ 3018 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3019 3020 ept_access_test_setup(); 3021 ept_enable_ad_bits_or_skip_test(); 3022 3023 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3024 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3025 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3026 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 3027 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3028 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 3029 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 3030 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 3031 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 3032 } 3033 3034 static void ept_access_test_paddr_read_write(void) 3035 { 3036 ept_access_test_setup(); 3037 /* Read-write access to paging structure. */ 3038 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 3039 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 3040 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 3041 } 3042 3043 static void ept_access_test_paddr_read_write_execute(void) 3044 { 3045 ept_access_test_setup(); 3046 /* RWX access to paging structure. */ 3047 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 3048 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 3049 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 3050 } 3051 3052 static void ept_access_test_paddr_read_execute_ad_disabled(void) 3053 { 3054 /* 3055 * When EPT AD bits are disabled, all accesses to guest paging 3056 * structures are reported separately as a read and (after 3057 * translation of the GPA to host physical address) a read+write 3058 * if the A/D bits have to be set. 3059 */ 3060 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3061 3062 ept_access_test_setup(); 3063 ept_disable_ad_bits(); 3064 3065 /* Can't update A bit, so all accesses fail. */ 3066 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3067 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3068 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3069 /* AD bits disabled, so only writes try to update the D bit. */ 3070 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3071 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3072 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3073 /* Both A and D already set, so read-only is OK. */ 3074 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3075 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3076 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3077 } 3078 3079 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3080 { 3081 /* 3082 * When EPT AD bits are enabled, all accesses to guest paging 3083 * structures are considered writes as far as EPT translation 3084 * is concerned. 3085 */ 3086 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3087 3088 ept_access_test_setup(); 3089 ept_enable_ad_bits_or_skip_test(); 3090 3091 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3092 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3093 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3094 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3095 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3096 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3097 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3098 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3099 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3100 } 3101 3102 static void ept_access_test_paddr_not_present_page_fault(void) 3103 { 3104 ept_access_test_setup(); 3105 /* 3106 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3107 * page is read-only in EPT but GVA is also mapped read only in PT. 3108 * Thus guest page fault before host takes EPT violation for trying to 3109 * update A bit. 3110 */ 3111 } 3112 3113 static void ept_access_test_force_2m_page(void) 3114 { 3115 ept_access_test_setup(); 3116 3117 TEST_ASSERT_EQ(ept_2m_supported(), true); 3118 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3119 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3120 EPT_VLT_WR | EPT_VLT_PERM_RD | 3121 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3122 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3123 } 3124 3125 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3126 { 3127 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3128 3129 TEST_ASSERT(msr & VPID_CAP_INVVPID); 3130 3131 if (type < INVVPID_ADDR || type > INVVPID_CONTEXT_LOCAL) 3132 return false; 3133 3134 if (!(msr & (1ull << (type + VPID_CAP_INVVPID_TYPES_SHIFT)))) 3135 return false; 3136 3137 if (vpid >> 16) 3138 return false; 3139 3140 if (type != INVVPID_ALL && !vpid) 3141 return false; 3142 3143 if (type == INVVPID_ADDR && !is_canonical(gla)) 3144 return false; 3145 3146 return true; 3147 } 3148 3149 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3150 { 3151 int rc; 3152 bool valid = invvpid_valid(type, vpid, gla); 3153 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3154 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3155 /* 3156 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3157 * that we can tell if it is updated by INVVPID. 3158 */ 3159 vmcs_read(~0); 3160 rc = invvpid(type, vpid, gla); 3161 report("INVVPID type %ld VPID %lx GLA %lx %s", 3162 !rc == valid, type, vpid, gla, 3163 valid ? "passes" : "fails"); 3164 report("After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3165 vmcs_read(VMX_INST_ERROR) == expected, 3166 rc ? "failed" : "successful", 3167 expected, vmcs_read(VMX_INST_ERROR)); 3168 } 3169 3170 static void ds_invvpid(void *data) 3171 { 3172 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3173 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3174 3175 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3176 asm volatile("invvpid %0, %1" 3177 : 3178 : "m"(*(struct invvpid_operand *)data), 3179 "r"(type)); 3180 } 3181 3182 /* 3183 * The SS override is ignored in 64-bit mode, so we use an addressing 3184 * mode with %rsp as the base register to generate an implicit SS 3185 * reference. 3186 */ 3187 static void ss_invvpid(void *data) 3188 { 3189 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3190 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3191 3192 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3193 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3194 : "+r"(data) 3195 : "r"(type)); 3196 } 3197 3198 static void invvpid_test_gp(void) 3199 { 3200 bool fault; 3201 3202 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3203 (void *)NONCANONICAL); 3204 report("INVVPID with non-canonical DS operand raises #GP", fault); 3205 } 3206 3207 static void invvpid_test_ss(void) 3208 { 3209 bool fault; 3210 3211 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3212 (void *)NONCANONICAL); 3213 report("INVVPID with non-canonical SS operand raises #SS", fault); 3214 } 3215 3216 static void invvpid_test_pf(void) 3217 { 3218 void *vpage = alloc_vpage(); 3219 bool fault; 3220 3221 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3222 report("INVVPID with unmapped operand raises #PF", fault); 3223 } 3224 3225 static void try_compat_invvpid(void *unused) 3226 { 3227 struct far_pointer32 fp = { 3228 .offset = (uintptr_t)&&invvpid, 3229 .selector = KERNEL_CS32, 3230 }; 3231 register uintptr_t rsp asm("rsp"); 3232 3233 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3234 "Code address too high."); 3235 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3236 3237 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3238 return; 3239 invvpid: 3240 asm volatile (".code32;" 3241 "invvpid (%eax), %eax;" 3242 "lret;" 3243 ".code64"); 3244 __builtin_unreachable(); 3245 } 3246 3247 static void invvpid_test_compatibility_mode(void) 3248 { 3249 bool fault; 3250 3251 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3252 report("Compatibility mode INVVPID raises #UD", fault); 3253 } 3254 3255 static void invvpid_test_not_in_vmx_operation(void) 3256 { 3257 bool fault; 3258 3259 TEST_ASSERT(!vmx_off()); 3260 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3261 report("INVVPID outside of VMX operation raises #UD", fault); 3262 TEST_ASSERT(!vmx_on()); 3263 } 3264 3265 /* 3266 * This does not test real-address mode, virtual-8086 mode, protected mode, 3267 * or CPL > 0. 3268 */ 3269 static void invvpid_test_v2(void) 3270 { 3271 u64 msr; 3272 int i; 3273 unsigned types = 0; 3274 unsigned type; 3275 3276 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 3277 !(ctrl_cpu_rev[1].clr & CPU_VPID)) 3278 test_skip("VPID not supported"); 3279 3280 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3281 3282 if (!(msr & VPID_CAP_INVVPID)) 3283 test_skip("INVVPID not supported.\n"); 3284 3285 if (msr & VPID_CAP_INVVPID_ADDR) 3286 types |= 1u << INVVPID_ADDR; 3287 if (msr & VPID_CAP_INVVPID_CXTGLB) 3288 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3289 if (msr & VPID_CAP_INVVPID_ALL) 3290 types |= 1u << INVVPID_ALL; 3291 if (msr & VPID_CAP_INVVPID_CXTLOC) 3292 types |= 1u << INVVPID_CONTEXT_LOCAL; 3293 3294 if (!types) 3295 test_skip("No INVVPID types supported.\n"); 3296 3297 for (i = -127; i < 128; i++) 3298 try_invvpid(i, 0xffff, 0); 3299 3300 /* 3301 * VPID must not be more than 16 bits. 3302 */ 3303 for (i = 0; i < 64; i++) 3304 for (type = 0; type < 4; type++) 3305 if (types & (1u << type)) 3306 try_invvpid(type, 1ul << i, 0); 3307 3308 /* 3309 * VPID must not be zero, except for "all contexts." 3310 */ 3311 for (type = 0; type < 4; type++) 3312 if (types & (1u << type)) 3313 try_invvpid(type, 0, 0); 3314 3315 /* 3316 * The gla operand is only validated for single-address INVVPID. 3317 */ 3318 if (types & (1u << INVVPID_ADDR)) 3319 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3320 3321 invvpid_test_gp(); 3322 invvpid_test_ss(); 3323 invvpid_test_pf(); 3324 invvpid_test_compatibility_mode(); 3325 invvpid_test_not_in_vmx_operation(); 3326 } 3327 3328 /* 3329 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3330 * at least as far as the guest-state checks. Returns false if the 3331 * VMLAUNCH fails early and execution falls through to the next 3332 * instruction. 3333 */ 3334 static bool vmlaunch_succeeds(void) 3335 { 3336 u32 exit_reason; 3337 3338 /* 3339 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3340 * unsupported VMCS component"). The caller can then check 3341 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3342 */ 3343 vmcs_write(~0u, 0); 3344 3345 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3346 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3347 : 3348 : "r" ((u64)HOST_RSP) 3349 : "cc", "memory" 3350 : success); 3351 return false; 3352 success: 3353 exit_reason = vmcs_read(EXI_REASON); 3354 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3355 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3356 return true; 3357 } 3358 3359 /* 3360 * Try to launch the current VMCS. 3361 */ 3362 static void test_vmx_vmlaunch(u32 xerror) 3363 { 3364 bool success = vmlaunch_succeeds(); 3365 u32 vmx_inst_err; 3366 3367 report("vmlaunch %s", success == !xerror, 3368 !xerror ? "succeeds" : "fails"); 3369 if (!success && xerror) { 3370 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3371 report("VMX inst error is %d (actual %d)", 3372 vmx_inst_err == xerror, xerror, vmx_inst_err); 3373 } 3374 } 3375 3376 static void test_vmx_invalid_controls(void) 3377 { 3378 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3379 } 3380 3381 static void test_vmx_valid_controls(void) 3382 { 3383 test_vmx_vmlaunch(0); 3384 } 3385 3386 /* 3387 * Test a particular value of a VM-execution control bit, if the value 3388 * is required or if the value is zero. 3389 */ 3390 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3391 enum Encoding encoding, unsigned bit, 3392 unsigned val) 3393 { 3394 u32 mask = 1u << bit; 3395 bool expected; 3396 u32 controls; 3397 3398 if (msr.set & mask) 3399 TEST_ASSERT(msr.clr & mask); 3400 3401 /* 3402 * We can't arbitrarily turn on a control bit, because it may 3403 * introduce dependencies on other VMCS fields. So, we only 3404 * test turning on bits that have a required setting. 3405 */ 3406 if (val && (msr.clr & mask) && !(msr.set & mask)) 3407 return; 3408 3409 report_prefix_pushf("%s %s bit %d", 3410 val ? "Set" : "Clear", name, bit); 3411 3412 controls = vmcs_read(encoding); 3413 if (val) { 3414 vmcs_write(encoding, msr.set | mask); 3415 expected = (msr.clr & mask); 3416 } else { 3417 vmcs_write(encoding, msr.set & ~mask); 3418 expected = !(msr.set & mask); 3419 } 3420 if (expected) 3421 test_vmx_valid_controls(); 3422 else 3423 test_vmx_invalid_controls(); 3424 vmcs_write(encoding, controls); 3425 report_prefix_pop(); 3426 } 3427 3428 /* 3429 * Test reserved values of a VM-execution control bit, based on the 3430 * allowed bit settings from the corresponding VMX capability MSR. 3431 */ 3432 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3433 enum Encoding encoding, unsigned bit) 3434 { 3435 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3436 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3437 } 3438 3439 /* 3440 * Reserved bits in the pin-based VM-execution controls must be set 3441 * properly. Software may consult the VMX capability MSRs to determine 3442 * the proper settings. 3443 * [Intel SDM] 3444 */ 3445 static void test_pin_based_ctls(void) 3446 { 3447 unsigned bit; 3448 3449 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3450 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3451 for (bit = 0; bit < 32; bit++) 3452 test_rsvd_ctl_bit("pin-based controls", 3453 ctrl_pin_rev, PIN_CONTROLS, bit); 3454 } 3455 3456 /* 3457 * Reserved bits in the primary processor-based VM-execution controls 3458 * must be set properly. Software may consult the VMX capability MSRs 3459 * to determine the proper settings. 3460 * [Intel SDM] 3461 */ 3462 static void test_primary_processor_based_ctls(void) 3463 { 3464 unsigned bit; 3465 3466 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3467 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3468 for (bit = 0; bit < 32; bit++) 3469 test_rsvd_ctl_bit("primary processor-based controls", 3470 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3471 } 3472 3473 /* 3474 * If the "activate secondary controls" primary processor-based 3475 * VM-execution control is 1, reserved bits in the secondary 3476 * processor-based VM-execution controls must be cleared. Software may 3477 * consult the VMX capability MSRs to determine which bits are 3478 * reserved. 3479 * If the "activate secondary controls" primary processor-based 3480 * VM-execution control is 0 (or if the processor does not support the 3481 * 1-setting of that control), no checks are performed on the 3482 * secondary processor-based VM-execution controls. 3483 * [Intel SDM] 3484 */ 3485 static void test_secondary_processor_based_ctls(void) 3486 { 3487 u32 primary; 3488 u32 secondary; 3489 unsigned bit; 3490 3491 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3492 return; 3493 3494 primary = vmcs_read(CPU_EXEC_CTRL0); 3495 secondary = vmcs_read(CPU_EXEC_CTRL1); 3496 3497 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3498 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3499 for (bit = 0; bit < 32; bit++) 3500 test_rsvd_ctl_bit("secondary processor-based controls", 3501 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3502 3503 /* 3504 * When the "activate secondary controls" VM-execution control 3505 * is clear, there are no checks on the secondary controls. 3506 */ 3507 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3508 vmcs_write(CPU_EXEC_CTRL1, ~0); 3509 report("Secondary processor-based controls ignored", 3510 vmlaunch_succeeds()); 3511 vmcs_write(CPU_EXEC_CTRL1, secondary); 3512 vmcs_write(CPU_EXEC_CTRL0, primary); 3513 } 3514 3515 static void try_cr3_target_count(unsigned i, unsigned max) 3516 { 3517 report_prefix_pushf("CR3 target count 0x%x", i); 3518 vmcs_write(CR3_TARGET_COUNT, i); 3519 if (i <= max) 3520 test_vmx_valid_controls(); 3521 else 3522 test_vmx_invalid_controls(); 3523 report_prefix_pop(); 3524 } 3525 3526 /* 3527 * The CR3-target count must not be greater than 4. Future processors 3528 * may support a different number of CR3-target values. Software 3529 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3530 * number of values supported. 3531 * [Intel SDM] 3532 */ 3533 static void test_cr3_targets(void) 3534 { 3535 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3536 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3537 unsigned i; 3538 3539 printf("\nSupported CR3 targets: %d\n", supported_targets); 3540 TEST_ASSERT(supported_targets <= 256); 3541 3542 try_cr3_target_count(-1u, supported_targets); 3543 try_cr3_target_count(0x80000000, supported_targets); 3544 try_cr3_target_count(0x7fffffff, supported_targets); 3545 for (i = 0; i <= supported_targets + 1; i++) 3546 try_cr3_target_count(i, supported_targets); 3547 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3548 } 3549 3550 /* 3551 * Test a particular address setting in the VMCS 3552 */ 3553 static void test_vmcs_addr(const char *name, 3554 enum Encoding encoding, 3555 u64 align, 3556 bool ignored, 3557 bool skip_beyond_mapped_ram, 3558 u64 addr) 3559 { 3560 report_prefix_pushf("%s = %lx", name, addr); 3561 vmcs_write(encoding, addr); 3562 if (skip_beyond_mapped_ram && 3563 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3564 addr < (1ul << cpuid_maxphyaddr())) 3565 printf("Skipping physical address beyond mapped RAM\n"); 3566 else if (ignored || (IS_ALIGNED(addr, align) && 3567 addr < (1ul << cpuid_maxphyaddr()))) 3568 test_vmx_valid_controls(); 3569 else 3570 test_vmx_invalid_controls(); 3571 report_prefix_pop(); 3572 } 3573 3574 /* 3575 * Test interesting values for a VMCS address 3576 */ 3577 static void test_vmcs_addr_values(const char *name, 3578 enum Encoding encoding, 3579 u64 align, 3580 bool ignored, 3581 bool skip_beyond_mapped_ram, 3582 u32 bit_start, u32 bit_end) 3583 { 3584 unsigned i; 3585 u64 orig_val = vmcs_read(encoding); 3586 3587 for (i = bit_start; i <= bit_end; i++) 3588 test_vmcs_addr(name, encoding, align, ignored, 3589 skip_beyond_mapped_ram, 1ul << i); 3590 3591 test_vmcs_addr(name, encoding, align, ignored, 3592 skip_beyond_mapped_ram, PAGE_SIZE - 1); 3593 test_vmcs_addr(name, encoding, align, ignored, 3594 skip_beyond_mapped_ram, PAGE_SIZE); 3595 test_vmcs_addr(name, encoding, align, ignored, 3596 skip_beyond_mapped_ram, 3597 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3598 test_vmcs_addr(name, encoding, align, ignored, 3599 skip_beyond_mapped_ram, -1ul); 3600 3601 vmcs_write(encoding, orig_val); 3602 } 3603 3604 /* 3605 * Test a physical address reference in the VMCS, when the corresponding 3606 * feature is enabled and when the corresponding feature is disabled. 3607 */ 3608 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3609 const char *field_name, 3610 const char *control_name, u64 align, 3611 bool skip_beyond_mapped_ram, 3612 bool control_primary) 3613 { 3614 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3615 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3616 u64 page_addr; 3617 3618 if (control_primary) { 3619 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3620 return; 3621 } else { 3622 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3623 return; 3624 } 3625 3626 page_addr = vmcs_read(field); 3627 3628 report_prefix_pushf("%s enabled", control_name); 3629 if (control_primary) { 3630 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3631 } else { 3632 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3633 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3634 } 3635 3636 test_vmcs_addr_values(field_name, field, align, false, 3637 skip_beyond_mapped_ram, 0, 63); 3638 report_prefix_pop(); 3639 3640 report_prefix_pushf("%s disabled", control_name); 3641 if (control_primary) { 3642 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3643 } else { 3644 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3645 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3646 } 3647 3648 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3649 report_prefix_pop(); 3650 3651 vmcs_write(field, page_addr); 3652 vmcs_write(CPU_EXEC_CTRL0, primary); 3653 vmcs_write(CPU_EXEC_CTRL1, secondary); 3654 } 3655 3656 /* 3657 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3658 * each I/O-bitmap address must be 0. Neither address should set any 3659 * bits beyond the processor's physical-address width. 3660 * [Intel SDM] 3661 */ 3662 static void test_io_bitmaps(void) 3663 { 3664 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3665 "I/O bitmap A", "Use I/O bitmaps", 3666 PAGE_SIZE, false, true); 3667 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3668 "I/O bitmap B", "Use I/O bitmaps", 3669 PAGE_SIZE, false, true); 3670 } 3671 3672 /* 3673 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3674 * the MSR-bitmap address must be 0. The address should not set any 3675 * bits beyond the processor's physical-address width. 3676 * [Intel SDM] 3677 */ 3678 static void test_msr_bitmap(void) 3679 { 3680 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3681 "MSR bitmap", "Use MSR bitmaps", 3682 PAGE_SIZE, false, true); 3683 } 3684 3685 /* 3686 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3687 * address must satisfy the following checks: 3688 * - Bits 11:0 of the address must be 0. 3689 * - The address should not set any bits beyond the processor's 3690 * physical-address width. 3691 * [Intel SDM] 3692 */ 3693 static void test_apic_virt_addr(void) 3694 { 3695 /* 3696 * Ensure the processor will never use the virtual-APIC page, since 3697 * we will point it to invalid RAM. Otherwise KVM is puzzled about 3698 * what we're trying to achieve and fails vmentry. 3699 */ 3700 u32 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 3701 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0 | CPU_CR8_LOAD | CPU_CR8_STORE); 3702 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3703 "virtual-APIC address", "Use TPR shadow", 3704 PAGE_SIZE, false, true); 3705 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 3706 } 3707 3708 /* 3709 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3710 * APIC-access address must satisfy the following checks: 3711 * - Bits 11:0 of the address must be 0. 3712 * - The address should not set any bits beyond the processor's 3713 * physical-address width. 3714 * [Intel SDM] 3715 */ 3716 static void test_apic_access_addr(void) 3717 { 3718 void *apic_access_page = alloc_page(); 3719 3720 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3721 3722 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3723 "APIC-access address", 3724 "virtualize APIC-accesses", PAGE_SIZE, 3725 true, false); 3726 } 3727 3728 static bool set_bit_pattern(u8 mask, u32 *secondary) 3729 { 3730 u8 i; 3731 bool flag = false; 3732 u32 test_bits[3] = { 3733 CPU_VIRT_X2APIC, 3734 CPU_APIC_REG_VIRT, 3735 CPU_VINTD 3736 }; 3737 3738 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3739 if ((mask & (1u << i)) && 3740 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3741 *secondary |= test_bits[i]; 3742 flag = true; 3743 } 3744 } 3745 3746 return (flag); 3747 } 3748 3749 /* 3750 * If the "use TPR shadow" VM-execution control is 0, the following 3751 * VM-execution controls must also be 0: 3752 * - virtualize x2APIC mode 3753 * - APIC-register virtualization 3754 * - virtual-interrupt delivery 3755 * [Intel SDM] 3756 * 3757 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3758 * "virtualize APIC accesses" VM-execution control must be 0. 3759 * [Intel SDM] 3760 */ 3761 static void test_apic_virtual_ctls(void) 3762 { 3763 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3764 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3765 u32 primary = saved_primary; 3766 u32 secondary = saved_secondary; 3767 bool ctrl = false; 3768 char str[10] = "disabled"; 3769 u8 i = 0, j; 3770 3771 /* 3772 * First test 3773 */ 3774 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3775 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3776 return; 3777 3778 primary |= CPU_SECONDARY; 3779 primary &= ~CPU_TPR_SHADOW; 3780 vmcs_write(CPU_EXEC_CTRL0, primary); 3781 3782 while (1) { 3783 for (j = 1; j < 8; j++) { 3784 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3785 if (primary & CPU_TPR_SHADOW) { 3786 ctrl = true; 3787 } else { 3788 if (! set_bit_pattern(j, &secondary)) 3789 ctrl = true; 3790 else 3791 ctrl = false; 3792 } 3793 3794 vmcs_write(CPU_EXEC_CTRL1, secondary); 3795 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3796 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3797 if (ctrl) 3798 test_vmx_valid_controls(); 3799 else 3800 test_vmx_invalid_controls(); 3801 report_prefix_pop(); 3802 } 3803 3804 if (i == 1) 3805 break; 3806 i++; 3807 3808 primary |= CPU_TPR_SHADOW; 3809 vmcs_write(CPU_EXEC_CTRL0, primary); 3810 strcpy(str, "enabled"); 3811 } 3812 3813 /* 3814 * Second test 3815 */ 3816 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3817 3818 primary = saved_primary; 3819 secondary = saved_secondary; 3820 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3821 return; 3822 3823 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3824 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3825 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3826 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3827 test_vmx_valid_controls(); 3828 report_prefix_pop(); 3829 3830 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3831 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3832 test_vmx_valid_controls(); 3833 report_prefix_pop(); 3834 3835 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3836 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3837 test_vmx_invalid_controls(); 3838 report_prefix_pop(); 3839 3840 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3841 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3842 test_vmx_valid_controls(); 3843 report_prefix_pop(); 3844 3845 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3846 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3847 } 3848 3849 /* 3850 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3851 * "external-interrupt exiting" VM-execution control must be 1. 3852 * [Intel SDM] 3853 */ 3854 static void test_virtual_intr_ctls(void) 3855 { 3856 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3857 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3858 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3859 u32 primary = saved_primary; 3860 u32 secondary = saved_secondary; 3861 u32 pin = saved_pin; 3862 3863 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 3864 (ctrl_pin_rev.clr & PIN_EXTINT))) 3865 return; 3866 3867 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3868 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 3869 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3870 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 3871 test_vmx_valid_controls(); 3872 report_prefix_pop(); 3873 3874 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 3875 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3876 test_vmx_invalid_controls(); 3877 report_prefix_pop(); 3878 3879 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 3880 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 3881 test_vmx_valid_controls(); 3882 report_prefix_pop(); 3883 3884 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3885 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3886 test_vmx_invalid_controls(); 3887 report_prefix_pop(); 3888 3889 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3890 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3891 vmcs_write(PIN_CONTROLS, saved_pin); 3892 } 3893 3894 static void test_pi_desc_addr(u64 addr, bool ctrl) 3895 { 3896 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 3897 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 3898 if (ctrl) 3899 test_vmx_valid_controls(); 3900 else 3901 test_vmx_invalid_controls(); 3902 report_prefix_pop(); 3903 } 3904 3905 /* 3906 * If the “process posted interrupts†VM-execution control is 1, the 3907 * following must be true: 3908 * 3909 * - The “virtual-interrupt delivery†VM-execution control is 1. 3910 * - The “acknowledge interrupt on exit†VM-exit control is 1. 3911 * - The posted-interrupt notification vector has a value in the 3912 * - range 0–255 (bits 15:8 are all 0). 3913 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 3914 * - The posted-interrupt descriptor address does not set any bits 3915 * beyond the processor's physical-address width. 3916 * [Intel SDM] 3917 */ 3918 static void test_posted_intr(void) 3919 { 3920 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3921 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3922 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3923 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 3924 u32 primary = saved_primary; 3925 u32 secondary = saved_secondary; 3926 u32 pin = saved_pin; 3927 u32 exit_ctl = exit_ctl_saved; 3928 u16 vec; 3929 int i; 3930 3931 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 3932 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 3933 (ctrl_exit_rev.clr & EXI_INTA))) 3934 return; 3935 3936 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3937 3938 /* 3939 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 3940 */ 3941 pin |= PIN_POST_INTR; 3942 vmcs_write(PIN_CONTROLS, pin); 3943 secondary &= ~CPU_VINTD; 3944 vmcs_write(CPU_EXEC_CTRL1, secondary); 3945 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 3946 test_vmx_invalid_controls(); 3947 report_prefix_pop(); 3948 3949 secondary |= CPU_VINTD; 3950 vmcs_write(CPU_EXEC_CTRL1, secondary); 3951 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 3952 test_vmx_invalid_controls(); 3953 report_prefix_pop(); 3954 3955 exit_ctl &= ~EXI_INTA; 3956 vmcs_write(EXI_CONTROLS, exit_ctl); 3957 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 3958 test_vmx_invalid_controls(); 3959 report_prefix_pop(); 3960 3961 exit_ctl |= EXI_INTA; 3962 vmcs_write(EXI_CONTROLS, exit_ctl); 3963 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3964 test_vmx_valid_controls(); 3965 report_prefix_pop(); 3966 3967 secondary &= ~CPU_VINTD; 3968 vmcs_write(CPU_EXEC_CTRL1, secondary); 3969 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 3970 test_vmx_invalid_controls(); 3971 report_prefix_pop(); 3972 3973 secondary |= CPU_VINTD; 3974 vmcs_write(CPU_EXEC_CTRL1, secondary); 3975 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3976 test_vmx_valid_controls(); 3977 report_prefix_pop(); 3978 3979 /* 3980 * Test posted-interrupt notification vector 3981 */ 3982 for (i = 0; i < 8; i++) { 3983 vec = (1ul << i); 3984 vmcs_write(PINV, vec); 3985 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3986 test_vmx_valid_controls(); 3987 report_prefix_pop(); 3988 } 3989 for (i = 8; i < 16; i++) { 3990 vec = (1ul << i); 3991 vmcs_write(PINV, vec); 3992 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3993 test_vmx_invalid_controls(); 3994 report_prefix_pop(); 3995 } 3996 3997 vec &= ~(0xff << 8); 3998 vmcs_write(PINV, vec); 3999 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4000 test_vmx_valid_controls(); 4001 report_prefix_pop(); 4002 4003 /* 4004 * Test posted-interrupt descriptor addresss 4005 */ 4006 for (i = 0; i < 6; i++) { 4007 test_pi_desc_addr(1ul << i, false); 4008 } 4009 4010 test_pi_desc_addr(0xf0, false); 4011 test_pi_desc_addr(0xff, false); 4012 test_pi_desc_addr(0x0f, false); 4013 test_pi_desc_addr(0x8000, true); 4014 test_pi_desc_addr(0x00, true); 4015 test_pi_desc_addr(0xc000, true); 4016 4017 test_vmcs_addr_values("process-posted interrupts", 4018 POSTED_INTR_DESC_ADDR, 64, 4019 false, false, 0, 63); 4020 4021 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4022 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4023 vmcs_write(PIN_CONTROLS, saved_pin); 4024 } 4025 4026 static void test_apic_ctls(void) 4027 { 4028 test_apic_virt_addr(); 4029 test_apic_access_addr(); 4030 test_apic_virtual_ctls(); 4031 test_virtual_intr_ctls(); 4032 test_posted_intr(); 4033 } 4034 4035 /* 4036 * If the “enable VPID†VM-execution control is 1, the value of the 4037 * of the VPID VM-execution control field must not be 0000H. 4038 * [Intel SDM] 4039 */ 4040 static void test_vpid(void) 4041 { 4042 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4043 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4044 u16 vpid = 0x0000; 4045 int i; 4046 4047 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4048 (ctrl_cpu_rev[1].clr & CPU_VPID))) { 4049 printf("Secondary controls and/or VPID not supported\n"); 4050 return; 4051 } 4052 4053 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 4054 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 4055 vmcs_write(VPID, vpid); 4056 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 4057 test_vmx_valid_controls(); 4058 report_prefix_pop(); 4059 4060 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 4061 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4062 test_vmx_invalid_controls(); 4063 report_prefix_pop(); 4064 4065 for (i = 0; i < 16; i++) { 4066 vpid = (short)1 << i;; 4067 vmcs_write(VPID, vpid); 4068 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4069 test_vmx_valid_controls(); 4070 report_prefix_pop(); 4071 } 4072 4073 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4074 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4075 } 4076 4077 static void set_vtpr(unsigned vtpr) 4078 { 4079 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 4080 } 4081 4082 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 4083 { 4084 bool valid = true; 4085 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4086 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4087 4088 if ((primary & CPU_TPR_SHADOW) && 4089 (!(primary & CPU_SECONDARY) || 4090 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4091 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 4092 4093 set_vtpr(vtpr); 4094 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 4095 threshold, (vtpr >> 4) & 0xf); 4096 if (valid) 4097 test_vmx_valid_controls(); 4098 else 4099 test_vmx_invalid_controls(); 4100 report_prefix_pop(); 4101 } 4102 4103 static void test_invalid_event_injection(void) 4104 { 4105 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4106 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4107 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4108 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4109 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4110 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4111 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4112 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4113 u32 cnt; 4114 4115 /* Setup */ 4116 report_prefix_push("invalid event injection"); 4117 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4118 vmcs_write(ENT_INST_LEN, 0x00000001); 4119 4120 /* The field’s interruption type is not set to a reserved value. */ 4121 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4122 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4123 "RESERVED interruption type invalid [-]", 4124 ent_intr_info); 4125 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4126 test_vmx_invalid_controls(); 4127 report_prefix_pop(); 4128 4129 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4130 DE_VECTOR; 4131 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4132 "RESERVED interruption type invalid [+]", 4133 ent_intr_info); 4134 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4135 test_vmx_valid_controls(); 4136 report_prefix_pop(); 4137 4138 /* If the interruption type is other event, the vector is 0. */ 4139 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4140 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4141 "(OTHER EVENT && vector != 0) invalid [-]", 4142 ent_intr_info); 4143 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4144 test_vmx_invalid_controls(); 4145 report_prefix_pop(); 4146 4147 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4148 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4149 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4150 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4151 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4152 test_vmx_invalid_controls(); 4153 report_prefix_pop(); 4154 4155 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4156 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4157 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4158 "(NMI && vector == 2) valid [+]", ent_intr_info); 4159 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4160 test_vmx_valid_controls(); 4161 report_prefix_pop(); 4162 4163 /* 4164 * If the interruption type 4165 * is HW exception, the vector is at most 31. 4166 */ 4167 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4168 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4169 "(HW exception && vector > 31) invalid [-]", 4170 ent_intr_info); 4171 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4172 test_vmx_invalid_controls(); 4173 report_prefix_pop(); 4174 4175 /* 4176 * deliver-error-code is 1 iff either 4177 * (a) the "unrestricted guest" VM-execution control is 0 4178 * (b) CR0.PE is set. 4179 */ 4180 4181 /* Assert that unrestricted guest is disabled or unsupported */ 4182 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 4183 !(secondary_save & CPU_URG)); 4184 4185 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4186 GP_VECTOR; 4187 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4188 "error code <-> (!URG || prot_mode) [-]", 4189 ent_intr_info); 4190 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4191 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4192 test_vmx_invalid_controls(); 4193 report_prefix_pop(); 4194 4195 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4196 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4197 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4198 "error code <-> (!URG || prot_mode) [+]", 4199 ent_intr_info); 4200 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4201 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4202 test_vmx_valid_controls(); 4203 report_prefix_pop(); 4204 4205 if (enable_unrestricted_guest()) 4206 goto skip_unrestricted_guest; 4207 4208 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4209 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4210 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4211 "error code <-> (!URG || prot_mode) [-]", 4212 ent_intr_info); 4213 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4214 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4215 test_vmx_invalid_controls(); 4216 report_prefix_pop(); 4217 4218 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4219 GP_VECTOR; 4220 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4221 "error code <-> (!URG || prot_mode) [-]", 4222 ent_intr_info); 4223 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4224 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4225 test_vmx_invalid_controls(); 4226 report_prefix_pop(); 4227 4228 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4229 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4230 4231 skip_unrestricted_guest: 4232 vmcs_write(GUEST_CR0, guest_cr0_save); 4233 4234 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4235 report_prefix_push("error code <-> HW exception"); 4236 for (cnt = 0; cnt < 8; cnt++) { 4237 u32 exception_type_mask = cnt << 8; 4238 u32 deliver_error_code_mask = 4239 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4240 INTR_INFO_DELIVER_CODE_MASK : 0; 4241 4242 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4243 exception_type_mask | GP_VECTOR; 4244 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4245 ent_intr_info); 4246 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4247 test_vmx_invalid_controls(); 4248 report_prefix_pop(); 4249 } 4250 report_prefix_pop(); 4251 4252 /* 4253 * deliver-error-code is 1 iff the the vector 4254 * indicates an exception that would normally deliver an error code 4255 */ 4256 report_prefix_push("error code <-> vector delivers error code"); 4257 for (cnt = 0; cnt < 32; cnt++) { 4258 bool has_error_code = false; 4259 u32 deliver_error_code_mask; 4260 4261 switch (cnt) { 4262 case DF_VECTOR: 4263 case TS_VECTOR: 4264 case NP_VECTOR: 4265 case SS_VECTOR: 4266 case GP_VECTOR: 4267 case PF_VECTOR: 4268 case AC_VECTOR: 4269 has_error_code = true; 4270 } 4271 4272 /* Negative case */ 4273 deliver_error_code_mask = has_error_code ? 4274 0 : 4275 INTR_INFO_DELIVER_CODE_MASK; 4276 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4277 INTR_TYPE_HARD_EXCEPTION | cnt; 4278 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4279 ent_intr_info); 4280 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4281 test_vmx_invalid_controls(); 4282 report_prefix_pop(); 4283 4284 /* Positive case */ 4285 deliver_error_code_mask = has_error_code ? 4286 INTR_INFO_DELIVER_CODE_MASK : 4287 0; 4288 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4289 INTR_TYPE_HARD_EXCEPTION | cnt; 4290 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4291 ent_intr_info); 4292 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4293 test_vmx_valid_controls(); 4294 report_prefix_pop(); 4295 } 4296 report_prefix_pop(); 4297 4298 /* Reserved bits in the field (30:12) are 0. */ 4299 report_prefix_push("reserved bits clear"); 4300 for (cnt = 12; cnt <= 30; cnt++) { 4301 ent_intr_info = ent_intr_info_base | 4302 INTR_INFO_DELIVER_CODE_MASK | 4303 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4304 (1U << cnt); 4305 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4306 ent_intr_info); 4307 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4308 test_vmx_invalid_controls(); 4309 report_prefix_pop(); 4310 } 4311 report_prefix_pop(); 4312 4313 /* 4314 * If deliver-error-code is 1 4315 * bits 31:16 of the VM-entry exception error-code field are 0. 4316 */ 4317 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4318 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4319 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4320 "VM-entry exception error code[31:16] clear", 4321 ent_intr_info); 4322 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4323 for (cnt = 16; cnt <= 31; cnt++) { 4324 ent_intr_err = 1U << cnt; 4325 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4326 ent_intr_err); 4327 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4328 test_vmx_invalid_controls(); 4329 report_prefix_pop(); 4330 } 4331 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4332 report_prefix_pop(); 4333 4334 /* 4335 * If the interruption type is software interrupt, software exception, 4336 * or privileged software exception, the VM-entry instruction-length 4337 * field is in the range 0–15. 4338 */ 4339 4340 for (cnt = 0; cnt < 3; cnt++) { 4341 switch (cnt) { 4342 case 0: 4343 ent_intr_info = ent_intr_info_base | 4344 INTR_TYPE_SOFT_INTR; 4345 break; 4346 case 1: 4347 ent_intr_info = ent_intr_info_base | 4348 INTR_TYPE_SOFT_EXCEPTION; 4349 break; 4350 case 2: 4351 ent_intr_info = ent_intr_info_base | 4352 INTR_TYPE_PRIV_SW_EXCEPTION; 4353 break; 4354 } 4355 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4356 "VM-entry instruction-length check", 4357 ent_intr_info); 4358 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4359 4360 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4361 ent_intr_len = -1; 4362 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4363 ent_intr_len); 4364 vmcs_write(ENT_INST_LEN, ent_intr_len); 4365 test_vmx_invalid_controls(); 4366 report_prefix_pop(); 4367 4368 /* Instruction length set to 16 should fail */ 4369 ent_intr_len = 0x00000010; 4370 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4371 ent_intr_len); 4372 vmcs_write(ENT_INST_LEN, 0x00000010); 4373 test_vmx_invalid_controls(); 4374 report_prefix_pop(); 4375 4376 report_prefix_pop(); 4377 } 4378 4379 /* Cleanup */ 4380 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4381 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4382 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4383 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4384 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4385 vmcs_write(GUEST_CR0, guest_cr0_save); 4386 report_prefix_pop(); 4387 } 4388 4389 /* 4390 * Test interesting vTPR values for a given TPR threshold. 4391 */ 4392 static void test_vtpr_values(unsigned threshold) 4393 { 4394 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4395 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4396 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4397 } 4398 4399 static void try_tpr_threshold(unsigned threshold) 4400 { 4401 bool valid = true; 4402 4403 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4404 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4405 4406 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4407 (secondary & CPU_VINTD))) 4408 valid = !(threshold >> 4); 4409 4410 set_vtpr(-1); 4411 vmcs_write(TPR_THRESHOLD, threshold); 4412 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4413 if (valid) 4414 test_vmx_valid_controls(); 4415 else 4416 test_vmx_invalid_controls(); 4417 report_prefix_pop(); 4418 4419 if (valid) 4420 test_vtpr_values(threshold); 4421 } 4422 4423 /* 4424 * Test interesting TPR threshold values. 4425 */ 4426 static void test_tpr_threshold_values(void) 4427 { 4428 unsigned i; 4429 4430 for (i = 0; i < 0x10; i++) 4431 try_tpr_threshold(i); 4432 for (i = 4; i < 32; i++) 4433 try_tpr_threshold(1u << i); 4434 try_tpr_threshold(-1u); 4435 try_tpr_threshold(0x7fffffff); 4436 } 4437 4438 /* 4439 * This test covers the following two VM entry checks: 4440 * 4441 * i) If the "use TPR shadow" VM-execution control is 1 and the 4442 * "virtual-interrupt delivery" VM-execution control is 0, bits 4443 * 31:4 of the TPR threshold VM-execution control field must 4444 be 0. 4445 * [Intel SDM] 4446 * 4447 * ii) If the "use TPR shadow" VM-execution control is 1, the 4448 * "virtual-interrupt delivery" VM-execution control is 0 4449 * and the "virtualize APIC accesses" VM-execution control 4450 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4451 * control field must not be greater than the value of bits 4452 * 7:4 of VTPR. 4453 * [Intel SDM] 4454 */ 4455 static void test_tpr_threshold(void) 4456 { 4457 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4458 u64 apic_virt_addr = vmcs_read(APIC_VIRT_ADDR); 4459 u64 threshold = vmcs_read(TPR_THRESHOLD); 4460 void *virtual_apic_page; 4461 4462 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4463 return; 4464 4465 virtual_apic_page = alloc_page(); 4466 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4467 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4468 4469 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4470 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4471 test_tpr_threshold_values(); 4472 report_prefix_pop(); 4473 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4474 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4475 test_tpr_threshold_values(); 4476 report_prefix_pop(); 4477 4478 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4479 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4480 goto out; 4481 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4482 4483 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4484 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4485 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4486 test_tpr_threshold_values(); 4487 report_prefix_pop(); 4488 4489 vmcs_write(CPU_EXEC_CTRL0, 4490 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4491 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4492 test_tpr_threshold_values(); 4493 report_prefix_pop(); 4494 } 4495 4496 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4497 vmcs_write(CPU_EXEC_CTRL0, 4498 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4499 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4500 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4501 test_tpr_threshold_values(); 4502 report_prefix_pop(); 4503 4504 vmcs_write(CPU_EXEC_CTRL0, 4505 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4506 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4507 test_tpr_threshold_values(); 4508 report_prefix_pop(); 4509 } 4510 4511 if ((ctrl_cpu_rev[1].clr & 4512 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4513 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4514 vmcs_write(CPU_EXEC_CTRL0, 4515 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4516 vmcs_write(CPU_EXEC_CTRL1, 4517 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4518 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4519 test_tpr_threshold_values(); 4520 report_prefix_pop(); 4521 4522 vmcs_write(CPU_EXEC_CTRL0, 4523 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4524 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4525 test_tpr_threshold_values(); 4526 report_prefix_pop(); 4527 } 4528 4529 vmcs_write(CPU_EXEC_CTRL1, secondary); 4530 out: 4531 vmcs_write(TPR_THRESHOLD, threshold); 4532 vmcs_write(APIC_VIRT_ADDR, apic_virt_addr); 4533 vmcs_write(CPU_EXEC_CTRL0, primary); 4534 } 4535 4536 /* 4537 * This test verifies the following two vmentry checks: 4538 * 4539 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4540 * VM-execution control must be 0. 4541 * [Intel SDM] 4542 * 4543 * If the “virtual NMIs” VM-execution control is 0, the “NMI-window 4544 * exiting” VM-execution control must be 0. 4545 * [Intel SDM] 4546 */ 4547 static void test_nmi_ctrls(void) 4548 { 4549 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4550 4551 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4552 (PIN_NMI | PIN_VIRT_NMI)) { 4553 printf("NMI exiting and Virtual NMIs are not supported !\n"); 4554 return; 4555 } 4556 4557 /* Save the controls so that we can restore them after our tests */ 4558 pin_ctrls = vmcs_read(PIN_CONTROLS); 4559 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4560 4561 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4562 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4563 4564 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4565 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4566 test_vmx_valid_controls(); 4567 report_prefix_pop(); 4568 4569 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4570 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4571 test_vmx_invalid_controls(); 4572 report_prefix_pop(); 4573 4574 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4575 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4576 test_vmx_valid_controls(); 4577 report_prefix_pop(); 4578 4579 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4580 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4581 test_vmx_valid_controls(); 4582 report_prefix_pop(); 4583 4584 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4585 report_info("NMI-window exiting is not supported, skipping..."); 4586 goto done; 4587 } 4588 4589 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4590 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4591 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4592 test_vmx_invalid_controls(); 4593 report_prefix_pop(); 4594 4595 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4596 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4597 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4598 test_vmx_valid_controls(); 4599 report_prefix_pop(); 4600 4601 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4602 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4603 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4604 test_vmx_valid_controls(); 4605 report_prefix_pop(); 4606 4607 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4608 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4609 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4610 test_vmx_valid_controls(); 4611 report_prefix_pop(); 4612 4613 /* Restore the controls to their original values */ 4614 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4615 done: 4616 vmcs_write(PIN_CONTROLS, pin_ctrls); 4617 } 4618 4619 static void test_eptp_ad_bit(u64 eptp, bool ctrl) 4620 { 4621 vmcs_write(EPTP, eptp); 4622 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4623 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4624 if (ctrl) 4625 test_vmx_valid_controls(); 4626 else 4627 test_vmx_invalid_controls(); 4628 report_prefix_pop(); 4629 4630 } 4631 4632 /* 4633 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4634 * control field must satisfy the following checks: 4635 * 4636 * - The EPT memory type (bits 2:0) must be a value supported by the 4637 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4638 * - Bits 5:3 (1 less than the EPT page-walk length) must be 3, 4639 * indicating an EPT page-walk length of 4. 4640 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4641 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4642 * indicating that the processor does not support accessed and dirty 4643 * dirty flags for EPT. 4644 * - Reserved bits 11:7 and 63:N (where N is the processor's 4645 * physical-address width) must all be 0. 4646 * 4647 * 2. If the "unrestricted guest" VM-execution control is 1, the 4648 * "enable EPT" VM-execution control must also be 1. 4649 */ 4650 static void test_ept_eptp(void) 4651 { 4652 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4653 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4654 u64 eptp_saved = vmcs_read(EPTP); 4655 u32 primary = primary_saved; 4656 u32 secondary = secondary_saved; 4657 u64 msr, eptp = eptp_saved; 4658 bool un_cache = false; 4659 bool wr_bk = false; 4660 bool ctrl; 4661 u32 i, maxphysaddr; 4662 u64 j, resv_bits_mask = 0; 4663 4664 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4665 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4666 printf("\"CPU secondary\" and/or \"enable EPT\" execution controls are not supported !\n"); 4667 return; 4668 } 4669 4670 /* 4671 * Memory type (bits 2:0) 4672 */ 4673 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 4674 if (msr & EPT_CAP_UC) 4675 un_cache = true; 4676 if (msr & EPT_CAP_WB) 4677 wr_bk = true; 4678 4679 primary |= CPU_SECONDARY; 4680 vmcs_write(CPU_EXEC_CTRL0, primary); 4681 secondary |= CPU_EPT; 4682 vmcs_write(CPU_EXEC_CTRL1, secondary); 4683 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4684 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4685 vmcs_write(EPTP, eptp); 4686 4687 for (i = 0; i < 8; i++) { 4688 if (i == 0) { 4689 if (un_cache) { 4690 report_info("EPT paging structure memory-type is Un-cacheable\n"); 4691 ctrl = true; 4692 } else { 4693 ctrl = false; 4694 } 4695 } else if (i == 6) { 4696 if (wr_bk) { 4697 report_info("EPT paging structure memory-type is Write-back\n"); 4698 ctrl = true; 4699 } else { 4700 ctrl = false; 4701 } 4702 } else { 4703 ctrl = false; 4704 } 4705 4706 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4707 vmcs_write(EPTP, eptp); 4708 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4709 eptp & EPT_MEM_TYPE_MASK); 4710 if (ctrl) 4711 test_vmx_valid_controls(); 4712 else 4713 test_vmx_invalid_controls(); 4714 report_prefix_pop(); 4715 } 4716 4717 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4718 4719 /* 4720 * Page walk length (bits 5:3) 4721 */ 4722 for (i = 0; i < 8; i++) { 4723 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4724 (i << EPTP_PG_WALK_LEN_SHIFT); 4725 if (i == 3) 4726 ctrl = true; 4727 else 4728 ctrl = false; 4729 4730 vmcs_write(EPTP, eptp); 4731 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4732 eptp & EPTP_PG_WALK_LEN_MASK); 4733 if (ctrl) 4734 test_vmx_valid_controls(); 4735 else 4736 test_vmx_invalid_controls(); 4737 report_prefix_pop(); 4738 } 4739 4740 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4741 3ul << EPTP_PG_WALK_LEN_SHIFT; 4742 4743 /* 4744 * Accessed and dirty flag (bit 6) 4745 */ 4746 if (msr & EPT_CAP_AD_FLAG) { 4747 report_info("Processor supports accessed and dirty flag"); 4748 eptp &= ~EPTP_AD_FLAG; 4749 test_eptp_ad_bit(eptp, true); 4750 4751 eptp |= EPTP_AD_FLAG; 4752 test_eptp_ad_bit(eptp, true); 4753 } else { 4754 report_info("Processor does not supports accessed and dirty flag"); 4755 eptp &= ~EPTP_AD_FLAG; 4756 test_eptp_ad_bit(eptp, true); 4757 4758 eptp |= EPTP_AD_FLAG; 4759 test_eptp_ad_bit(eptp, false); 4760 } 4761 4762 /* 4763 * Reserved bits [11:7] and [63:N] 4764 */ 4765 for (i = 0; i < 32; i++) { 4766 eptp = (eptp & 4767 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4768 (i << EPTP_RESERV_BITS_SHIFT); 4769 vmcs_write(EPTP, eptp); 4770 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4771 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4772 EPTP_RESERV_BITS_MASK); 4773 if (i == 0) 4774 test_vmx_valid_controls(); 4775 else 4776 test_vmx_invalid_controls(); 4777 report_prefix_pop(); 4778 } 4779 4780 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4781 4782 maxphysaddr = cpuid_maxphyaddr(); 4783 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4784 resv_bits_mask |= 1ul << i; 4785 } 4786 4787 for (j = maxphysaddr - 1; j <= 63; j++) { 4788 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4789 (j < maxphysaddr ? 0 : 1ul << j); 4790 vmcs_write(EPTP, eptp); 4791 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4792 (eptp >> maxphysaddr) & resv_bits_mask); 4793 if (j < maxphysaddr) 4794 test_vmx_valid_controls(); 4795 else 4796 test_vmx_invalid_controls(); 4797 report_prefix_pop(); 4798 } 4799 4800 secondary &= ~(CPU_EPT | CPU_URG); 4801 vmcs_write(CPU_EXEC_CTRL1, secondary); 4802 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4803 test_vmx_valid_controls(); 4804 report_prefix_pop(); 4805 4806 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) 4807 goto skip_unrestricted_guest; 4808 4809 secondary |= CPU_URG; 4810 vmcs_write(CPU_EXEC_CTRL1, secondary); 4811 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4812 test_vmx_invalid_controls(); 4813 report_prefix_pop(); 4814 4815 secondary |= CPU_EPT; 4816 setup_dummy_ept(); 4817 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4818 test_vmx_valid_controls(); 4819 report_prefix_pop(); 4820 4821 skip_unrestricted_guest: 4822 secondary &= ~CPU_URG; 4823 vmcs_write(CPU_EXEC_CTRL1, secondary); 4824 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4825 test_vmx_valid_controls(); 4826 report_prefix_pop(); 4827 4828 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4829 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4830 vmcs_write(EPTP, eptp_saved); 4831 } 4832 4833 /* 4834 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4835 * VM-execution control must also be 1. In addition, the PML address 4836 * must satisfy the following checks: 4837 * 4838 * * Bits 11:0 of the address must be 0. 4839 * * The address should not set any bits beyond the processor's 4840 * physical-address width. 4841 * 4842 * [Intel SDM] 4843 */ 4844 static void test_pml(void) 4845 { 4846 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4847 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4848 u32 primary = primary_saved; 4849 u32 secondary = secondary_saved; 4850 4851 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4852 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 4853 printf("\"Secondary execution\" control or \"enable EPT\" control or \"enable PML\" control is not supported !\n"); 4854 return; 4855 } 4856 4857 primary |= CPU_SECONDARY; 4858 vmcs_write(CPU_EXEC_CTRL0, primary); 4859 secondary &= ~(CPU_PML | CPU_EPT); 4860 vmcs_write(CPU_EXEC_CTRL1, secondary); 4861 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 4862 test_vmx_valid_controls(); 4863 report_prefix_pop(); 4864 4865 secondary |= CPU_PML; 4866 vmcs_write(CPU_EXEC_CTRL1, secondary); 4867 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 4868 test_vmx_invalid_controls(); 4869 report_prefix_pop(); 4870 4871 secondary |= CPU_EPT; 4872 setup_dummy_ept(); 4873 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 4874 test_vmx_valid_controls(); 4875 report_prefix_pop(); 4876 4877 secondary &= ~CPU_PML; 4878 vmcs_write(CPU_EXEC_CTRL1, secondary); 4879 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 4880 test_vmx_valid_controls(); 4881 report_prefix_pop(); 4882 4883 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 4884 PAGE_SIZE, false, false); 4885 4886 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4887 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4888 } 4889 4890 /* 4891 * If the "activate VMX-preemption timer" VM-execution control is 0, the 4892 * the "save VMX-preemption timer value" VM-exit control must also be 0. 4893 * 4894 * [Intel SDM] 4895 */ 4896 static void test_vmx_preemption_timer(void) 4897 { 4898 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4899 u32 saved_exit = vmcs_read(EXI_CONTROLS); 4900 u32 pin = saved_pin; 4901 u32 exit = saved_exit; 4902 4903 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 4904 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 4905 printf("\"Save-VMX-preemption-timer\" control and/or \"Enable-VMX-preemption-timer\" control is not supported\n"); 4906 return; 4907 } 4908 4909 pin |= PIN_PREEMPT; 4910 vmcs_write(PIN_CONTROLS, pin); 4911 exit &= ~EXI_SAVE_PREEMPT; 4912 vmcs_write(EXI_CONTROLS, exit); 4913 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 4914 test_vmx_valid_controls(); 4915 report_prefix_pop(); 4916 4917 exit |= EXI_SAVE_PREEMPT; 4918 vmcs_write(EXI_CONTROLS, exit); 4919 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 4920 test_vmx_valid_controls(); 4921 report_prefix_pop(); 4922 4923 pin &= ~PIN_PREEMPT; 4924 vmcs_write(PIN_CONTROLS, pin); 4925 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 4926 test_vmx_invalid_controls(); 4927 report_prefix_pop(); 4928 4929 exit &= ~EXI_SAVE_PREEMPT; 4930 vmcs_write(EXI_CONTROLS, exit); 4931 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 4932 test_vmx_valid_controls(); 4933 report_prefix_pop(); 4934 4935 vmcs_write(PIN_CONTROLS, saved_pin); 4936 vmcs_write(EXI_CONTROLS, saved_exit); 4937 } 4938 4939 /* 4940 * Tests for VM-execution control fields 4941 */ 4942 static void test_vm_execution_ctls(void) 4943 { 4944 test_pin_based_ctls(); 4945 test_primary_processor_based_ctls(); 4946 test_secondary_processor_based_ctls(); 4947 test_cr3_targets(); 4948 test_io_bitmaps(); 4949 test_msr_bitmap(); 4950 test_apic_ctls(); 4951 test_tpr_threshold(); 4952 test_nmi_ctrls(); 4953 test_pml(); 4954 test_vpid(); 4955 test_ept_eptp(); 4956 test_vmx_preemption_timer(); 4957 } 4958 4959 /* 4960 * The following checks are performed for the VM-entry MSR-load address if 4961 * the VM-entry MSR-load count field is non-zero: 4962 * 4963 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 4964 * The address should not set any bits beyond the processor’s 4965 * physical-address width. 4966 * 4967 * - The address of the last byte in the VM-entry MSR-load area 4968 * should not set any bits beyond the processor’s physical-address 4969 * width. The address of this last byte is VM-entry MSR-load address 4970 * + (MSR count * 16) - 1. (The arithmetic used for the computation 4971 * uses more bits than the processor’s physical-address width.) 4972 * 4973 * 4974 * [Intel SDM] 4975 */ 4976 static void test_entry_msr_load(void) 4977 { 4978 entry_msr_load = alloc_page(); 4979 u64 tmp; 4980 u32 entry_msr_ld_cnt = 1; 4981 int i; 4982 u32 addr_len = 64; 4983 4984 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 4985 4986 /* Check first 4 bits of VM-entry MSR-load address */ 4987 for (i = 0; i < 4; i++) { 4988 tmp = (u64)entry_msr_load | 1ull << i; 4989 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 4990 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 4991 tmp & 0xf); 4992 test_vmx_invalid_controls(); 4993 report_prefix_pop(); 4994 } 4995 4996 if (basic.val & (1ul << 48)) 4997 addr_len = 32; 4998 4999 test_vmcs_addr_values("VM-entry-MSR-load address", 5000 ENTER_MSR_LD_ADDR, 16, false, false, 5001 4, addr_len - 1); 5002 5003 /* 5004 * Check last byte of VM-entry MSR-load address 5005 */ 5006 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 5007 5008 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5009 i < 64; i++) { 5010 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 5011 1ul << i; 5012 vmcs_write(ENTER_MSR_LD_ADDR, 5013 tmp - (entry_msr_ld_cnt * 16 - 1)); 5014 test_vmx_invalid_controls(); 5015 } 5016 5017 vmcs_write(ENT_MSR_LD_CNT, 2); 5018 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5019 test_vmx_invalid_controls(); 5020 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5021 test_vmx_valid_controls(); 5022 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5023 test_vmx_valid_controls(); 5024 } 5025 5026 static void guest_state_test_main(void) 5027 { 5028 while (1) { 5029 if (vmx_get_test_stage() != 2) 5030 vmcall(); 5031 else 5032 break; 5033 } 5034 5035 asm volatile("fnop"); 5036 } 5037 5038 static void advance_guest_state_test(void) 5039 { 5040 u32 reason = vmcs_read(EXI_REASON); 5041 if (! (reason & 0x80000000)) { 5042 u64 guest_rip = vmcs_read(GUEST_RIP); 5043 u32 insn_len = vmcs_read(EXI_INST_LEN); 5044 vmcs_write(GUEST_RIP, guest_rip + insn_len); 5045 } 5046 } 5047 5048 static void report_guest_state_test(const char *test, u32 xreason, 5049 u64 field, const char * field_name) 5050 { 5051 u32 reason = vmcs_read(EXI_REASON); 5052 5053 report("%s, %s %lx", reason == xreason, test, field_name, field); 5054 advance_guest_state_test(); 5055 } 5056 5057 /* 5058 * Tests for VM-entry control fields 5059 */ 5060 static void test_vm_entry_ctls(void) 5061 { 5062 test_invalid_event_injection(); 5063 test_entry_msr_load(); 5064 } 5065 5066 /* 5067 * The following checks are performed for the VM-exit MSR-store address if 5068 * the VM-exit MSR-store count field is non-zero: 5069 * 5070 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 5071 * The address should not set any bits beyond the processor’s 5072 * physical-address width. 5073 * 5074 * - The address of the last byte in the VM-exit MSR-store area 5075 * should not set any bits beyond the processor’s physical-address 5076 * width. The address of this last byte is VM-exit MSR-store address 5077 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5078 * uses more bits than the processor’s physical-address width.) 5079 * 5080 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 5081 * in the range 63:32. 5082 * 5083 * [Intel SDM] 5084 */ 5085 static void test_exit_msr_store(void) 5086 { 5087 exit_msr_store = alloc_page(); 5088 u64 tmp; 5089 u32 exit_msr_st_cnt = 1; 5090 int i; 5091 u32 addr_len = 64; 5092 5093 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 5094 5095 /* Check first 4 bits of VM-exit MSR-store address */ 5096 for (i = 0; i < 4; i++) { 5097 tmp = (u64)exit_msr_store | 1ull << i; 5098 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 5099 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 5100 tmp & 0xf); 5101 test_vmx_invalid_controls(); 5102 report_prefix_pop(); 5103 } 5104 5105 if (basic.val & (1ul << 48)) 5106 addr_len = 32; 5107 5108 test_vmcs_addr_values("VM-exit-MSR-store address", 5109 EXIT_MSR_ST_ADDR, 16, false, false, 5110 4, addr_len - 1); 5111 5112 /* 5113 * Check last byte of VM-exit MSR-store address 5114 */ 5115 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 5116 5117 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5118 i < 64; i++) { 5119 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 5120 1ul << i; 5121 vmcs_write(EXIT_MSR_ST_ADDR, 5122 tmp - (exit_msr_st_cnt * 16 - 1)); 5123 test_vmx_invalid_controls(); 5124 } 5125 5126 vmcs_write(EXI_MSR_ST_CNT, 2); 5127 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5128 test_vmx_invalid_controls(); 5129 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5130 test_vmx_valid_controls(); 5131 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5132 test_vmx_valid_controls(); 5133 } 5134 5135 /* 5136 * Tests for VM-exit controls 5137 */ 5138 static void test_vm_exit_ctls(void) 5139 { 5140 test_exit_msr_store(); 5141 } 5142 5143 /* 5144 * Check that the virtual CPU checks all of the VMX controls as 5145 * documented in the Intel SDM. 5146 */ 5147 static void vmx_controls_test(void) 5148 { 5149 /* 5150 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 5151 * fail due to invalid guest state, should we make it that 5152 * far. 5153 */ 5154 vmcs_write(GUEST_RFLAGS, 0); 5155 5156 test_vm_execution_ctls(); 5157 test_vm_exit_ctls(); 5158 test_vm_entry_ctls(); 5159 } 5160 5161 struct apic_reg_virt_config { 5162 bool apic_register_virtualization; 5163 bool use_tpr_shadow; 5164 bool virtualize_apic_accesses; 5165 bool virtualize_x2apic_mode; 5166 bool activate_secondary_controls; 5167 }; 5168 5169 struct apic_reg_test { 5170 const char *name; 5171 struct apic_reg_virt_config apic_reg_virt_config; 5172 }; 5173 5174 struct apic_reg_virt_expectation { 5175 enum Reason rd_exit_reason; 5176 enum Reason wr_exit_reason; 5177 u32 val; 5178 u32 (*virt_fn)(u32); 5179 5180 /* 5181 * If false, accessing the APIC access address from L2 is treated as a 5182 * normal memory operation, rather than triggering virtualization. 5183 */ 5184 bool virtualize_apic_accesses; 5185 }; 5186 5187 static u32 apic_virt_identity(u32 val) 5188 { 5189 return val; 5190 } 5191 5192 static u32 apic_virt_nibble1(u32 val) 5193 { 5194 return val & 0xf0; 5195 } 5196 5197 static u32 apic_virt_byte3(u32 val) 5198 { 5199 return val & (0xff << 24); 5200 } 5201 5202 static bool apic_reg_virt_exit_expectation( 5203 u32 reg, struct apic_reg_virt_config *config, 5204 struct apic_reg_virt_expectation *expectation) 5205 { 5206 /* Good configs, where some L2 APIC accesses are virtualized. */ 5207 bool virtualize_apic_accesses_only = 5208 config->virtualize_apic_accesses && 5209 !config->use_tpr_shadow && 5210 !config->apic_register_virtualization && 5211 !config->virtualize_x2apic_mode && 5212 config->activate_secondary_controls; 5213 bool virtualize_apic_accesses_and_use_tpr_shadow = 5214 config->virtualize_apic_accesses && 5215 config->use_tpr_shadow && 5216 !config->apic_register_virtualization && 5217 !config->virtualize_x2apic_mode && 5218 config->activate_secondary_controls; 5219 bool apic_register_virtualization = 5220 config->virtualize_apic_accesses && 5221 config->use_tpr_shadow && 5222 config->apic_register_virtualization && 5223 !config->virtualize_x2apic_mode && 5224 config->activate_secondary_controls; 5225 5226 expectation->val = MAGIC_VAL_1; 5227 expectation->virt_fn = apic_virt_identity; 5228 expectation->virtualize_apic_accesses = 5229 config->virtualize_apic_accesses && 5230 config->activate_secondary_controls; 5231 if (virtualize_apic_accesses_only) { 5232 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5233 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5234 } else if (virtualize_apic_accesses_and_use_tpr_shadow) { 5235 switch (reg) { 5236 case APIC_TASKPRI: 5237 expectation->rd_exit_reason = VMX_VMCALL; 5238 expectation->wr_exit_reason = VMX_VMCALL; 5239 expectation->virt_fn = apic_virt_nibble1; 5240 break; 5241 default: 5242 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5243 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5244 } 5245 } else if (apic_register_virtualization) { 5246 expectation->rd_exit_reason = VMX_VMCALL; 5247 5248 switch (reg) { 5249 case APIC_ID: 5250 case APIC_EOI: 5251 case APIC_LDR: 5252 case APIC_DFR: 5253 case APIC_SPIV: 5254 case APIC_ESR: 5255 case APIC_ICR: 5256 case APIC_LVTT: 5257 case APIC_LVTTHMR: 5258 case APIC_LVTPC: 5259 case APIC_LVT0: 5260 case APIC_LVT1: 5261 case APIC_LVTERR: 5262 case APIC_TMICT: 5263 case APIC_TDCR: 5264 expectation->wr_exit_reason = VMX_APIC_WRITE; 5265 break; 5266 case APIC_LVR: 5267 case APIC_ISR ... APIC_ISR + 0x70: 5268 case APIC_TMR ... APIC_TMR + 0x70: 5269 case APIC_IRR ... APIC_IRR + 0x70: 5270 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5271 break; 5272 case APIC_TASKPRI: 5273 expectation->wr_exit_reason = VMX_VMCALL; 5274 expectation->virt_fn = apic_virt_nibble1; 5275 break; 5276 case APIC_ICR2: 5277 expectation->wr_exit_reason = VMX_VMCALL; 5278 expectation->virt_fn = apic_virt_byte3; 5279 break; 5280 default: 5281 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5282 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5283 } 5284 } else if (!expectation->virtualize_apic_accesses) { 5285 /* 5286 * No APIC registers are directly virtualized. This includes 5287 * VTPR, which can be virtualized through MOV to/from CR8 via 5288 * the use TPR shadow control, but not through directly 5289 * accessing VTPR. 5290 */ 5291 expectation->rd_exit_reason = VMX_VMCALL; 5292 expectation->wr_exit_reason = VMX_VMCALL; 5293 } else { 5294 printf("Cannot parse APIC register virtualization config:\n" 5295 "\tvirtualize_apic_accesses: %d\n" 5296 "\tuse_tpr_shadow: %d\n" 5297 "\tapic_register_virtualization: %d\n" 5298 "\tvirtualize_x2apic_mode: %d\n" 5299 "\tactivate_secondary_controls: %d\n", 5300 config->virtualize_apic_accesses, 5301 config->use_tpr_shadow, 5302 config->apic_register_virtualization, 5303 config->virtualize_x2apic_mode, 5304 config->activate_secondary_controls); 5305 5306 return false; 5307 } 5308 5309 return true; 5310 } 5311 5312 struct apic_reg_test apic_reg_tests[] = { 5313 /* Good configs, where some L2 APIC accesses are virtualized. */ 5314 { 5315 .name = "Virtualize APIC accesses", 5316 .apic_reg_virt_config = { 5317 .virtualize_apic_accesses = true, 5318 .use_tpr_shadow = false, 5319 .apic_register_virtualization = false, 5320 .virtualize_x2apic_mode = false, 5321 .activate_secondary_controls = true, 5322 }, 5323 }, 5324 { 5325 .name = "Virtualize APIC accesses + Use TPR shadow", 5326 .apic_reg_virt_config = { 5327 .virtualize_apic_accesses = true, 5328 .use_tpr_shadow = true, 5329 .apic_register_virtualization = false, 5330 .virtualize_x2apic_mode = false, 5331 .activate_secondary_controls = true, 5332 }, 5333 }, 5334 { 5335 .name = "APIC-register virtualization", 5336 .apic_reg_virt_config = { 5337 .virtualize_apic_accesses = true, 5338 .use_tpr_shadow = true, 5339 .apic_register_virtualization = true, 5340 .virtualize_x2apic_mode = false, 5341 .activate_secondary_controls = true, 5342 }, 5343 }, 5344 5345 /* 5346 * Test that the secondary processor-based VM-execution controls are 5347 * correctly ignored when "activate secondary controls" is disabled. 5348 */ 5349 { 5350 .name = "Activate secondary controls off", 5351 .apic_reg_virt_config = { 5352 .virtualize_apic_accesses = true, 5353 .use_tpr_shadow = false, 5354 .apic_register_virtualization = true, 5355 .virtualize_x2apic_mode = true, 5356 .activate_secondary_controls = false, 5357 }, 5358 }, 5359 { 5360 .name = "Activate secondary controls off + Use TPR shadow", 5361 .apic_reg_virt_config = { 5362 .virtualize_apic_accesses = true, 5363 .use_tpr_shadow = true, 5364 .apic_register_virtualization = true, 5365 .virtualize_x2apic_mode = true, 5366 .activate_secondary_controls = false, 5367 }, 5368 }, 5369 5370 /* 5371 * Test that the APIC access address is treated like an arbitrary memory 5372 * address when "virtualize APIC accesses" is disabled. 5373 */ 5374 { 5375 .name = "Virtualize APIC accesses off + Use TPR shadow", 5376 .apic_reg_virt_config = { 5377 .virtualize_apic_accesses = false, 5378 .use_tpr_shadow = true, 5379 .apic_register_virtualization = true, 5380 .virtualize_x2apic_mode = true, 5381 .activate_secondary_controls = true, 5382 }, 5383 }, 5384 5385 /* 5386 * Test that VM entry fails due to invalid controls when 5387 * "APIC-register virtualization" is enabled while "use TPR shadow" is 5388 * disabled. 5389 */ 5390 { 5391 .name = "APIC-register virtualization + Use TPR shadow off", 5392 .apic_reg_virt_config = { 5393 .virtualize_apic_accesses = true, 5394 .use_tpr_shadow = false, 5395 .apic_register_virtualization = true, 5396 .virtualize_x2apic_mode = false, 5397 .activate_secondary_controls = true, 5398 }, 5399 }, 5400 5401 /* 5402 * Test that VM entry fails due to invalid controls when 5403 * "Virtualize x2APIC mode" is enabled while "use TPR shadow" is 5404 * disabled. 5405 */ 5406 { 5407 .name = "Virtualize x2APIC mode + Use TPR shadow off", 5408 .apic_reg_virt_config = { 5409 .virtualize_apic_accesses = false, 5410 .use_tpr_shadow = false, 5411 .apic_register_virtualization = false, 5412 .virtualize_x2apic_mode = true, 5413 .activate_secondary_controls = true, 5414 }, 5415 }, 5416 { 5417 .name = "Virtualize x2APIC mode + Use TPR shadow off v2", 5418 .apic_reg_virt_config = { 5419 .virtualize_apic_accesses = false, 5420 .use_tpr_shadow = false, 5421 .apic_register_virtualization = true, 5422 .virtualize_x2apic_mode = true, 5423 .activate_secondary_controls = true, 5424 }, 5425 }, 5426 5427 /* 5428 * Test that VM entry fails due to invalid controls when 5429 * "virtualize x2APIC mode" is enabled while "virtualize APIC accesses" 5430 * is enabled. 5431 */ 5432 { 5433 .name = "Virtualize x2APIC mode + Virtualize APIC accesses", 5434 .apic_reg_virt_config = { 5435 .virtualize_apic_accesses = true, 5436 .use_tpr_shadow = true, 5437 .apic_register_virtualization = false, 5438 .virtualize_x2apic_mode = true, 5439 .activate_secondary_controls = true, 5440 }, 5441 }, 5442 { 5443 .name = "Virtualize x2APIC mode + Virtualize APIC accesses v2", 5444 .apic_reg_virt_config = { 5445 .virtualize_apic_accesses = true, 5446 .use_tpr_shadow = true, 5447 .apic_register_virtualization = true, 5448 .virtualize_x2apic_mode = true, 5449 .activate_secondary_controls = true, 5450 }, 5451 }, 5452 }; 5453 5454 enum Apic_op { 5455 APIC_OP_XAPIC_RD, 5456 APIC_OP_XAPIC_WR, 5457 TERMINATE, 5458 }; 5459 5460 static u32 vmx_xapic_read(u32 *apic_access_address, u32 reg) 5461 { 5462 return *(volatile u32 *)((uintptr_t)apic_access_address + reg); 5463 } 5464 5465 static void vmx_xapic_write(u32 *apic_access_address, u32 reg, u32 val) 5466 { 5467 *(volatile u32 *)((uintptr_t)apic_access_address + reg) = val; 5468 } 5469 5470 struct apic_reg_virt_guest_args { 5471 enum Apic_op op; 5472 u32 *apic_access_address; 5473 u32 reg; 5474 u32 val; 5475 bool check_rd; 5476 u32 (*virt_fn)(u32); 5477 } apic_reg_virt_guest_args; 5478 5479 static void apic_reg_virt_guest(void) 5480 { 5481 volatile struct apic_reg_virt_guest_args *args = 5482 &apic_reg_virt_guest_args; 5483 5484 for (;;) { 5485 enum Apic_op op = args->op; 5486 u32 *apic_access_address = args->apic_access_address; 5487 u32 reg = args->reg; 5488 u32 val = args->val; 5489 bool check_rd = args->check_rd; 5490 u32 (*virt_fn)(u32) = args->virt_fn; 5491 5492 if (op == TERMINATE) 5493 break; 5494 5495 if (op == APIC_OP_XAPIC_RD) { 5496 u32 ret = vmx_xapic_read(apic_access_address, reg); 5497 5498 if (check_rd) { 5499 u32 want = virt_fn(val); 5500 u32 got = virt_fn(ret); 5501 5502 report("read 0x%x, expected 0x%x.", 5503 got == want, got, want); 5504 } 5505 } else if (op == APIC_OP_XAPIC_WR) { 5506 vmx_xapic_write(apic_access_address, reg, val); 5507 } 5508 5509 /* 5510 * The L1 should always execute a vmcall after it's done testing 5511 * an individual APIC operation. This helps to validate that the 5512 * L1 and L2 are in sync with each other, as expected. 5513 */ 5514 vmcall(); 5515 } 5516 } 5517 5518 static void test_xapic_rd( 5519 u32 reg, struct apic_reg_virt_expectation *expectation, 5520 u32 *apic_access_address, u32 *virtual_apic_page) 5521 { 5522 u32 val = expectation->val; 5523 u32 exit_reason_want = expectation->rd_exit_reason; 5524 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5525 5526 report_prefix_pushf("xapic - reading 0x%03x", reg); 5527 5528 /* Configure guest to do an xapic read */ 5529 args->op = APIC_OP_XAPIC_RD; 5530 args->apic_access_address = apic_access_address; 5531 args->reg = reg; 5532 args->val = val; 5533 args->check_rd = exit_reason_want == VMX_VMCALL; 5534 args->virt_fn = expectation->virt_fn; 5535 5536 /* Setup virtual APIC page */ 5537 if (!expectation->virtualize_apic_accesses) { 5538 apic_access_address[apic_reg_index(reg)] = val; 5539 virtual_apic_page[apic_reg_index(reg)] = 0; 5540 } else if (exit_reason_want == VMX_VMCALL) { 5541 apic_access_address[apic_reg_index(reg)] = 0; 5542 virtual_apic_page[apic_reg_index(reg)] = val; 5543 } 5544 5545 /* Enter guest */ 5546 enter_guest(); 5547 5548 /* 5549 * Validate the behavior and 5550 * pass a magic value back to the guest. 5551 */ 5552 if (exit_reason_want == VMX_APIC_ACCESS) { 5553 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5554 5555 assert_exit_reason(exit_reason_want); 5556 report("got APIC access exit @ page offset 0x%03x, want 0x%03x", 5557 apic_page_offset == reg, apic_page_offset, reg); 5558 skip_exit_insn(); 5559 5560 /* Reenter guest so it can consume/check rcx and exit again. */ 5561 enter_guest(); 5562 } else if (exit_reason_want != VMX_VMCALL) { 5563 report("Oops, bad exit expectation: %u.", false, 5564 exit_reason_want); 5565 } 5566 5567 skip_exit_vmcall(); 5568 report_prefix_pop(); 5569 } 5570 5571 static void test_xapic_wr( 5572 u32 reg, struct apic_reg_virt_expectation *expectation, 5573 u32 *apic_access_address, u32 *virtual_apic_page) 5574 { 5575 u32 val = expectation->val; 5576 u32 exit_reason_want = expectation->wr_exit_reason; 5577 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5578 bool virtualized = 5579 expectation->virtualize_apic_accesses && 5580 (exit_reason_want == VMX_APIC_WRITE || 5581 exit_reason_want == VMX_VMCALL); 5582 bool checked = false; 5583 5584 report_prefix_pushf("xapic - writing 0x%x to 0x%03x", val, reg); 5585 5586 /* Configure guest to do an xapic read */ 5587 args->op = APIC_OP_XAPIC_WR; 5588 args->apic_access_address = apic_access_address; 5589 args->reg = reg; 5590 args->val = val; 5591 5592 /* Setup virtual APIC page */ 5593 if (virtualized || !expectation->virtualize_apic_accesses) { 5594 apic_access_address[apic_reg_index(reg)] = 0; 5595 virtual_apic_page[apic_reg_index(reg)] = 0; 5596 } 5597 5598 /* Enter guest */ 5599 enter_guest(); 5600 5601 /* 5602 * Validate the behavior and 5603 * pass a magic value back to the guest. 5604 */ 5605 if (exit_reason_want == VMX_APIC_ACCESS) { 5606 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5607 5608 assert_exit_reason(exit_reason_want); 5609 report("got APIC access exit @ page offset 0x%03x, want 0x%03x", 5610 apic_page_offset == reg, apic_page_offset, reg); 5611 skip_exit_insn(); 5612 5613 /* Reenter guest so it can consume/check rcx and exit again. */ 5614 enter_guest(); 5615 } else if (exit_reason_want == VMX_APIC_WRITE) { 5616 assert_exit_reason(exit_reason_want); 5617 report("got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%x", 5618 virtual_apic_page[apic_reg_index(reg)] == val, 5619 apic_reg_index(reg), 5620 virtual_apic_page[apic_reg_index(reg)], val); 5621 checked = true; 5622 5623 /* Reenter guest so it can consume/check rcx and exit again. */ 5624 enter_guest(); 5625 } else if (exit_reason_want != VMX_VMCALL) { 5626 report("Oops, bad exit expectation: %u.", false, 5627 exit_reason_want); 5628 } 5629 5630 assert_exit_reason(VMX_VMCALL); 5631 if (virtualized && !checked) { 5632 u32 want = expectation->virt_fn(val); 5633 u32 got = virtual_apic_page[apic_reg_index(reg)]; 5634 got = expectation->virt_fn(got); 5635 5636 report("exitless write; val is 0x%x, want 0x%x", 5637 got == want, got, want); 5638 } else if (!expectation->virtualize_apic_accesses && !checked) { 5639 u32 got = apic_access_address[apic_reg_index(reg)]; 5640 5641 report("non-virtualized write; val is 0x%x, want 0x%x", 5642 got == val, got, val); 5643 } else if (!expectation->virtualize_apic_accesses && checked) { 5644 report("Non-virtualized write was prematurely checked!", false); 5645 } 5646 5647 skip_exit_vmcall(); 5648 report_prefix_pop(); 5649 } 5650 5651 enum Config_type { 5652 CONFIG_TYPE_GOOD, 5653 CONFIG_TYPE_UNSUPPORTED, 5654 CONFIG_TYPE_VMENTRY_FAILS_EARLY, 5655 }; 5656 5657 static enum Config_type configure_apic_reg_virt_test( 5658 struct apic_reg_virt_config *apic_reg_virt_config) 5659 { 5660 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5661 u32 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 5662 /* Configs where L2 entry fails early, due to invalid controls. */ 5663 bool use_tpr_shadow_incorrectly_off = 5664 !apic_reg_virt_config->use_tpr_shadow && 5665 (apic_reg_virt_config->apic_register_virtualization || 5666 apic_reg_virt_config->virtualize_x2apic_mode) && 5667 apic_reg_virt_config->activate_secondary_controls; 5668 bool virtualize_apic_accesses_incorrectly_on = 5669 apic_reg_virt_config->virtualize_apic_accesses && 5670 apic_reg_virt_config->virtualize_x2apic_mode && 5671 apic_reg_virt_config->activate_secondary_controls; 5672 bool vmentry_fails_early = 5673 use_tpr_shadow_incorrectly_off || 5674 virtualize_apic_accesses_incorrectly_on; 5675 5676 if (apic_reg_virt_config->activate_secondary_controls) { 5677 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 5678 printf("VM-execution control \"activate secondary controls\" NOT supported.\n"); 5679 return CONFIG_TYPE_UNSUPPORTED; 5680 } 5681 cpu_exec_ctrl0 |= CPU_SECONDARY; 5682 } else { 5683 cpu_exec_ctrl0 &= ~CPU_SECONDARY; 5684 } 5685 5686 if (apic_reg_virt_config->virtualize_apic_accesses) { 5687 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES)) { 5688 printf("VM-execution control \"virtualize APIC accesses\" NOT supported.\n"); 5689 return CONFIG_TYPE_UNSUPPORTED; 5690 } 5691 cpu_exec_ctrl1 |= CPU_VIRT_APIC_ACCESSES; 5692 } else { 5693 cpu_exec_ctrl1 &= ~CPU_VIRT_APIC_ACCESSES; 5694 } 5695 5696 if (apic_reg_virt_config->use_tpr_shadow) { 5697 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 5698 printf("VM-execution control \"use TPR shadow\" NOT supported.\n"); 5699 return CONFIG_TYPE_UNSUPPORTED; 5700 } 5701 cpu_exec_ctrl0 |= CPU_TPR_SHADOW; 5702 } else { 5703 cpu_exec_ctrl0 &= ~CPU_TPR_SHADOW; 5704 } 5705 5706 if (apic_reg_virt_config->apic_register_virtualization) { 5707 if (!(ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT)) { 5708 printf("VM-execution control \"APIC-register virtualization\" NOT supported.\n"); 5709 return CONFIG_TYPE_UNSUPPORTED; 5710 } 5711 cpu_exec_ctrl1 |= CPU_APIC_REG_VIRT; 5712 } else { 5713 cpu_exec_ctrl1 &= ~CPU_APIC_REG_VIRT; 5714 } 5715 5716 if (apic_reg_virt_config->virtualize_x2apic_mode) { 5717 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_X2APIC)) { 5718 printf("VM-execution control \"virtualize x2APIC mode\" NOT supported.\n"); 5719 return CONFIG_TYPE_UNSUPPORTED; 5720 } 5721 cpu_exec_ctrl1 |= CPU_VIRT_X2APIC; 5722 } else { 5723 cpu_exec_ctrl1 &= ~CPU_VIRT_X2APIC; 5724 } 5725 5726 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 5727 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 5728 5729 if (vmentry_fails_early) 5730 return CONFIG_TYPE_VMENTRY_FAILS_EARLY; 5731 5732 return CONFIG_TYPE_GOOD; 5733 } 5734 5735 static bool cpu_has_apicv(void) 5736 { 5737 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 5738 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 5739 (ctrl_pin_rev.clr & PIN_POST_INTR)); 5740 } 5741 5742 /* Validates APIC register access across valid virtualization configurations. */ 5743 static void apic_reg_virt_test(void) 5744 { 5745 u32 *apic_access_address; 5746 u32 *virtual_apic_page; 5747 u64 control; 5748 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5749 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 5750 int i; 5751 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5752 5753 if (!cpu_has_apicv()) { 5754 report_skip(__func__); 5755 return; 5756 } 5757 5758 control = cpu_exec_ctrl1; 5759 control &= ~CPU_VINTD; 5760 vmcs_write(CPU_EXEC_CTRL1, control); 5761 5762 test_set_guest(apic_reg_virt_guest); 5763 5764 /* 5765 * From the SDM: The 1-setting of the "virtualize APIC accesses" 5766 * VM-execution is guaranteed to apply only if translations to the 5767 * APIC-access address use a 4-KByte page. 5768 */ 5769 apic_access_address = alloc_page(); 5770 force_4k_page(apic_access_address); 5771 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_address)); 5772 5773 virtual_apic_page = alloc_page(); 5774 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 5775 5776 for (i = 0; i < ARRAY_SIZE(apic_reg_tests); i++) { 5777 struct apic_reg_test *apic_reg_test = &apic_reg_tests[i]; 5778 struct apic_reg_virt_config *apic_reg_virt_config = 5779 &apic_reg_test->apic_reg_virt_config; 5780 enum Config_type config_type; 5781 u32 reg; 5782 5783 printf("--- %s test ---\n", apic_reg_test->name); 5784 config_type = 5785 configure_apic_reg_virt_test(apic_reg_virt_config); 5786 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 5787 printf("Skip because of missing features.\n"); 5788 continue; 5789 } 5790 5791 if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 5792 enter_guest_with_bad_controls(); 5793 continue; 5794 } 5795 5796 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 5797 struct apic_reg_virt_expectation expectation = {}; 5798 bool ok; 5799 5800 ok = apic_reg_virt_exit_expectation( 5801 reg, apic_reg_virt_config, &expectation); 5802 if (!ok) { 5803 report("Malformed test.", false); 5804 break; 5805 } 5806 5807 test_xapic_rd(reg, &expectation, apic_access_address, 5808 virtual_apic_page); 5809 test_xapic_wr(reg, &expectation, apic_access_address, 5810 virtual_apic_page); 5811 } 5812 } 5813 5814 /* Terminate the guest */ 5815 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 5816 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 5817 args->op = TERMINATE; 5818 enter_guest(); 5819 assert_exit_reason(VMX_VMCALL); 5820 } 5821 5822 struct virt_x2apic_mode_config { 5823 struct apic_reg_virt_config apic_reg_virt_config; 5824 bool virtual_interrupt_delivery; 5825 bool use_msr_bitmaps; 5826 bool disable_x2apic_msr_intercepts; 5827 bool disable_x2apic; 5828 }; 5829 5830 struct virt_x2apic_mode_test_case { 5831 const char *name; 5832 struct virt_x2apic_mode_config virt_x2apic_mode_config; 5833 }; 5834 5835 enum Virt_x2apic_mode_behavior_type { 5836 X2APIC_ACCESS_VIRTUALIZED, 5837 X2APIC_ACCESS_PASSED_THROUGH, 5838 X2APIC_ACCESS_TRIGGERS_GP, 5839 }; 5840 5841 struct virt_x2apic_mode_expectation { 5842 enum Reason rd_exit_reason; 5843 enum Reason wr_exit_reason; 5844 5845 /* 5846 * RDMSR and WRMSR handle 64-bit values. However, except for ICR, all of 5847 * the x2APIC registers are 32 bits. Notice: 5848 * 1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers. 5849 * 2. vmx_x2apic_write() expects the val arg to be well-formed. 5850 */ 5851 u64 rd_val; 5852 u64 wr_val; 5853 5854 /* 5855 * Compares input to virtualized output; 5856 * 1st arg is pointer to return expected virtualization output. 5857 */ 5858 u64 (*virt_fn)(u64); 5859 5860 enum Virt_x2apic_mode_behavior_type rd_behavior; 5861 enum Virt_x2apic_mode_behavior_type wr_behavior; 5862 bool wr_only; 5863 }; 5864 5865 static u64 virt_x2apic_mode_identity(u64 val) 5866 { 5867 return val; 5868 } 5869 5870 static u64 virt_x2apic_mode_nibble1(u64 val) 5871 { 5872 return val & 0xf0; 5873 } 5874 5875 static bool is_cmci_enabled(void) 5876 { 5877 return rdmsr(MSR_IA32_MCG_CAP) & BIT_ULL(10); 5878 } 5879 5880 static void virt_x2apic_mode_rd_expectation( 5881 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 5882 bool apic_register_virtualization, bool virtual_interrupt_delivery, 5883 struct virt_x2apic_mode_expectation *expectation) 5884 { 5885 bool readable = 5886 !x2apic_reg_reserved(reg) && 5887 reg != APIC_EOI; 5888 5889 if (reg == APIC_CMCI && !is_cmci_enabled()) 5890 readable = false; 5891 5892 expectation->rd_exit_reason = VMX_VMCALL; 5893 expectation->virt_fn = virt_x2apic_mode_identity; 5894 if (virt_x2apic_mode_on && apic_register_virtualization) { 5895 expectation->rd_val = MAGIC_VAL_1; 5896 if (reg == APIC_PROCPRI && virtual_interrupt_delivery) 5897 expectation->virt_fn = virt_x2apic_mode_nibble1; 5898 else if (reg == APIC_TASKPRI) 5899 expectation->virt_fn = virt_x2apic_mode_nibble1; 5900 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 5901 } else if (virt_x2apic_mode_on && !apic_register_virtualization && 5902 reg == APIC_TASKPRI) { 5903 expectation->rd_val = MAGIC_VAL_1; 5904 expectation->virt_fn = virt_x2apic_mode_nibble1; 5905 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 5906 } else if (!disable_x2apic && readable) { 5907 expectation->rd_val = apic_read(reg); 5908 expectation->rd_behavior = X2APIC_ACCESS_PASSED_THROUGH; 5909 } else { 5910 expectation->rd_behavior = X2APIC_ACCESS_TRIGGERS_GP; 5911 } 5912 } 5913 5914 /* 5915 * get_x2apic_wr_val() creates an innocuous write value for an x2APIC register. 5916 * 5917 * For writable registers, get_x2apic_wr_val() deposits the write value into the 5918 * val pointer arg and returns true. For non-writable registers, val is not 5919 * modified and get_x2apic_wr_val() returns false. 5920 */ 5921 static bool get_x2apic_wr_val(u32 reg, u64 *val) 5922 { 5923 switch (reg) { 5924 case APIC_TASKPRI: 5925 /* Bits 31:8 are reserved. */ 5926 *val &= 0xff; 5927 break; 5928 case APIC_EOI: 5929 case APIC_ESR: 5930 case APIC_TMICT: 5931 /* 5932 * EOI, ESR: WRMSR of a non-zero value causes #GP(0). 5933 * TMICT: A write of 0 to the initial-count register effectively 5934 * stops the local APIC timer, in both one-shot and 5935 * periodic mode. 5936 */ 5937 *val = 0; 5938 break; 5939 case APIC_SPIV: 5940 case APIC_LVTT: 5941 case APIC_LVTTHMR: 5942 case APIC_LVTPC: 5943 case APIC_LVT0: 5944 case APIC_LVT1: 5945 case APIC_LVTERR: 5946 case APIC_TDCR: 5947 /* 5948 * To avoid writing a 1 to a reserved bit or causing some other 5949 * unintended side effect, read the current value and use it as 5950 * the write value. 5951 */ 5952 *val = apic_read(reg); 5953 break; 5954 case APIC_CMCI: 5955 if (!is_cmci_enabled()) 5956 return false; 5957 *val = apic_read(reg); 5958 break; 5959 case APIC_ICR: 5960 *val = 0x40000 | 0xf1; 5961 break; 5962 case APIC_SELF_IPI: 5963 /* 5964 * With special processing (i.e., virtualize x2APIC mode + 5965 * virtual interrupt delivery), writing zero causes an 5966 * APIC-write VM exit. We plan to add a test for enabling 5967 * "virtual-interrupt delivery" in VMCS12, and that's where we 5968 * will test a self IPI with special processing. 5969 */ 5970 *val = 0x0; 5971 break; 5972 default: 5973 return false; 5974 } 5975 5976 return true; 5977 } 5978 5979 static bool special_processing_applies(u32 reg, u64 *val, 5980 bool virt_int_delivery) 5981 { 5982 bool special_processing = 5983 (reg == APIC_TASKPRI) || 5984 (virt_int_delivery && 5985 (reg == APIC_EOI || reg == APIC_SELF_IPI)); 5986 5987 if (special_processing) { 5988 TEST_ASSERT(get_x2apic_wr_val(reg, val)); 5989 return true; 5990 } 5991 5992 return false; 5993 } 5994 5995 static void virt_x2apic_mode_wr_expectation( 5996 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 5997 bool virt_int_delivery, 5998 struct virt_x2apic_mode_expectation *expectation) 5999 { 6000 expectation->wr_exit_reason = VMX_VMCALL; 6001 expectation->wr_val = MAGIC_VAL_1; 6002 expectation->wr_only = false; 6003 6004 if (virt_x2apic_mode_on && 6005 special_processing_applies(reg, &expectation->wr_val, 6006 virt_int_delivery)) { 6007 expectation->wr_behavior = X2APIC_ACCESS_VIRTUALIZED; 6008 if (reg == APIC_SELF_IPI) 6009 expectation->wr_exit_reason = VMX_APIC_WRITE; 6010 } else if (!disable_x2apic && 6011 get_x2apic_wr_val(reg, &expectation->wr_val)) { 6012 expectation->wr_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6013 if (reg == APIC_EOI || reg == APIC_SELF_IPI) 6014 expectation->wr_only = true; 6015 if (reg == APIC_ICR) 6016 expectation->wr_exit_reason = VMX_EXTINT; 6017 } else { 6018 expectation->wr_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6019 /* 6020 * Writing 1 to a reserved bit triggers a #GP. 6021 * Thus, set the write value to 0, which seems 6022 * the most likely to detect a missed #GP. 6023 */ 6024 expectation->wr_val = 0; 6025 } 6026 } 6027 6028 static void virt_x2apic_mode_exit_expectation( 6029 u32 reg, struct virt_x2apic_mode_config *config, 6030 struct virt_x2apic_mode_expectation *expectation) 6031 { 6032 struct apic_reg_virt_config *base_config = 6033 &config->apic_reg_virt_config; 6034 bool virt_x2apic_mode_on = 6035 base_config->virtualize_x2apic_mode && 6036 config->use_msr_bitmaps && 6037 config->disable_x2apic_msr_intercepts && 6038 base_config->activate_secondary_controls; 6039 6040 virt_x2apic_mode_wr_expectation( 6041 reg, virt_x2apic_mode_on, config->disable_x2apic, 6042 config->virtual_interrupt_delivery, expectation); 6043 virt_x2apic_mode_rd_expectation( 6044 reg, virt_x2apic_mode_on, config->disable_x2apic, 6045 base_config->apic_register_virtualization, 6046 config->virtual_interrupt_delivery, expectation); 6047 } 6048 6049 struct virt_x2apic_mode_test_case virt_x2apic_mode_tests[] = { 6050 /* 6051 * Baseline "virtualize x2APIC mode" configuration: 6052 * - virtualize x2APIC mode 6053 * - virtual-interrupt delivery 6054 * - APIC-register virtualization 6055 * - x2APIC MSR intercepts disabled 6056 * 6057 * Reads come from virtual APIC page, special processing applies to 6058 * VTPR, EOI, and SELF IPI, and all other writes pass through to L1 6059 * APIC. 6060 */ 6061 { 6062 .name = "Baseline", 6063 .virt_x2apic_mode_config = { 6064 .virtual_interrupt_delivery = true, 6065 .use_msr_bitmaps = true, 6066 .disable_x2apic_msr_intercepts = true, 6067 .disable_x2apic = false, 6068 .apic_reg_virt_config = { 6069 .apic_register_virtualization = true, 6070 .use_tpr_shadow = true, 6071 .virtualize_apic_accesses = false, 6072 .virtualize_x2apic_mode = true, 6073 .activate_secondary_controls = true, 6074 }, 6075 }, 6076 }, 6077 { 6078 .name = "Baseline w/ x2apic disabled", 6079 .virt_x2apic_mode_config = { 6080 .virtual_interrupt_delivery = true, 6081 .use_msr_bitmaps = true, 6082 .disable_x2apic_msr_intercepts = true, 6083 .disable_x2apic = true, 6084 .apic_reg_virt_config = { 6085 .apic_register_virtualization = true, 6086 .use_tpr_shadow = true, 6087 .virtualize_apic_accesses = false, 6088 .virtualize_x2apic_mode = true, 6089 .activate_secondary_controls = true, 6090 }, 6091 }, 6092 }, 6093 6094 /* 6095 * Baseline, minus virtual-interrupt delivery. Reads come from virtual 6096 * APIC page, special processing applies to VTPR, and all other writes 6097 * pass through to L1 APIC. 6098 */ 6099 { 6100 .name = "Baseline - virtual interrupt delivery", 6101 .virt_x2apic_mode_config = { 6102 .virtual_interrupt_delivery = false, 6103 .use_msr_bitmaps = true, 6104 .disable_x2apic_msr_intercepts = true, 6105 .disable_x2apic = false, 6106 .apic_reg_virt_config = { 6107 .apic_register_virtualization = true, 6108 .use_tpr_shadow = true, 6109 .virtualize_apic_accesses = false, 6110 .virtualize_x2apic_mode = true, 6111 .activate_secondary_controls = true, 6112 }, 6113 }, 6114 }, 6115 6116 /* 6117 * Baseline, minus APIC-register virtualization. x2APIC reads pass 6118 * through to L1's APIC, unless reading VTPR 6119 */ 6120 { 6121 .name = "Virtualize x2APIC mode, no APIC reg virt", 6122 .virt_x2apic_mode_config = { 6123 .virtual_interrupt_delivery = true, 6124 .use_msr_bitmaps = true, 6125 .disable_x2apic_msr_intercepts = true, 6126 .disable_x2apic = false, 6127 .apic_reg_virt_config = { 6128 .apic_register_virtualization = false, 6129 .use_tpr_shadow = true, 6130 .virtualize_apic_accesses = false, 6131 .virtualize_x2apic_mode = true, 6132 .activate_secondary_controls = true, 6133 }, 6134 }, 6135 }, 6136 { 6137 .name = "Virtualize x2APIC mode, no APIC reg virt, x2APIC off", 6138 .virt_x2apic_mode_config = { 6139 .virtual_interrupt_delivery = true, 6140 .use_msr_bitmaps = true, 6141 .disable_x2apic_msr_intercepts = true, 6142 .disable_x2apic = true, 6143 .apic_reg_virt_config = { 6144 .apic_register_virtualization = false, 6145 .use_tpr_shadow = true, 6146 .virtualize_apic_accesses = false, 6147 .virtualize_x2apic_mode = true, 6148 .activate_secondary_controls = true, 6149 }, 6150 }, 6151 }, 6152 6153 /* 6154 * Enable "virtualize x2APIC mode" and "APIC-register virtualization", 6155 * and disable intercepts for the x2APIC MSRs, but fail to enable 6156 * "activate secondary controls" (i.e. L2 gets access to L1's x2APIC 6157 * MSRs). 6158 */ 6159 { 6160 .name = "Fail to enable activate secondary controls", 6161 .virt_x2apic_mode_config = { 6162 .virtual_interrupt_delivery = true, 6163 .use_msr_bitmaps = true, 6164 .disable_x2apic_msr_intercepts = true, 6165 .disable_x2apic = false, 6166 .apic_reg_virt_config = { 6167 .apic_register_virtualization = true, 6168 .use_tpr_shadow = true, 6169 .virtualize_apic_accesses = false, 6170 .virtualize_x2apic_mode = true, 6171 .activate_secondary_controls = false, 6172 }, 6173 }, 6174 }, 6175 6176 /* 6177 * Enable "APIC-register virtualization" and enable "activate secondary 6178 * controls" and disable intercepts for the x2APIC MSRs, but do not 6179 * enable the "virtualize x2APIC mode" VM-execution control (i.e. L2 6180 * gets access to L1's x2APIC MSRs). 6181 */ 6182 { 6183 .name = "Fail to enable virtualize x2APIC mode", 6184 .virt_x2apic_mode_config = { 6185 .virtual_interrupt_delivery = true, 6186 .use_msr_bitmaps = true, 6187 .disable_x2apic_msr_intercepts = true, 6188 .disable_x2apic = false, 6189 .apic_reg_virt_config = { 6190 .apic_register_virtualization = true, 6191 .use_tpr_shadow = true, 6192 .virtualize_apic_accesses = false, 6193 .virtualize_x2apic_mode = false, 6194 .activate_secondary_controls = true, 6195 }, 6196 }, 6197 }, 6198 6199 /* 6200 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and 6201 * enable "APIC-register virtualization" --> L2 gets L1's x2APIC MSRs. 6202 */ 6203 { 6204 .name = "Baseline", 6205 .virt_x2apic_mode_config = { 6206 .virtual_interrupt_delivery = true, 6207 .use_msr_bitmaps = true, 6208 .disable_x2apic_msr_intercepts = true, 6209 .disable_x2apic = false, 6210 .apic_reg_virt_config = { 6211 .apic_register_virtualization = true, 6212 .use_tpr_shadow = true, 6213 .virtualize_apic_accesses = false, 6214 .virtualize_x2apic_mode = false, 6215 .activate_secondary_controls = true, 6216 }, 6217 }, 6218 }, 6219 }; 6220 6221 enum X2apic_op { 6222 X2APIC_OP_RD, 6223 X2APIC_OP_WR, 6224 X2APIC_TERMINATE, 6225 }; 6226 6227 static u64 vmx_x2apic_read(u32 reg) 6228 { 6229 u32 msr_addr = x2apic_msr(reg); 6230 u64 val; 6231 6232 val = rdmsr(msr_addr); 6233 6234 return val; 6235 } 6236 6237 static void vmx_x2apic_write(u32 reg, u64 val) 6238 { 6239 u32 msr_addr = x2apic_msr(reg); 6240 6241 wrmsr(msr_addr, val); 6242 } 6243 6244 struct virt_x2apic_mode_guest_args { 6245 enum X2apic_op op; 6246 u32 reg; 6247 u64 val; 6248 bool should_gp; 6249 u64 (*virt_fn)(u64); 6250 } virt_x2apic_mode_guest_args; 6251 6252 static volatile bool handle_x2apic_gp_ran; 6253 static volatile u32 handle_x2apic_gp_insn_len; 6254 static void handle_x2apic_gp(struct ex_regs *regs) 6255 { 6256 handle_x2apic_gp_ran = true; 6257 regs->rip += handle_x2apic_gp_insn_len; 6258 } 6259 6260 static handler setup_x2apic_gp_handler(void) 6261 { 6262 handler old_handler; 6263 6264 old_handler = handle_exception(GP_VECTOR, handle_x2apic_gp); 6265 /* RDMSR and WRMSR are both 2 bytes, assuming no prefixes. */ 6266 handle_x2apic_gp_insn_len = 2; 6267 6268 return old_handler; 6269 } 6270 6271 static void teardown_x2apic_gp_handler(handler old_handler) 6272 { 6273 handle_exception(GP_VECTOR, old_handler); 6274 6275 /* 6276 * Defensively reset instruction length, so that if the handler is 6277 * incorrectly used, it will loop infinitely, rather than run off into 6278 * la la land. 6279 */ 6280 handle_x2apic_gp_insn_len = 0; 6281 handle_x2apic_gp_ran = false; 6282 } 6283 6284 static void virt_x2apic_mode_guest(void) 6285 { 6286 volatile struct virt_x2apic_mode_guest_args *args = 6287 &virt_x2apic_mode_guest_args; 6288 6289 for (;;) { 6290 enum X2apic_op op = args->op; 6291 u32 reg = args->reg; 6292 u64 val = args->val; 6293 bool should_gp = args->should_gp; 6294 u64 (*virt_fn)(u64) = args->virt_fn; 6295 handler old_handler; 6296 6297 if (op == X2APIC_TERMINATE) 6298 break; 6299 6300 if (should_gp) { 6301 TEST_ASSERT(!handle_x2apic_gp_ran); 6302 old_handler = setup_x2apic_gp_handler(); 6303 } 6304 6305 if (op == X2APIC_OP_RD) { 6306 u64 ret = vmx_x2apic_read(reg); 6307 6308 if (!should_gp) { 6309 u64 want = virt_fn(val); 6310 u64 got = virt_fn(ret); 6311 6312 report("APIC read; got 0x%lx, want 0x%lx.", 6313 got == want, got, want); 6314 } 6315 } else if (op == X2APIC_OP_WR) { 6316 vmx_x2apic_write(reg, val); 6317 } 6318 6319 if (should_gp) { 6320 report("x2APIC op triggered GP.", 6321 handle_x2apic_gp_ran); 6322 teardown_x2apic_gp_handler(old_handler); 6323 } 6324 6325 /* 6326 * The L1 should always execute a vmcall after it's done testing 6327 * an individual APIC operation. This helps to validate that the 6328 * L1 and L2 are in sync with each other, as expected. 6329 */ 6330 vmcall(); 6331 } 6332 } 6333 6334 static void test_x2apic_rd( 6335 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6336 u32 *virtual_apic_page) 6337 { 6338 u64 val = expectation->rd_val; 6339 u32 exit_reason_want = expectation->rd_exit_reason; 6340 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6341 6342 report_prefix_pushf("x2apic - reading 0x%03x", reg); 6343 6344 /* Configure guest to do an x2apic read */ 6345 args->op = X2APIC_OP_RD; 6346 args->reg = reg; 6347 args->val = val; 6348 args->should_gp = expectation->rd_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6349 args->virt_fn = expectation->virt_fn; 6350 6351 /* Setup virtual APIC page */ 6352 if (expectation->rd_behavior == X2APIC_ACCESS_VIRTUALIZED) 6353 virtual_apic_page[apic_reg_index(reg)] = (u32)val; 6354 6355 /* Enter guest */ 6356 enter_guest(); 6357 6358 if (exit_reason_want != VMX_VMCALL) { 6359 report("Oops, bad exit expectation: %u.", false, 6360 exit_reason_want); 6361 } 6362 6363 skip_exit_vmcall(); 6364 report_prefix_pop(); 6365 } 6366 6367 static volatile bool handle_x2apic_ipi_ran; 6368 static void handle_x2apic_ipi(isr_regs_t *regs) 6369 { 6370 handle_x2apic_ipi_ran = true; 6371 eoi(); 6372 } 6373 6374 static void test_x2apic_wr( 6375 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6376 u32 *virtual_apic_page) 6377 { 6378 u64 val = expectation->wr_val; 6379 u32 exit_reason_want = expectation->wr_exit_reason; 6380 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6381 int ipi_vector = 0xf1; 6382 u32 restore_val = 0; 6383 6384 report_prefix_pushf("x2apic - writing 0x%lx to 0x%03x", val, reg); 6385 6386 /* Configure guest to do an x2apic read */ 6387 args->op = X2APIC_OP_WR; 6388 args->reg = reg; 6389 args->val = val; 6390 args->should_gp = expectation->wr_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6391 6392 /* Setup virtual APIC page */ 6393 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) 6394 virtual_apic_page[apic_reg_index(reg)] = 0; 6395 if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH && !expectation->wr_only) 6396 restore_val = apic_read(reg); 6397 6398 /* Setup IPI handler */ 6399 handle_x2apic_ipi_ran = false; 6400 handle_irq(ipi_vector, handle_x2apic_ipi); 6401 6402 /* Enter guest */ 6403 enter_guest(); 6404 6405 /* 6406 * Validate the behavior and 6407 * pass a magic value back to the guest. 6408 */ 6409 if (exit_reason_want == VMX_EXTINT) { 6410 assert_exit_reason(exit_reason_want); 6411 6412 /* Clear the external interrupt. */ 6413 irq_enable(); 6414 asm volatile ("nop"); 6415 irq_disable(); 6416 report("Got pending interrupt after IRQ enabled.", 6417 handle_x2apic_ipi_ran); 6418 6419 enter_guest(); 6420 } else if (exit_reason_want == VMX_APIC_WRITE) { 6421 assert_exit_reason(exit_reason_want); 6422 report("got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%lx", 6423 virtual_apic_page[apic_reg_index(reg)] == val, 6424 apic_reg_index(reg), 6425 virtual_apic_page[apic_reg_index(reg)], val); 6426 6427 /* Reenter guest so it can consume/check rcx and exit again. */ 6428 enter_guest(); 6429 } else if (exit_reason_want != VMX_VMCALL) { 6430 report("Oops, bad exit expectation: %u.", false, 6431 exit_reason_want); 6432 } 6433 6434 assert_exit_reason(VMX_VMCALL); 6435 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) { 6436 u64 want = val; 6437 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6438 6439 report("x2APIC write; got 0x%x, want 0x%lx", 6440 got == want, got, want); 6441 } else if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH) { 6442 if (!expectation->wr_only) { 6443 u32 got = apic_read(reg); 6444 bool ok; 6445 6446 /* 6447 * When L1's TPR is passed through to L2, the lower 6448 * nibble can be lost. For example, if L2 executes 6449 * WRMSR(0x808, 0x78), then, L1 might read 0x70. 6450 * 6451 * Here's how the lower nibble can get lost: 6452 * 1. L2 executes WRMSR(0x808, 0x78). 6453 * 2. L2 exits to L0 with a WRMSR exit. 6454 * 3. L0 emulates WRMSR, by writing L1's TPR. 6455 * 4. L0 re-enters L2. 6456 * 5. L2 exits to L0 (reason doesn't matter). 6457 * 6. L0 reflects L2's exit to L1. 6458 * 7. Before entering L1, L0 exits to user-space 6459 * (e.g., to satisfy TPR access reporting). 6460 * 8. User-space executes KVM_SET_REGS ioctl, which 6461 * clears the lower nibble of L1's TPR. 6462 */ 6463 if (reg == APIC_TASKPRI) { 6464 got = apic_virt_nibble1(got); 6465 val = apic_virt_nibble1(val); 6466 } 6467 6468 ok = got == val; 6469 report("non-virtualized write; val is 0x%x, want 0x%lx", 6470 ok, got, val); 6471 apic_write(reg, restore_val); 6472 } else { 6473 report("non-virtualized and write-only OK", true); 6474 } 6475 } 6476 skip_exit_insn(); 6477 6478 report_prefix_pop(); 6479 } 6480 6481 static enum Config_type configure_virt_x2apic_mode_test( 6482 struct virt_x2apic_mode_config *virt_x2apic_mode_config, 6483 u8 *msr_bitmap_page) 6484 { 6485 int msr; 6486 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6487 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6488 6489 /* x2apic-specific VMCS config */ 6490 if (virt_x2apic_mode_config->use_msr_bitmaps) { 6491 /* virt_x2apic_mode_test() checks for MSR bitmaps support */ 6492 cpu_exec_ctrl0 |= CPU_MSR_BITMAP; 6493 } else { 6494 cpu_exec_ctrl0 &= ~CPU_MSR_BITMAP; 6495 } 6496 6497 if (virt_x2apic_mode_config->virtual_interrupt_delivery) { 6498 if (!(ctrl_cpu_rev[1].clr & CPU_VINTD)) { 6499 report_skip("VM-execution control \"virtual-interrupt delivery\" NOT supported.\n"); 6500 return CONFIG_TYPE_UNSUPPORTED; 6501 } 6502 cpu_exec_ctrl1 |= CPU_VINTD; 6503 } else { 6504 cpu_exec_ctrl1 &= ~CPU_VINTD; 6505 } 6506 6507 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6508 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6509 6510 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */ 6511 for (msr = 0x800; msr <= 0x8ff; msr++) { 6512 if (virt_x2apic_mode_config->disable_x2apic_msr_intercepts) { 6513 clear_bit(msr, msr_bitmap_page + 0x000); 6514 clear_bit(msr, msr_bitmap_page + 0x800); 6515 } else { 6516 set_bit(msr, msr_bitmap_page + 0x000); 6517 set_bit(msr, msr_bitmap_page + 0x800); 6518 } 6519 } 6520 6521 /* x2APIC mode can impact virtualization */ 6522 reset_apic(); 6523 if (!virt_x2apic_mode_config->disable_x2apic) 6524 enable_x2apic(); 6525 6526 return configure_apic_reg_virt_test( 6527 &virt_x2apic_mode_config->apic_reg_virt_config); 6528 } 6529 6530 static void virt_x2apic_mode_test(void) 6531 { 6532 u32 *virtual_apic_page; 6533 u8 *msr_bitmap_page; 6534 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6535 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6536 int i; 6537 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6538 6539 if (!cpu_has_apicv()) { 6540 report_skip(__func__); 6541 return; 6542 } 6543 6544 /* 6545 * This is to exercise an issue in KVM's logic to merge L0's and L1's 6546 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by 6547 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would 6548 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the 6549 * "Virtualize x2APIC mod" control set, even when it didn't. 6550 */ 6551 if (has_spec_ctrl()) 6552 wrmsr(MSR_IA32_SPEC_CTRL, 1); 6553 6554 /* 6555 * Check that VMCS12 supports: 6556 * - "Virtual-APIC address", indicated by "use TPR shadow" 6557 * - "MSR-bitmap address", indicated by "use MSR bitmaps" 6558 */ 6559 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6560 report_skip("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6561 return; 6562 } else if (!(ctrl_cpu_rev[0].clr & CPU_MSR_BITMAP)) { 6563 report_skip("VM-execution control \"use MSR bitmaps\" NOT supported.\n"); 6564 return; 6565 } 6566 6567 test_set_guest(virt_x2apic_mode_guest); 6568 6569 virtual_apic_page = alloc_page(); 6570 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6571 6572 msr_bitmap_page = alloc_page(); 6573 memset(msr_bitmap_page, 0xff, PAGE_SIZE); 6574 vmcs_write(MSR_BITMAP, virt_to_phys(msr_bitmap_page)); 6575 6576 for (i = 0; i < ARRAY_SIZE(virt_x2apic_mode_tests); i++) { 6577 struct virt_x2apic_mode_test_case *virt_x2apic_mode_test_case = 6578 &virt_x2apic_mode_tests[i]; 6579 struct virt_x2apic_mode_config *virt_x2apic_mode_config = 6580 &virt_x2apic_mode_test_case->virt_x2apic_mode_config; 6581 enum Config_type config_type; 6582 u32 reg; 6583 6584 printf("--- %s test ---\n", virt_x2apic_mode_test_case->name); 6585 config_type = 6586 configure_virt_x2apic_mode_test(virt_x2apic_mode_config, 6587 msr_bitmap_page); 6588 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6589 report_skip("Skip because of missing features.\n"); 6590 continue; 6591 } else if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6592 enter_guest_with_bad_controls(); 6593 continue; 6594 } 6595 6596 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6597 struct virt_x2apic_mode_expectation expectation; 6598 6599 virt_x2apic_mode_exit_expectation( 6600 reg, virt_x2apic_mode_config, &expectation); 6601 6602 test_x2apic_rd(reg, &expectation, virtual_apic_page); 6603 test_x2apic_wr(reg, &expectation, virtual_apic_page); 6604 } 6605 } 6606 6607 6608 /* Terminate the guest */ 6609 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6610 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6611 args->op = X2APIC_TERMINATE; 6612 enter_guest(); 6613 assert_exit_reason(VMX_VMCALL); 6614 } 6615 6616 /* 6617 * On processors that support Intel 64 architecture, the IA32_SYSENTER_ESP 6618 * field and the IA32_SYSENTER_EIP field must each contain a canonical 6619 * address. 6620 * 6621 * [Intel SDM] 6622 */ 6623 static void test_sysenter_field(u32 field, const char *name) 6624 { 6625 u64 addr_saved = vmcs_read(field); 6626 6627 vmcs_write(field, NONCANONICAL); 6628 report_prefix_pushf("%s non-canonical", name); 6629 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6630 report_prefix_pop(); 6631 6632 vmcs_write(field, 0xffffffff); 6633 report_prefix_pushf("%s canonical", name); 6634 test_vmx_vmlaunch(0); 6635 report_prefix_pop(); 6636 6637 vmcs_write(field, addr_saved); 6638 } 6639 6640 static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1) 6641 { 6642 u64 val; 6643 u64 cr_saved = vmcs_read(cr); 6644 int i; 6645 6646 val = fixed0 & fixed1; 6647 if (cr == HOST_CR4) 6648 vmcs_write(cr, val | X86_CR4_PAE); 6649 else 6650 vmcs_write(cr, val); 6651 report_prefix_pushf("%s %lx", cr_name, val); 6652 if (val == fixed0) 6653 test_vmx_vmlaunch(0); 6654 else 6655 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6656 report_prefix_pop(); 6657 6658 for (i = 0; i < 64; i++) { 6659 6660 /* Set a bit when the corresponding bit in fixed1 is 0 */ 6661 if ((fixed1 & (1ull << i)) == 0) { 6662 if (cr == HOST_CR4 && ((1ull << i) & X86_CR4_SMEP || 6663 (1ull << i) & X86_CR4_SMAP)) 6664 continue; 6665 6666 vmcs_write(cr, cr_saved | (1ull << i)); 6667 report_prefix_pushf("%s %llx", cr_name, 6668 cr_saved | (1ull << i)); 6669 test_vmx_vmlaunch( 6670 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6671 report_prefix_pop(); 6672 } 6673 6674 /* Unset a bit when the corresponding bit in fixed0 is 1 */ 6675 if (fixed0 & (1ull << i)) { 6676 vmcs_write(cr, cr_saved & ~(1ull << i)); 6677 report_prefix_pushf("%s %llx", cr_name, 6678 cr_saved & ~(1ull << i)); 6679 test_vmx_vmlaunch( 6680 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6681 report_prefix_pop(); 6682 } 6683 } 6684 6685 vmcs_write(cr, cr_saved); 6686 } 6687 6688 /* 6689 * 1. The CR0 field must not set any bit to a value not supported in VMX 6690 * operation. 6691 * 2. The CR4 field must not set any bit to a value not supported in VMX 6692 * operation. 6693 * 3. On processors that support Intel 64 architecture, the CR3 field must 6694 * be such that bits 63:52 and bits in the range 51:32 beyond the 6695 * processor’s physical-address width must be 0. 6696 * 6697 * [Intel SDM] 6698 */ 6699 static void test_host_ctl_regs(void) 6700 { 6701 u64 fixed0, fixed1, cr3, cr3_saved; 6702 int i; 6703 6704 /* Test CR0 */ 6705 fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0); 6706 fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1); 6707 test_ctl_reg("HOST_CR0", HOST_CR0, fixed0, fixed1); 6708 6709 /* Test CR4 */ 6710 fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0); 6711 fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1) & 6712 ~(X86_CR4_SMEP | X86_CR4_SMAP); 6713 test_ctl_reg("HOST_CR4", HOST_CR4, fixed0, fixed1); 6714 6715 /* Test CR3 */ 6716 cr3_saved = vmcs_read(HOST_CR3); 6717 for (i = cpuid_maxphyaddr(); i < 64; i++) { 6718 cr3 = cr3_saved | (1ul << i); 6719 vmcs_write(HOST_CR3, cr3); 6720 report_prefix_pushf("HOST_CR3 %lx", cr3); 6721 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6722 report_prefix_pop(); 6723 } 6724 6725 vmcs_write(HOST_CR3, cr3_saved); 6726 } 6727 6728 static void test_efer_vmlaunch(u32 fld, bool ok) 6729 { 6730 if (fld == HOST_EFER) { 6731 if (ok) 6732 test_vmx_vmlaunch(0); 6733 else 6734 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6735 } else { 6736 if (ok) { 6737 enter_guest(); 6738 report("vmlaunch succeeds", vmcs_read(EXI_REASON) == VMX_VMCALL); 6739 } else { 6740 enter_guest_with_invalid_guest_state(); 6741 report("vmlaunch fails", vmcs_read(EXI_REASON) == (VMX_ENTRY_FAILURE | VMX_FAIL_STATE)); 6742 } 6743 advance_guest_state_test(); 6744 } 6745 } 6746 6747 static void test_efer_one(u32 fld, const char * fld_name, u64 efer, 6748 u32 ctrl_fld, u64 ctrl, 6749 int i, const char *efer_bit_name) 6750 { 6751 bool ok; 6752 6753 ok = true; 6754 if (ctrl_fld == EXI_CONTROLS && (ctrl & EXI_LOAD_EFER)) { 6755 if (!!(efer & EFER_LMA) != !!(ctrl & EXI_HOST_64)) 6756 ok = false; 6757 if (!!(efer & EFER_LME) != !!(ctrl & EXI_HOST_64)) 6758 ok = false; 6759 } 6760 if (ctrl_fld == ENT_CONTROLS && (ctrl & ENT_LOAD_EFER)) { 6761 /* Check LMA too since CR0.PG is set. */ 6762 if (!!(efer & EFER_LMA) != !!(ctrl & ENT_GUEST_64)) 6763 ok = false; 6764 if (!!(efer & EFER_LME) != !!(ctrl & ENT_GUEST_64)) 6765 ok = false; 6766 } 6767 6768 /* 6769 * Skip the test if it would enter the guest in 32-bit mode. 6770 * Perhaps write the test in assembly and make sure it 6771 * can be run in either mode? 6772 */ 6773 if (fld == GUEST_EFER && ok && !(ctrl & ENT_GUEST_64)) 6774 return; 6775 6776 vmcs_write(ctrl_fld, ctrl); 6777 vmcs_write(fld, efer); 6778 report_prefix_pushf("%s %s bit turned %s, controls %s", 6779 fld_name, efer_bit_name, 6780 (i & 1) ? "on" : "off", 6781 (i & 2) ? "on" : "off"); 6782 6783 test_efer_vmlaunch(fld, ok); 6784 report_prefix_pop(); 6785 } 6786 6787 static void test_efer_bit(u32 fld, const char * fld_name, 6788 u32 ctrl_fld, u64 ctrl_bit, u64 efer_bit, 6789 const char *efer_bit_name) 6790 { 6791 u64 efer_saved = vmcs_read(fld); 6792 u32 ctrl_saved = vmcs_read(ctrl_fld); 6793 int i; 6794 6795 for (i = 0; i < 4; i++) { 6796 u64 efer = efer_saved & ~efer_bit; 6797 u64 ctrl = ctrl_saved & ~ctrl_bit; 6798 6799 if (i & 1) 6800 efer |= efer_bit; 6801 if (i & 2) 6802 ctrl |= ctrl_bit; 6803 6804 test_efer_one(fld, fld_name, efer, ctrl_fld, ctrl, 6805 i, efer_bit_name); 6806 } 6807 6808 vmcs_write(ctrl_fld, ctrl_saved); 6809 vmcs_write(fld, efer_saved); 6810 } 6811 6812 static void test_efer(u32 fld, const char * fld_name, u32 ctrl_fld, 6813 u64 ctrl_bit1, u64 ctrl_bit2) 6814 { 6815 u64 efer_saved = vmcs_read(fld); 6816 u32 ctrl_saved = vmcs_read(ctrl_fld); 6817 u64 efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 6818 u64 i; 6819 u64 efer; 6820 6821 if (cpu_has_efer_nx()) 6822 efer_reserved_bits &= ~EFER_NX; 6823 6824 if (!ctrl_bit1) { 6825 printf("\"Load-IA32-EFER\" exit control not supported\n"); 6826 goto test_entry_exit_mode; 6827 } 6828 6829 report_prefix_pushf("%s %lx", fld_name, efer_saved); 6830 test_efer_vmlaunch(fld, true); 6831 report_prefix_pop(); 6832 6833 /* 6834 * Check reserved bits 6835 */ 6836 vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit1); 6837 for (i = 0; i < 64; i++) { 6838 if ((1ull << i) & efer_reserved_bits) { 6839 efer = efer_saved | (1ull << i); 6840 vmcs_write(fld, efer); 6841 report_prefix_pushf("%s %lx", fld_name, efer); 6842 test_efer_vmlaunch(fld, true); 6843 report_prefix_pop(); 6844 } 6845 } 6846 6847 vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit1); 6848 for (i = 0; i < 64; i++) { 6849 if ((1ull << i) & efer_reserved_bits) { 6850 efer = efer_saved | (1ull << i); 6851 vmcs_write(fld, efer); 6852 report_prefix_pushf("%s %lx", fld_name, efer); 6853 test_efer_vmlaunch(fld, false); 6854 report_prefix_pop(); 6855 } 6856 } 6857 6858 vmcs_write(ctrl_fld, ctrl_saved); 6859 vmcs_write(fld, efer_saved); 6860 6861 /* 6862 * Check LMA and LME bits 6863 */ 6864 test_efer_bit(fld, fld_name, 6865 ctrl_fld, ctrl_bit1, 6866 EFER_LMA, 6867 "EFER_LMA"); 6868 test_efer_bit(fld, fld_name, 6869 ctrl_fld, ctrl_bit1, 6870 EFER_LME, 6871 "EFER_LME"); 6872 6873 test_entry_exit_mode: 6874 test_efer_bit(fld, fld_name, 6875 ctrl_fld, ctrl_bit2, 6876 EFER_LMA, 6877 "EFER_LMA"); 6878 test_efer_bit(fld, fld_name, 6879 ctrl_fld, ctrl_bit2, 6880 EFER_LME, 6881 "EFER_LME"); 6882 } 6883 6884 /* 6885 * If the 'load IA32_EFER' VM-exit control is 1, bits reserved in the 6886 * IA32_EFER MSR must be 0 in the field for that register. In addition, 6887 * the values of the LMA and LME bits in the field must each be that of 6888 * the 'host address-space size' VM-exit control. 6889 * 6890 * [Intel SDM] 6891 */ 6892 static void test_host_efer(void) 6893 { 6894 test_efer(HOST_EFER, "HOST_EFER", EXI_CONTROLS, 6895 ctrl_exit_rev.clr & EXI_LOAD_EFER, 6896 EXI_HOST_64); 6897 } 6898 6899 /* 6900 * If the 'load IA32_EFER' VM-enter control is 1, bits reserved in the 6901 * IA32_EFER MSR must be 0 in the field for that register. In addition, 6902 * the values of the LMA and LME bits in the field must each be that of 6903 * the 'IA32e-mode guest' VM-exit control. 6904 */ 6905 static void test_guest_efer(void) 6906 { 6907 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) { 6908 printf("\"Load-IA32-EFER\" entry control not supported\n"); 6909 return; 6910 } 6911 6912 vmcs_write(GUEST_EFER, rdmsr(MSR_EFER)); 6913 test_efer(GUEST_EFER, "GUEST_EFER", ENT_CONTROLS, 6914 ctrl_enter_rev.clr & ENT_LOAD_EFER, 6915 ENT_GUEST_64); 6916 } 6917 6918 /* 6919 * PAT values higher than 8 are uninteresting since they're likely lumped 6920 * in with "8". We only test values above 8 one bit at a time, 6921 * in order to reduce the number of VM-Entries and keep the runtime reasonable. 6922 */ 6923 #define PAT_VAL_LIMIT 8 6924 6925 static void test_pat(u32 field, const char * field_name, u32 ctrl_field, 6926 u64 ctrl_bit) 6927 { 6928 u32 ctrl_saved = vmcs_read(ctrl_field); 6929 u64 pat_saved = vmcs_read(field); 6930 u64 i, val; 6931 u32 j; 6932 int error; 6933 6934 vmcs_clear_bits(ctrl_field, ctrl_bit); 6935 6936 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 6937 /* Test PAT0..PAT7 fields */ 6938 for (j = 0; j < (i ? 8 : 1); j++) { 6939 val = i << j * 8; 6940 vmcs_write(field, val); 6941 if (field == HOST_PAT) { 6942 report_prefix_pushf("%s %lx", field_name, val); 6943 test_vmx_vmlaunch(0); 6944 report_prefix_pop(); 6945 6946 } else { // GUEST_PAT 6947 enter_guest(); 6948 report_guest_state_test("ENT_LOAD_PAT enabled", 6949 VMX_VMCALL, val, 6950 "GUEST_PAT"); 6951 } 6952 } 6953 } 6954 6955 vmcs_set_bits(ctrl_field, ctrl_bit); 6956 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 6957 /* Test PAT0..PAT7 fields */ 6958 for (j = 0; j < (i ? 8 : 1); j++) { 6959 val = i << j * 8; 6960 vmcs_write(field, val); 6961 6962 if (field == HOST_PAT) { 6963 report_prefix_pushf("%s %lx", field_name, val); 6964 if (i == 0x2 || i == 0x3 || i >= 0x8) 6965 error = 6966 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; 6967 else 6968 error = 0; 6969 6970 test_vmx_vmlaunch(error); 6971 report_prefix_pop(); 6972 6973 } else { // GUEST_PAT 6974 if (i == 0x2 || i == 0x3 || i >= 0x8) { 6975 enter_guest_with_invalid_guest_state(); 6976 report_guest_state_test("ENT_LOAD_PAT " 6977 "enabled", 6978 VMX_FAIL_STATE | VMX_ENTRY_FAILURE, 6979 val, 6980 "GUEST_PAT"); 6981 } else { 6982 enter_guest(); 6983 report_guest_state_test("ENT_LOAD_PAT " 6984 "enabled", 6985 VMX_VMCALL, 6986 val, 6987 "GUEST_PAT"); 6988 } 6989 } 6990 6991 } 6992 } 6993 6994 vmcs_write(ctrl_field, ctrl_saved); 6995 vmcs_write(field, pat_saved); 6996 } 6997 6998 /* 6999 * If the "load IA32_PAT" VM-exit control is 1, the value of the field 7000 * for the IA32_PAT MSR must be one that could be written by WRMSR 7001 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7002 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7003 * 6 (WB), or 7 (UC-). 7004 * 7005 * [Intel SDM] 7006 */ 7007 static void test_load_host_pat(void) 7008 { 7009 /* 7010 * "load IA32_PAT" VM-exit control 7011 */ 7012 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) { 7013 printf("\"Load-IA32-PAT\" exit control not supported\n"); 7014 return; 7015 } 7016 7017 test_pat(HOST_PAT, "HOST_PAT", EXI_CONTROLS, EXI_LOAD_PAT); 7018 } 7019 7020 /* 7021 * test_vmcs_field - test a value for the given VMCS field 7022 * @field: VMCS field 7023 * @field_name: string name of VMCS field 7024 * @bit_start: starting bit 7025 * @bit_end: ending bit 7026 * @val: value that the bit range must or must not contain 7027 * @valid_val: whether value given in 'val' must be valid or not 7028 * @error: expected VMCS error when vmentry fails for an invalid value 7029 */ 7030 static void test_vmcs_field(u64 field, const char *field_name, u32 bit_start, 7031 u32 bit_end, u64 val, bool valid_val, u32 error) 7032 { 7033 u64 field_saved = vmcs_read(field); 7034 u32 i; 7035 u64 tmp; 7036 u32 bit_on; 7037 u64 mask = ~0ull; 7038 7039 mask = (mask >> bit_end) << bit_end; 7040 mask = mask | ((1 << bit_start) - 1); 7041 tmp = (field_saved & mask) | (val << bit_start); 7042 7043 vmcs_write(field, tmp); 7044 report_prefix_pushf("%s %lx", field_name, tmp); 7045 if (valid_val) 7046 test_vmx_vmlaunch(0); 7047 else 7048 test_vmx_vmlaunch(error); 7049 report_prefix_pop(); 7050 7051 for (i = bit_start; i <= bit_end; i = i + 2) { 7052 bit_on = ((1ull < i) & (val << bit_start)) ? 0 : 1; 7053 if (bit_on) 7054 tmp = field_saved | (1ull << i); 7055 else 7056 tmp = field_saved & ~(1ull << i); 7057 vmcs_write(field, tmp); 7058 report_prefix_pushf("%s %lx", field_name, tmp); 7059 if (valid_val) 7060 test_vmx_vmlaunch(error); 7061 else 7062 test_vmx_vmlaunch(0); 7063 report_prefix_pop(); 7064 } 7065 7066 vmcs_write(field, field_saved); 7067 } 7068 7069 static void test_canonical(u64 field, const char * field_name) 7070 { 7071 u64 addr_saved = vmcs_read(field); 7072 7073 report_prefix_pushf("%s %lx", field_name, addr_saved); 7074 if (is_canonical(addr_saved)) { 7075 test_vmx_vmlaunch(0); 7076 report_prefix_pop(); 7077 7078 vmcs_write(field, NONCANONICAL); 7079 report_prefix_pushf("%s %llx", field_name, NONCANONICAL); 7080 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7081 7082 vmcs_write(field, addr_saved); 7083 } else { 7084 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7085 } 7086 report_prefix_pop(); 7087 } 7088 7089 #define TEST_RPL_TI_FLAGS(reg, name) \ 7090 test_vmcs_field(reg, name, 0, 2, 0x0, true, \ 7091 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7092 7093 #define TEST_CS_TR_FLAGS(reg, name) \ 7094 test_vmcs_field(reg, name, 3, 15, 0x0000, false, \ 7095 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7096 7097 /* 7098 * 1. In the selector field for each of CS, SS, DS, ES, FS, GS and TR, the 7099 * RPL (bits 1:0) and the TI flag (bit 2) must be 0. 7100 * 2. The selector fields for CS and TR cannot be 0000H. 7101 * 3. The selector field for SS cannot be 0000H if the "host address-space 7102 * size" VM-exit control is 0. 7103 * 4. On processors that support Intel 64 architecture, the base-address 7104 * fields for FS, GS and TR must contain canonical addresses. 7105 */ 7106 static void test_host_segment_regs(void) 7107 { 7108 u16 selector_saved; 7109 7110 /* 7111 * Test RPL and TI flags 7112 */ 7113 TEST_RPL_TI_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7114 TEST_RPL_TI_FLAGS(HOST_SEL_SS, "HOST_SEL_SS"); 7115 TEST_RPL_TI_FLAGS(HOST_SEL_DS, "HOST_SEL_DS"); 7116 TEST_RPL_TI_FLAGS(HOST_SEL_ES, "HOST_SEL_ES"); 7117 TEST_RPL_TI_FLAGS(HOST_SEL_FS, "HOST_SEL_FS"); 7118 TEST_RPL_TI_FLAGS(HOST_SEL_GS, "HOST_SEL_GS"); 7119 TEST_RPL_TI_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7120 7121 /* 7122 * Test that CS and TR fields can not be 0x0000 7123 */ 7124 TEST_CS_TR_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7125 TEST_CS_TR_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7126 7127 /* 7128 * SS field can not be 0x0000 if "host address-space size" VM-exit 7129 * control is 0 7130 */ 7131 selector_saved = vmcs_read(HOST_SEL_SS); 7132 vmcs_write(HOST_SEL_SS, 0); 7133 report_prefix_pushf("HOST_SEL_SS 0"); 7134 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7135 test_vmx_vmlaunch(0); 7136 } else { 7137 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7138 } 7139 report_prefix_pop(); 7140 7141 vmcs_write(HOST_SEL_SS, selector_saved); 7142 7143 #ifdef __x86_64__ 7144 /* 7145 * Base address for FS, GS and TR must be canonical 7146 */ 7147 test_canonical(HOST_BASE_FS, "HOST_BASE_FS"); 7148 test_canonical(HOST_BASE_GS, "HOST_BASE_GS"); 7149 test_canonical(HOST_BASE_TR, "HOST_BASE_TR"); 7150 #endif 7151 } 7152 7153 /* 7154 * On processors that support Intel 64 architecture, the base-address 7155 * fields for GDTR and IDTR must contain canonical addresses. 7156 */ 7157 static void test_host_desc_tables(void) 7158 { 7159 #ifdef __x86_64__ 7160 test_canonical(HOST_BASE_GDTR, "HOST_BASE_GDTR"); 7161 test_canonical(HOST_BASE_IDTR, "HOST_BASE_IDTR"); 7162 #endif 7163 } 7164 7165 /* 7166 * If the "host address-space size" VM-exit control is 0, the following must 7167 * hold: 7168 * - The "IA-32e mode guest" VM-entry control is 0. 7169 * - Bit 17 of the CR4 field (corresponding to CR4.PCIDE) is 0. 7170 * - Bits 63:32 in the RIP field are 0. 7171 * 7172 * If the "host address-space size" VM-exit control is 1, the following must 7173 * hold: 7174 * - Bit 5 of the CR4 field (corresponding to CR4.PAE) is 1. 7175 * - The RIP field contains a canonical address. 7176 * 7177 */ 7178 static void test_host_addr_size(void) 7179 { 7180 u64 cr4_saved = vmcs_read(HOST_CR4); 7181 u64 rip_saved = vmcs_read(HOST_RIP); 7182 u64 entry_ctrl_saved = vmcs_read(ENT_CONTROLS); 7183 int i; 7184 u64 tmp; 7185 7186 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7187 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7188 report_prefix_pushf("\"IA-32e mode guest\" enabled"); 7189 test_vmx_vmlaunch(0); 7190 report_prefix_pop(); 7191 7192 vmcs_write(HOST_CR4, cr4_saved | X86_CR4_PCIDE); 7193 report_prefix_pushf("\"CR4.PCIDE\" set"); 7194 test_vmx_vmlaunch(0); 7195 report_prefix_pop(); 7196 7197 for (i = 32; i <= 63; i = i + 4) { 7198 tmp = rip_saved | 1ull << i; 7199 vmcs_write(HOST_RIP, tmp); 7200 report_prefix_pushf("HOST_RIP %lx", tmp); 7201 test_vmx_vmlaunch(0); 7202 report_prefix_pop(); 7203 } 7204 7205 if (cr4_saved & X86_CR4_PAE) { 7206 vmcs_write(HOST_CR4, cr4_saved & ~X86_CR4_PAE); 7207 report_prefix_pushf("\"CR4.PAE\" unset"); 7208 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7209 } else { 7210 report_prefix_pushf("\"CR4.PAE\" set"); 7211 test_vmx_vmlaunch(0); 7212 } 7213 report_prefix_pop(); 7214 7215 vmcs_write(HOST_RIP, NONCANONICAL); 7216 report_prefix_pushf("HOST_RIP %llx", NONCANONICAL); 7217 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7218 report_prefix_pop(); 7219 7220 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7221 vmcs_write(HOST_RIP, rip_saved); 7222 vmcs_write(HOST_CR4, cr4_saved); 7223 } 7224 } 7225 7226 /* 7227 * Check that the virtual CPU checks the VMX Host State Area as 7228 * documented in the Intel SDM. 7229 */ 7230 static void vmx_host_state_area_test(void) 7231 { 7232 /* 7233 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 7234 * fail due to invalid guest state, should we make it that 7235 * far. 7236 */ 7237 vmcs_write(GUEST_RFLAGS, 0); 7238 7239 test_host_ctl_regs(); 7240 7241 test_sysenter_field(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP"); 7242 test_sysenter_field(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP"); 7243 7244 test_host_efer(); 7245 test_load_host_pat(); 7246 test_host_segment_regs(); 7247 test_host_desc_tables(); 7248 test_host_addr_size(); 7249 } 7250 7251 /* 7252 * If the "load IA32_PAT" VM-entry control is 1, the value of the field 7253 * for the IA32_PAT MSR must be one that could be written by WRMSR 7254 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7255 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7256 * 6 (WB), or 7 (UC-). 7257 * 7258 * [Intel SDM] 7259 */ 7260 static void test_load_guest_pat(void) 7261 { 7262 /* 7263 * "load IA32_PAT" VM-entry control 7264 */ 7265 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 7266 printf("\"Load-IA32-PAT\" entry control not supported\n"); 7267 return; 7268 } 7269 7270 test_pat(GUEST_PAT, "GUEST_PAT", ENT_CONTROLS, ENT_LOAD_PAT); 7271 } 7272 7273 /* 7274 * Check that the virtual CPU checks the VMX Guest State Area as 7275 * documented in the Intel SDM. 7276 */ 7277 static void vmx_guest_state_area_test(void) 7278 { 7279 vmx_set_test_stage(1); 7280 test_set_guest(guest_state_test_main); 7281 7282 test_load_guest_pat(); 7283 test_guest_efer(); 7284 7285 /* 7286 * Let the guest finish execution 7287 */ 7288 vmx_set_test_stage(2); 7289 enter_guest(); 7290 } 7291 7292 static bool valid_vmcs_for_vmentry(void) 7293 { 7294 struct vmcs *current_vmcs = NULL; 7295 7296 if (vmcs_save(¤t_vmcs)) 7297 return false; 7298 7299 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 7300 } 7301 7302 static void try_vmentry_in_movss_shadow(void) 7303 { 7304 u32 vm_inst_err; 7305 u32 flags; 7306 bool early_failure = false; 7307 u32 expected_flags = X86_EFLAGS_FIXED; 7308 bool valid_vmcs = valid_vmcs_for_vmentry(); 7309 7310 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 7311 7312 /* 7313 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 7314 * unsupported VMCS component"). 7315 */ 7316 vmcs_write(~0u, 0); 7317 7318 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 7319 "vmwrite %%rsp, %%rdx;" 7320 "mov 0f, %%rax;" 7321 "mov %[host_rip], %%edx;" 7322 "vmwrite %%rax, %%rdx;" 7323 "mov $-1, %%ah;" 7324 "sahf;" 7325 "mov %%ss, %%ax;" 7326 "mov %%ax, %%ss;" 7327 "vmlaunch;" 7328 "mov $1, %[early_failure];" 7329 "0: lahf;" 7330 "movzbl %%ah, %[flags]" 7331 : [early_failure] "+r" (early_failure), 7332 [flags] "=&a" (flags) 7333 : [host_rsp] "i" (HOST_RSP), 7334 [host_rip] "i" (HOST_RIP) 7335 : "rdx", "cc", "memory"); 7336 vm_inst_err = vmcs_read(VMX_INST_ERROR); 7337 7338 report("Early VM-entry failure", early_failure); 7339 report("RFLAGS[8:0] is %x (actual %x)", flags == expected_flags, 7340 expected_flags, flags); 7341 if (valid_vmcs) 7342 report("VM-instruction error is %d (actual %d)", 7343 vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 7344 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 7345 } 7346 7347 static void vmentry_movss_shadow_test(void) 7348 { 7349 struct vmcs *orig_vmcs; 7350 7351 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 7352 7353 /* 7354 * Set the launched flag on the current VMCS to verify the correct 7355 * error priority, below. 7356 */ 7357 test_set_guest(v2_null_test_guest); 7358 enter_guest(); 7359 7360 /* 7361 * With bit 1 of the guest's RFLAGS clear, VM-entry should 7362 * fail due to invalid guest state (if we make it that far). 7363 */ 7364 vmcs_write(GUEST_RFLAGS, 0); 7365 7366 /* 7367 * "VM entry with events blocked by MOV SS" takes precedence over 7368 * "VMLAUNCH with non-clear VMCS." 7369 */ 7370 report_prefix_push("valid current-VMCS"); 7371 try_vmentry_in_movss_shadow(); 7372 report_prefix_pop(); 7373 7374 /* 7375 * VMfailInvalid takes precedence over "VM entry with events 7376 * blocked by MOV SS." 7377 */ 7378 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 7379 report_prefix_push("no current-VMCS"); 7380 try_vmentry_in_movss_shadow(); 7381 report_prefix_pop(); 7382 7383 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 7384 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 7385 } 7386 7387 static void vmx_cr_load_test(void) 7388 { 7389 unsigned long cr3, cr4, orig_cr3, orig_cr4; 7390 7391 orig_cr4 = read_cr4(); 7392 orig_cr3 = read_cr3(); 7393 7394 if (!this_cpu_has(X86_FEATURE_PCID)) { 7395 report_skip("PCID not detected"); 7396 return; 7397 } 7398 if (!this_cpu_has(X86_FEATURE_MCE)) { 7399 report_skip("MCE not detected"); 7400 return; 7401 } 7402 7403 TEST_ASSERT(!(orig_cr3 & X86_CR3_PCID_MASK)); 7404 7405 /* Enable PCID for L1. */ 7406 cr4 = orig_cr4 | X86_CR4_PCIDE; 7407 cr3 = orig_cr3 | 0x1; 7408 TEST_ASSERT(!write_cr4_checking(cr4)); 7409 write_cr3(cr3); 7410 7411 test_set_guest(v2_null_test_guest); 7412 vmcs_write(HOST_CR4, cr4); 7413 vmcs_write(HOST_CR3, cr3); 7414 enter_guest(); 7415 7416 /* 7417 * No exception is expected. 7418 * 7419 * NB. KVM loads the last guest write to CR4 into CR4 read 7420 * shadow. In order to trigger an exit to KVM, we can toggle a 7421 * bit that is owned by KVM. We use CR4.MCE, which shall 7422 * have no side effect because normally no guest MCE (e.g., as the 7423 * result of bad memory) would happen during this test. 7424 */ 7425 TEST_ASSERT(!write_cr4_checking(cr4 ^ X86_CR4_MCE)); 7426 7427 /* Cleanup L1 state. */ 7428 write_cr3(orig_cr3); 7429 TEST_ASSERT(!write_cr4_checking(orig_cr4)); 7430 } 7431 7432 static void vmx_nm_test_guest(void) 7433 { 7434 write_cr0(read_cr0() | X86_CR0_TS); 7435 asm volatile("fnop"); 7436 } 7437 7438 static void check_nm_exit(const char *test) 7439 { 7440 u32 reason = vmcs_read(EXI_REASON); 7441 u32 intr_info = vmcs_read(EXI_INTR_INFO); 7442 const u32 expected = INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 7443 NM_VECTOR; 7444 7445 report("%s", reason == VMX_EXC_NMI && intr_info == expected, test); 7446 } 7447 7448 /* 7449 * This test checks that: 7450 * 7451 * (a) If L2 launches with CR0.TS clear, but later sets CR0.TS, then 7452 * a subsequent #NM VM-exit is reflected to L1. 7453 * 7454 * (b) If L2 launches with CR0.TS clear and CR0.EM set, then a 7455 * subsequent #NM VM-exit is reflected to L1. 7456 */ 7457 static void vmx_nm_test(void) 7458 { 7459 unsigned long cr0 = read_cr0(); 7460 7461 test_set_guest(vmx_nm_test_guest); 7462 7463 /* 7464 * L1 wants to intercept #NM exceptions encountered in L2. 7465 */ 7466 vmcs_write(EXC_BITMAP, 1 << NM_VECTOR); 7467 7468 /* 7469 * Launch L2 with CR0.TS clear, but don't claim host ownership of 7470 * any CR0 bits. L2 will set CR0.TS and then try to execute fnop, 7471 * which will raise #NM. L0 should reflect the #NM VM-exit to L1. 7472 */ 7473 vmcs_write(CR0_MASK, 0); 7474 vmcs_write(GUEST_CR0, cr0 & ~X86_CR0_TS); 7475 enter_guest(); 7476 check_nm_exit("fnop with CR0.TS set in L2 triggers #NM VM-exit to L1"); 7477 7478 /* 7479 * Re-enter L2 at the fnop instruction, with CR0.TS clear but 7480 * CR0.EM set. The fnop will still raise #NM, and L0 should 7481 * reflect the #NM VM-exit to L1. 7482 */ 7483 vmcs_write(GUEST_CR0, (cr0 & ~X86_CR0_TS) | X86_CR0_EM); 7484 enter_guest(); 7485 check_nm_exit("fnop with CR0.EM set in L2 triggers #NM VM-exit to L1"); 7486 7487 /* 7488 * Re-enter L2 at the fnop instruction, with both CR0.TS and 7489 * CR0.EM clear. There will be no #NM, and the L2 guest should 7490 * exit normally. 7491 */ 7492 vmcs_write(GUEST_CR0, cr0 & ~(X86_CR0_TS | X86_CR0_EM)); 7493 enter_guest(); 7494 } 7495 7496 bool vmx_pending_event_ipi_fired; 7497 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 7498 { 7499 vmx_pending_event_ipi_fired = true; 7500 eoi(); 7501 } 7502 7503 bool vmx_pending_event_guest_run; 7504 static void vmx_pending_event_guest(void) 7505 { 7506 vmcall(); 7507 vmx_pending_event_guest_run = true; 7508 } 7509 7510 static void vmx_pending_event_test_core(bool guest_hlt) 7511 { 7512 int ipi_vector = 0xf1; 7513 7514 vmx_pending_event_ipi_fired = false; 7515 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 7516 7517 vmx_pending_event_guest_run = false; 7518 test_set_guest(vmx_pending_event_guest); 7519 7520 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 7521 7522 enter_guest(); 7523 skip_exit_vmcall(); 7524 7525 if (guest_hlt) 7526 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7527 7528 irq_disable(); 7529 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 7530 APIC_DM_FIXED | ipi_vector, 7531 0); 7532 7533 enter_guest(); 7534 7535 assert_exit_reason(VMX_EXTINT); 7536 report("Guest did not run before host received IPI", 7537 !vmx_pending_event_guest_run); 7538 7539 irq_enable(); 7540 asm volatile ("nop"); 7541 irq_disable(); 7542 report("Got pending interrupt after IRQ enabled", 7543 vmx_pending_event_ipi_fired); 7544 7545 if (guest_hlt) 7546 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 7547 7548 enter_guest(); 7549 report("Guest finished running when no interrupt", 7550 vmx_pending_event_guest_run); 7551 } 7552 7553 static void vmx_pending_event_test(void) 7554 { 7555 vmx_pending_event_test_core(false); 7556 } 7557 7558 static void vmx_pending_event_hlt_test(void) 7559 { 7560 vmx_pending_event_test_core(true); 7561 } 7562 7563 static int vmx_window_test_db_count; 7564 7565 static void vmx_window_test_db_handler(struct ex_regs *regs) 7566 { 7567 vmx_window_test_db_count++; 7568 } 7569 7570 static void vmx_nmi_window_test_guest(void) 7571 { 7572 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 7573 7574 asm volatile("vmcall\n\t" 7575 "nop\n\t"); 7576 7577 handle_exception(DB_VECTOR, NULL); 7578 } 7579 7580 static void verify_nmi_window_exit(u64 rip) 7581 { 7582 u32 exit_reason = vmcs_read(EXI_REASON); 7583 7584 report("Exit reason (%d) is 'NMI window'", 7585 exit_reason == VMX_NMI_WINDOW, exit_reason); 7586 report("RIP (%#lx) is %#lx", vmcs_read(GUEST_RIP) == rip, 7587 vmcs_read(GUEST_RIP), rip); 7588 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 7589 } 7590 7591 static void vmx_nmi_window_test(void) 7592 { 7593 u64 nop_addr; 7594 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 7595 7596 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 7597 report_skip("CPU does not support the \"Virtual NMIs\" VM-execution control."); 7598 return; 7599 } 7600 7601 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 7602 report_skip("CPU does not support the \"NMI-window exiting\" VM-execution control."); 7603 return; 7604 } 7605 7606 vmx_window_test_db_count = 0; 7607 7608 report_prefix_push("NMI-window"); 7609 test_set_guest(vmx_nmi_window_test_guest); 7610 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 7611 enter_guest(); 7612 skip_exit_vmcall(); 7613 nop_addr = vmcs_read(GUEST_RIP); 7614 7615 /* 7616 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 7617 * RIP will not advance. 7618 */ 7619 report_prefix_push("active, no blocking"); 7620 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 7621 enter_guest(); 7622 verify_nmi_window_exit(nop_addr); 7623 report_prefix_pop(); 7624 7625 /* 7626 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 7627 * a VM-exit on the next instruction after the nop. (The nop 7628 * is one byte.) 7629 */ 7630 report_prefix_push("active, blocking by MOV-SS"); 7631 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 7632 enter_guest(); 7633 verify_nmi_window_exit(nop_addr + 1); 7634 report_prefix_pop(); 7635 7636 /* 7637 * Ask for "NMI-window exiting" (with event injection), and 7638 * expect a VM-exit after the event is injected. (RIP should 7639 * be at the address specified in the IDT entry for #DB.) 7640 */ 7641 report_prefix_push("active, no blocking, injecting #DB"); 7642 vmcs_write(ENT_INTR_INFO, 7643 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 7644 enter_guest(); 7645 verify_nmi_window_exit((u64)db_fault_addr); 7646 report_prefix_pop(); 7647 7648 /* 7649 * Ask for "NMI-window exiting" with NMI blocking, and expect 7650 * a VM-exit after the next IRET (i.e. after the #DB handler 7651 * returns). So, RIP should be back at one byte past the nop. 7652 */ 7653 report_prefix_push("active, blocking by NMI"); 7654 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 7655 enter_guest(); 7656 verify_nmi_window_exit(nop_addr + 1); 7657 report("#DB handler executed once (actual %d times)", 7658 vmx_window_test_db_count == 1, 7659 vmx_window_test_db_count); 7660 report_prefix_pop(); 7661 7662 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 7663 report_skip("CPU does not support activity state HLT."); 7664 } else { 7665 /* 7666 * Ask for "NMI-window exiting" when entering activity 7667 * state HLT, and expect an immediate VM-exit. RIP is 7668 * still one byte past the nop. 7669 */ 7670 report_prefix_push("halted, no blocking"); 7671 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7672 enter_guest(); 7673 verify_nmi_window_exit(nop_addr + 1); 7674 report_prefix_pop(); 7675 7676 /* 7677 * Ask for "NMI-window exiting" when entering activity 7678 * state HLT (with event injection), and expect a 7679 * VM-exit after the event is injected. (RIP should be 7680 * at the address specified in the IDT entry for #DB.) 7681 */ 7682 report_prefix_push("halted, no blocking, injecting #DB"); 7683 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7684 vmcs_write(ENT_INTR_INFO, 7685 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 7686 DB_VECTOR); 7687 enter_guest(); 7688 verify_nmi_window_exit((u64)db_fault_addr); 7689 report_prefix_pop(); 7690 } 7691 7692 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 7693 enter_guest(); 7694 report_prefix_pop(); 7695 } 7696 7697 static void vmx_intr_window_test_guest(void) 7698 { 7699 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 7700 7701 /* 7702 * The two consecutive STIs are to ensure that only the first 7703 * one has a shadow. Note that NOP and STI are one byte 7704 * instructions. 7705 */ 7706 asm volatile("vmcall\n\t" 7707 "nop\n\t" 7708 "sti\n\t" 7709 "sti\n\t"); 7710 7711 handle_exception(DB_VECTOR, NULL); 7712 } 7713 7714 static void verify_intr_window_exit(u64 rip) 7715 { 7716 u32 exit_reason = vmcs_read(EXI_REASON); 7717 7718 report("Exit reason (%d) is 'interrupt window'", 7719 exit_reason == VMX_INTR_WINDOW, exit_reason); 7720 report("RIP (%#lx) is %#lx", vmcs_read(GUEST_RIP) == rip, 7721 vmcs_read(GUEST_RIP), rip); 7722 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 7723 } 7724 7725 static void vmx_intr_window_test(void) 7726 { 7727 u64 vmcall_addr; 7728 u64 nop_addr; 7729 unsigned int orig_db_gate_type; 7730 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 7731 7732 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 7733 report_skip("CPU does not support the \"interrupt-window exiting\" VM-execution control."); 7734 return; 7735 } 7736 7737 /* 7738 * Change the IDT entry for #DB from interrupt gate to trap gate, 7739 * so that it won't clear RFLAGS.IF. We don't want interrupts to 7740 * be disabled after vectoring a #DB. 7741 */ 7742 orig_db_gate_type = boot_idt[DB_VECTOR].type; 7743 boot_idt[DB_VECTOR].type = 15; 7744 7745 report_prefix_push("interrupt-window"); 7746 test_set_guest(vmx_intr_window_test_guest); 7747 enter_guest(); 7748 assert_exit_reason(VMX_VMCALL); 7749 vmcall_addr = vmcs_read(GUEST_RIP); 7750 7751 /* 7752 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 7753 * no blocking; expect an immediate VM-exit. Note that we have 7754 * not advanced past the vmcall instruction yet, so RIP should 7755 * point to the vmcall instruction. 7756 */ 7757 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 7758 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7759 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 7760 enter_guest(); 7761 verify_intr_window_exit(vmcall_addr); 7762 report_prefix_pop(); 7763 7764 /* 7765 * Ask for "interrupt-window exiting" (with event injection) 7766 * with RFLAGS.IF set and no blocking; expect a VM-exit after 7767 * the event is injected. That is, RIP should should be at the 7768 * address specified in the IDT entry for #DB. 7769 */ 7770 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #DB"); 7771 vmcs_write(ENT_INTR_INFO, 7772 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 7773 vmcall_addr = vmcs_read(GUEST_RIP); 7774 enter_guest(); 7775 verify_intr_window_exit((u64)db_fault_addr); 7776 report_prefix_pop(); 7777 7778 /* 7779 * Let the L2 guest run through the IRET, back to the VMCALL. 7780 * We have to clear the "interrupt-window exiting" 7781 * VM-execution control, or it would just keep causing 7782 * VM-exits. Then, advance past the VMCALL and set the 7783 * "interrupt-window exiting" VM-execution control again. 7784 */ 7785 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7786 enter_guest(); 7787 skip_exit_vmcall(); 7788 nop_addr = vmcs_read(GUEST_RIP); 7789 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7790 7791 /* 7792 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 7793 * RFLAGS.IF set, and expect a VM-exit on the next 7794 * instruction. (NOP is one byte.) 7795 */ 7796 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 7797 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 7798 enter_guest(); 7799 verify_intr_window_exit(nop_addr + 1); 7800 report_prefix_pop(); 7801 7802 /* 7803 * Back up to the NOP and ask for "interrupt-window exiting" 7804 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 7805 * on the next instruction. (NOP is one byte.) 7806 */ 7807 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 7808 vmcs_write(GUEST_RIP, nop_addr); 7809 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 7810 enter_guest(); 7811 verify_intr_window_exit(nop_addr + 1); 7812 report_prefix_pop(); 7813 7814 /* 7815 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 7816 * and expect a VM-exit on the instruction following the STI 7817 * shadow. Only the first STI (which is one byte past the NOP) 7818 * should have a shadow. The second STI (which is two bytes 7819 * past the NOP) has no shadow. Therefore, the interrupt 7820 * window opens at three bytes past the NOP. 7821 */ 7822 report_prefix_push("active, RFLAGS.IF = 0"); 7823 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 7824 enter_guest(); 7825 verify_intr_window_exit(nop_addr + 3); 7826 report_prefix_pop(); 7827 7828 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 7829 report_skip("CPU does not support activity state HLT."); 7830 } else { 7831 /* 7832 * Ask for "interrupt-window exiting" when entering 7833 * activity state HLT, and expect an immediate 7834 * VM-exit. RIP is still three bytes past the nop. 7835 */ 7836 report_prefix_push("halted, no blocking"); 7837 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7838 enter_guest(); 7839 verify_intr_window_exit(nop_addr + 3); 7840 report_prefix_pop(); 7841 7842 /* 7843 * Ask for "interrupt-window exiting" when entering 7844 * activity state HLT (with event injection), and 7845 * expect a VM-exit after the event is injected. That 7846 * is, RIP should should be at the address specified 7847 * in the IDT entry for #DB. 7848 */ 7849 report_prefix_push("halted, no blocking, injecting #DB"); 7850 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7851 vmcs_write(ENT_INTR_INFO, 7852 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 7853 DB_VECTOR); 7854 enter_guest(); 7855 verify_intr_window_exit((u64)db_fault_addr); 7856 report_prefix_pop(); 7857 } 7858 7859 boot_idt[DB_VECTOR].type = orig_db_gate_type; 7860 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7861 enter_guest(); 7862 report_prefix_pop(); 7863 } 7864 7865 #define GUEST_TSC_OFFSET (1u << 30) 7866 7867 static u64 guest_tsc; 7868 7869 static void vmx_store_tsc_test_guest(void) 7870 { 7871 guest_tsc = rdtsc(); 7872 } 7873 7874 /* 7875 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 7876 * list, the value saved is not subject to the TSC offset that is 7877 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 7878 */ 7879 static void vmx_store_tsc_test(void) 7880 { 7881 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 7882 u64 low, high; 7883 7884 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 7885 report_skip("'Use TSC offsetting' not supported"); 7886 return; 7887 } 7888 7889 test_set_guest(vmx_store_tsc_test_guest); 7890 7891 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 7892 vmcs_write(EXI_MSR_ST_CNT, 1); 7893 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 7894 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 7895 7896 low = rdtsc(); 7897 enter_guest(); 7898 high = rdtsc(); 7899 7900 report("RDTSC value in the guest (%lu) is in range [%lu, %lu]", 7901 low + GUEST_TSC_OFFSET <= guest_tsc && 7902 guest_tsc <= high + GUEST_TSC_OFFSET, 7903 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 7904 report("IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 7905 low <= msr_entry.value && msr_entry.value <= high, 7906 msr_entry.value, low, high); 7907 } 7908 7909 static void vmx_db_test_guest(void) 7910 { 7911 /* 7912 * For a hardware generated single-step #DB. 7913 */ 7914 asm volatile("vmcall;" 7915 "nop;" 7916 ".Lpost_nop:"); 7917 /* 7918 * ...in a MOVSS shadow, with pending debug exceptions. 7919 */ 7920 asm volatile("vmcall;" 7921 "nop;" 7922 ".Lpost_movss_nop:"); 7923 /* 7924 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 7925 * emulates it in software.) 7926 */ 7927 asm volatile("vmcall;" 7928 "wbinvd;" 7929 ".Lpost_wbinvd:"); 7930 /* 7931 * ...in a MOVSS shadow, with pending debug exceptions. 7932 */ 7933 asm volatile("vmcall;" 7934 "wbinvd;" 7935 ".Lpost_movss_wbinvd:"); 7936 /* 7937 * For a hardware generated single-step #DB in a transactional region. 7938 */ 7939 asm volatile("vmcall;" 7940 ".Lxbegin: xbegin .Lskip_rtm;" 7941 "xend;" 7942 ".Lskip_rtm:"); 7943 } 7944 7945 /* 7946 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 7947 * L2. No #DB is delivered and L2 continues to the next point of 7948 * interest. 7949 */ 7950 static void dismiss_db(void) 7951 { 7952 vmcs_write(GUEST_PENDING_DEBUG, 0); 7953 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 7954 enter_guest(); 7955 } 7956 7957 /* 7958 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 7959 * Then throw away the #DB exception and resume L2. 7960 */ 7961 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 7962 void *expected_rip, u64 expected_exit_qual, 7963 u64 expected_dr6) 7964 { 7965 u32 reason = vmcs_read(EXI_REASON); 7966 u32 intr_info = vmcs_read(EXI_INTR_INFO); 7967 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 7968 u64 guest_rip = vmcs_read(GUEST_RIP); 7969 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 7970 u64 dr6 = read_dr6(); 7971 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 7972 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 7973 7974 report("Expected #DB VM-exit", 7975 reason == VMX_EXC_NMI && intr_info == expected_intr_info); 7976 report("Expected RIP %p (actual %lx)", (u64)expected_rip == guest_rip, 7977 expected_rip, guest_rip); 7978 report_xfail("Expected pending debug exceptions 0 (actual %lx)", 7979 xfail_pdbg, 0 == guest_pending_dbg, guest_pending_dbg); 7980 report_xfail("Expected exit qualification %lx (actual %lx)", xfail_qual, 7981 expected_exit_qual == exit_qual, 7982 expected_exit_qual, exit_qual); 7983 report_xfail("Expected DR6 %lx (actual %lx)", xfail_dr6, 7984 expected_dr6 == dr6, expected_dr6, dr6); 7985 dismiss_db(); 7986 } 7987 7988 /* 7989 * Assuming the guest has just exited on a VMCALL instruction, skip 7990 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 7991 * pending debug exceptions are non-zero, set the VMCS up as if the 7992 * previous instruction was a MOVSS that generated the indicated 7993 * pending debug exceptions. Then enter L2. 7994 */ 7995 static void single_step_guest(const char *test_name, u64 starting_dr6, 7996 u64 pending_debug_exceptions) 7997 { 7998 printf("\n%s\n", test_name); 7999 skip_exit_vmcall(); 8000 write_dr6(starting_dr6); 8001 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 8002 if (pending_debug_exceptions) { 8003 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 8004 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8005 } 8006 enter_guest(); 8007 } 8008 8009 /* 8010 * When L1 intercepts #DB, verify that a single-step trap clears 8011 * pending debug exceptions, populates the exit qualification field 8012 * properly, and that DR6 is not prematurely clobbered. In a 8013 * (simulated) MOVSS shadow, make sure that the pending debug 8014 * exception bits are properly accumulated into the exit qualification 8015 * field. 8016 */ 8017 static void vmx_db_test(void) 8018 { 8019 /* 8020 * We are going to set a few arbitrary bits in DR6 to verify that 8021 * (a) DR6 is not modified by an intercepted #DB, and 8022 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 8023 * the exit qualification field for a subsequent #DB exception. 8024 */ 8025 const u64 starting_dr6 = DR6_RESERVED | BIT(13) | DR_TRAP3 | DR_TRAP1; 8026 extern char post_nop asm(".Lpost_nop"); 8027 extern char post_movss_nop asm(".Lpost_movss_nop"); 8028 extern char post_wbinvd asm(".Lpost_wbinvd"); 8029 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 8030 extern char xbegin asm(".Lxbegin"); 8031 extern char skip_rtm asm(".Lskip_rtm"); 8032 8033 /* 8034 * L1 wants to intercept #DB exceptions encountered in L2. 8035 */ 8036 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 8037 8038 /* 8039 * Start L2 and run it up to the first point of interest. 8040 */ 8041 test_set_guest(vmx_db_test_guest); 8042 enter_guest(); 8043 8044 /* 8045 * Hardware-delivered #DB trap for single-step sets the 8046 * standard that L0 has to follow for emulated instructions. 8047 */ 8048 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 8049 check_db_exit(false, false, false, &post_nop, DR_STEP, starting_dr6); 8050 8051 /* 8052 * Hardware-delivered #DB trap for single-step in MOVSS shadow 8053 * also sets the standard that L0 has to follow for emulated 8054 * instructions. Here, we establish the VMCS pending debug 8055 * exceptions to indicate that the simulated MOVSS triggered a 8056 * data breakpoint as well as the single-step trap. 8057 */ 8058 single_step_guest("Hardware delivered single-step in MOVSS shadow", 8059 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0 ); 8060 check_db_exit(false, false, false, &post_movss_nop, DR_STEP | DR_TRAP0, 8061 starting_dr6); 8062 8063 /* 8064 * L0 synthesized #DB trap for single-step is buggy, because 8065 * kvm (a) clobbers DR6 too early, and (b) tries its best to 8066 * reconstitute the exit qualification from the prematurely 8067 * modified DR6, but fails miserably. 8068 */ 8069 single_step_guest("Software synthesized single-step", starting_dr6, 0); 8070 check_db_exit(true, true, false, &post_wbinvd, DR_STEP, starting_dr6); 8071 8072 /* 8073 * L0 synthesized #DB trap for single-step in MOVSS shadow is 8074 * even worse, because L0 also leaves the pending debug 8075 * exceptions in the VMCS instead of accumulating them into 8076 * the exit qualification field for the #DB exception. 8077 */ 8078 single_step_guest("Software synthesized single-step in MOVSS shadow", 8079 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0); 8080 check_db_exit(true, true, true, &post_movss_wbinvd, DR_STEP | DR_TRAP0, 8081 starting_dr6); 8082 8083 /* 8084 * Optional RTM test for hardware that supports RTM, to 8085 * demonstrate that the current volume 3 of the SDM 8086 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 8087 * qualification for debug exceptions is not reserved. It is 8088 * set to 1 if a debug exception (#DB) or a breakpoint 8089 * exception (#BP) occurs inside an RTM region while advanced 8090 * debugging of RTM transactional regions is enabled. 8091 */ 8092 if (this_cpu_has(X86_FEATURE_RTM)) { 8093 vmcs_write(ENT_CONTROLS, 8094 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 8095 /* 8096 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 8097 * in the guest to enable advanced debugging of RTM 8098 * transactional regions. 8099 */ 8100 vmcs_write(GUEST_DR7, BIT(11)); 8101 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 8102 single_step_guest("Hardware delivered single-step in " 8103 "transactional region", starting_dr6, 0); 8104 check_db_exit(false, false, false, &xbegin, BIT(16), 8105 starting_dr6); 8106 } else { 8107 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 8108 enter_guest(); 8109 } 8110 } 8111 8112 static void enable_vid(void) 8113 { 8114 void *virtual_apic_page; 8115 8116 assert(cpu_has_apicv()); 8117 8118 disable_intercept_for_x2apic_msrs(); 8119 8120 virtual_apic_page = alloc_page(); 8121 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 8122 8123 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 8124 8125 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 8126 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 8127 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 8128 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 8129 8130 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 8131 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 8132 } 8133 8134 static void trigger_ioapic_scan_thread(void *data) 8135 { 8136 /* Wait until other CPU entered L2 */ 8137 while (vmx_get_test_stage() != 1) 8138 ; 8139 8140 /* Trigger ioapic scan */ 8141 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 8142 vmx_set_test_stage(2); 8143 } 8144 8145 static void irq_79_handler_guest(isr_regs_t *regs) 8146 { 8147 eoi(); 8148 8149 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 8150 vmcall(); 8151 } 8152 8153 /* 8154 * Constant for num of busy-loop iterations after which 8155 * a timer interrupt should have happened in host 8156 */ 8157 #define TIMER_INTERRUPT_DELAY 100000000 8158 8159 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 8160 { 8161 handle_irq(0x79, irq_79_handler_guest); 8162 irq_enable(); 8163 8164 /* Signal to L1 CPU to trigger ioapic scan */ 8165 vmx_set_test_stage(1); 8166 /* Wait until L1 CPU to trigger ioapic scan */ 8167 while (vmx_get_test_stage() != 2) 8168 ; 8169 8170 /* 8171 * Wait for L0 timer interrupt to be raised while we run in L2 8172 * such that L0 will process the IOAPIC scan request before 8173 * resuming L2 8174 */ 8175 delay(TIMER_INTERRUPT_DELAY); 8176 8177 asm volatile ("int $0x79"); 8178 } 8179 8180 static void vmx_eoi_bitmap_ioapic_scan_test(void) 8181 { 8182 if (!cpu_has_apicv() || (cpu_count() < 2)) { 8183 report_skip(__func__); 8184 return; 8185 } 8186 8187 enable_vid(); 8188 8189 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 8190 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 8191 8192 /* 8193 * Launch L2. 8194 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 8195 * In case the reason isn't VMX_VMCALL, the asserion inside 8196 * skip_exit_vmcall() will fail. 8197 */ 8198 enter_guest(); 8199 skip_exit_vmcall(); 8200 8201 /* Let L2 finish */ 8202 enter_guest(); 8203 report(__func__, 1); 8204 } 8205 8206 #define HLT_WITH_RVI_VECTOR (0xf1) 8207 8208 bool vmx_hlt_with_rvi_guest_isr_fired; 8209 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 8210 { 8211 vmx_hlt_with_rvi_guest_isr_fired = true; 8212 eoi(); 8213 } 8214 8215 static void vmx_hlt_with_rvi_guest(void) 8216 { 8217 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 8218 8219 irq_enable(); 8220 asm volatile ("nop"); 8221 8222 vmcall(); 8223 } 8224 8225 static void vmx_hlt_with_rvi_test(void) 8226 { 8227 if (!cpu_has_apicv()) { 8228 report_skip(__func__); 8229 return; 8230 } 8231 8232 enable_vid(); 8233 8234 vmx_hlt_with_rvi_guest_isr_fired = false; 8235 test_set_guest(vmx_hlt_with_rvi_guest); 8236 8237 enter_guest(); 8238 skip_exit_vmcall(); 8239 8240 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8241 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 8242 enter_guest(); 8243 8244 report("Interrupt raised in guest", vmx_hlt_with_rvi_guest_isr_fired); 8245 } 8246 8247 static void set_irq_line_thread(void *data) 8248 { 8249 /* Wait until other CPU entered L2 */ 8250 while (vmx_get_test_stage() != 1) 8251 ; 8252 8253 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 8254 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 8255 vmx_set_test_stage(2); 8256 } 8257 8258 static bool irq_78_handler_vmcall_before_eoi; 8259 static void irq_78_handler_guest(isr_regs_t *regs) 8260 { 8261 set_irq_line(0xf, 0); 8262 if (irq_78_handler_vmcall_before_eoi) 8263 vmcall(); 8264 eoi(); 8265 vmcall(); 8266 } 8267 8268 static void vmx_apic_passthrough_guest(void) 8269 { 8270 handle_irq(0x78, irq_78_handler_guest); 8271 irq_enable(); 8272 8273 /* If requested, wait for other CPU to trigger ioapic scan */ 8274 if (vmx_get_test_stage() < 1) { 8275 vmx_set_test_stage(1); 8276 while (vmx_get_test_stage() != 2) 8277 ; 8278 } 8279 8280 set_irq_line(0xf, 1); 8281 } 8282 8283 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 8284 { 8285 if (set_irq_line_from_thread && (cpu_count() < 2)) { 8286 report_skip(__func__); 8287 return; 8288 } 8289 8290 /* Test device is required for generating IRQs */ 8291 if (!test_device_enabled()) { 8292 report_skip(__func__); 8293 return; 8294 } 8295 u64 cpu_ctrl_0 = CPU_SECONDARY; 8296 u64 cpu_ctrl_1 = 0; 8297 8298 disable_intercept_for_x2apic_msrs(); 8299 8300 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 8301 8302 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 8303 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 8304 8305 if (set_irq_line_from_thread) { 8306 irq_78_handler_vmcall_before_eoi = false; 8307 on_cpu_async(1, set_irq_line_thread, NULL); 8308 } else { 8309 irq_78_handler_vmcall_before_eoi = true; 8310 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 8311 vmx_set_test_stage(2); 8312 } 8313 test_set_guest(vmx_apic_passthrough_guest); 8314 8315 if (irq_78_handler_vmcall_before_eoi) { 8316 /* Before EOI remote_irr should still be set */ 8317 enter_guest(); 8318 skip_exit_vmcall(); 8319 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 8320 "IOAPIC pass-through: remote_irr=1 before EOI"); 8321 } 8322 8323 /* After EOI remote_irr should be cleared */ 8324 enter_guest(); 8325 skip_exit_vmcall(); 8326 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 8327 "IOAPIC pass-through: remote_irr=0 after EOI"); 8328 8329 /* Let L2 finish */ 8330 enter_guest(); 8331 report(__func__, 1); 8332 } 8333 8334 static void vmx_apic_passthrough_test(void) 8335 { 8336 vmx_apic_passthrough(false); 8337 } 8338 8339 static void vmx_apic_passthrough_thread_test(void) 8340 { 8341 vmx_apic_passthrough(true); 8342 } 8343 8344 static void vmx_apic_passthrough_tpr_threshold_guest(void) 8345 { 8346 cli(); 8347 apic_set_tpr(0); 8348 } 8349 8350 static bool vmx_apic_passthrough_tpr_threshold_ipi_isr_fired; 8351 static void vmx_apic_passthrough_tpr_threshold_ipi_isr(isr_regs_t *regs) 8352 { 8353 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = true; 8354 eoi(); 8355 } 8356 8357 static void vmx_apic_passthrough_tpr_threshold_test(void) 8358 { 8359 int ipi_vector = 0xe1; 8360 8361 disable_intercept_for_x2apic_msrs(); 8362 vmcs_clear_bits(PIN_CONTROLS, PIN_EXTINT); 8363 8364 /* Raise L0 TPR-threshold by queueing vector in LAPIC IRR */ 8365 cli(); 8366 apic_set_tpr((ipi_vector >> 4) + 1); 8367 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 8368 APIC_DM_FIXED | ipi_vector, 8369 0); 8370 8371 test_set_guest(vmx_apic_passthrough_tpr_threshold_guest); 8372 enter_guest(); 8373 8374 report("TPR was zero by guest", apic_get_tpr() == 0); 8375 8376 /* Clean pending self-IPI */ 8377 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = false; 8378 handle_irq(ipi_vector, vmx_apic_passthrough_tpr_threshold_ipi_isr); 8379 sti(); 8380 asm volatile ("nop"); 8381 report("self-IPI fired", vmx_apic_passthrough_tpr_threshold_ipi_isr_fired); 8382 8383 report(__func__, 1); 8384 } 8385 8386 static u64 init_signal_test_exit_reason; 8387 static bool init_signal_test_thread_continued; 8388 8389 static void init_signal_test_thread(void *data) 8390 { 8391 struct vmcs *test_vmcs = data; 8392 8393 /* Enter VMX operation (i.e. exec VMXON) */ 8394 u64 *ap_vmxon_region = alloc_page(); 8395 enable_vmx(); 8396 init_vmx(ap_vmxon_region); 8397 _vmx_on(ap_vmxon_region); 8398 8399 /* Signal CPU have entered VMX operation */ 8400 vmx_set_test_stage(1); 8401 8402 /* Wait for BSP CPU to send INIT signal */ 8403 while (vmx_get_test_stage() != 2) 8404 ; 8405 8406 /* 8407 * Signal that we continue as usual as INIT signal 8408 * should be blocked while CPU is in VMX operation 8409 */ 8410 vmx_set_test_stage(3); 8411 8412 /* Wait for signal to enter VMX non-root mode */ 8413 while (vmx_get_test_stage() != 4) 8414 ; 8415 8416 /* Enter VMX non-root mode */ 8417 test_set_guest(v2_null_test_guest); 8418 make_vmcs_current(test_vmcs); 8419 enter_guest(); 8420 /* Save exit reason for BSP CPU to compare to expected result */ 8421 init_signal_test_exit_reason = vmcs_read(EXI_REASON); 8422 /* VMCLEAR test-vmcs so it could be loaded by BSP CPU */ 8423 vmcs_clear(test_vmcs); 8424 launched = false; 8425 /* Signal that CPU exited to VMX root mode */ 8426 vmx_set_test_stage(5); 8427 8428 /* Wait for signal to exit VMX operation */ 8429 while (vmx_get_test_stage() != 6) 8430 ; 8431 8432 /* Exit VMX operation (i.e. exec VMXOFF) */ 8433 vmx_off(); 8434 8435 /* 8436 * Exiting VMX operation should result in latched 8437 * INIT signal being processed. Therefore, we should 8438 * never reach the below code. Thus, signal to BSP 8439 * CPU if we have reached here so it is able to 8440 * report an issue if it happens. 8441 */ 8442 init_signal_test_thread_continued = true; 8443 } 8444 8445 #define INIT_SIGNAL_TEST_DELAY 100000000ULL 8446 8447 static void vmx_init_signal_test(void) 8448 { 8449 struct vmcs *test_vmcs; 8450 8451 if (cpu_count() < 2) { 8452 report_skip(__func__); 8453 return; 8454 } 8455 8456 /* VMCLEAR test-vmcs so it could be loaded by other CPU */ 8457 vmcs_save(&test_vmcs); 8458 vmcs_clear(test_vmcs); 8459 8460 vmx_set_test_stage(0); 8461 on_cpu_async(1, init_signal_test_thread, test_vmcs); 8462 8463 /* Wait for other CPU to enter VMX operation */ 8464 while (vmx_get_test_stage() != 1) 8465 ; 8466 8467 /* Send INIT signal to other CPU */ 8468 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 8469 id_map[1]); 8470 /* Signal other CPU we have sent INIT signal */ 8471 vmx_set_test_stage(2); 8472 8473 /* 8474 * Wait reasonable amount of time for INIT signal to 8475 * be received on other CPU and verify that other CPU 8476 * have proceed as usual to next test stage as INIT 8477 * signal should be blocked while other CPU in 8478 * VMX operation 8479 */ 8480 delay(INIT_SIGNAL_TEST_DELAY); 8481 report("INIT signal blocked when CPU in VMX operation", 8482 vmx_get_test_stage() == 3); 8483 /* No point to continue if we failed at this point */ 8484 if (vmx_get_test_stage() != 3) 8485 return; 8486 8487 /* Signal other CPU to enter VMX non-root mode */ 8488 init_signal_test_exit_reason = -1ull; 8489 vmx_set_test_stage(4); 8490 /* 8491 * Wait reasonable amont of time for other CPU 8492 * to exit to VMX root mode 8493 */ 8494 delay(INIT_SIGNAL_TEST_DELAY); 8495 if (vmx_get_test_stage() != 5) { 8496 report("Pending INIT signal didn't result in VMX exit", false); 8497 return; 8498 } 8499 report("INIT signal during VMX non-root mode result in exit-reason %s (%lu)", 8500 init_signal_test_exit_reason == VMX_INIT, 8501 exit_reason_description(init_signal_test_exit_reason), 8502 init_signal_test_exit_reason); 8503 8504 /* Run guest to completion */ 8505 make_vmcs_current(test_vmcs); 8506 enter_guest(); 8507 8508 /* Signal other CPU to exit VMX operation */ 8509 init_signal_test_thread_continued = false; 8510 vmx_set_test_stage(6); 8511 8512 /* 8513 * Wait reasonable amount of time for other CPU 8514 * to run after INIT signal was processed 8515 */ 8516 delay(INIT_SIGNAL_TEST_DELAY); 8517 report("INIT signal processed after exit VMX operation", 8518 !init_signal_test_thread_continued); 8519 8520 /* 8521 * TODO: Send SIPI to other CPU to sipi_entry (See x86/cstart64.S) 8522 * to re-init it to kvm-unit-tests standard environment. 8523 * Somehow (?) verify that SIPI was indeed received. 8524 */ 8525 } 8526 8527 enum vmcs_access { 8528 ACCESS_VMREAD, 8529 ACCESS_VMWRITE, 8530 ACCESS_NONE, 8531 }; 8532 8533 struct vmcs_shadow_test_common { 8534 enum vmcs_access op; 8535 enum Reason reason; 8536 u64 field; 8537 u64 value; 8538 u64 flags; 8539 u64 time; 8540 } l1_l2_common; 8541 8542 static inline u64 vmread_flags(u64 field, u64 *val) 8543 { 8544 u64 flags; 8545 8546 asm volatile ("vmread %2, %1; pushf; pop %0" 8547 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 8548 return flags & X86_EFLAGS_ALU; 8549 } 8550 8551 static inline u64 vmwrite_flags(u64 field, u64 val) 8552 { 8553 u64 flags; 8554 8555 asm volatile ("vmwrite %1, %2; pushf; pop %0" 8556 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 8557 return flags & X86_EFLAGS_ALU; 8558 } 8559 8560 static void vmx_vmcs_shadow_test_guest(void) 8561 { 8562 struct vmcs_shadow_test_common *c = &l1_l2_common; 8563 u64 start; 8564 8565 while (c->op != ACCESS_NONE) { 8566 start = rdtsc(); 8567 switch (c->op) { 8568 default: 8569 c->flags = -1ull; 8570 break; 8571 case ACCESS_VMREAD: 8572 c->flags = vmread_flags(c->field, &c->value); 8573 break; 8574 case ACCESS_VMWRITE: 8575 c->flags = vmwrite_flags(c->field, 0); 8576 break; 8577 } 8578 c->time = rdtsc() - start; 8579 vmcall(); 8580 } 8581 } 8582 8583 static u64 vmread_from_shadow(u64 field) 8584 { 8585 struct vmcs *primary; 8586 struct vmcs *shadow; 8587 u64 value; 8588 8589 TEST_ASSERT(!vmcs_save(&primary)); 8590 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 8591 TEST_ASSERT(!make_vmcs_current(shadow)); 8592 value = vmcs_read(field); 8593 TEST_ASSERT(!make_vmcs_current(primary)); 8594 return value; 8595 } 8596 8597 static u64 vmwrite_to_shadow(u64 field, u64 value) 8598 { 8599 struct vmcs *primary; 8600 struct vmcs *shadow; 8601 8602 TEST_ASSERT(!vmcs_save(&primary)); 8603 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 8604 TEST_ASSERT(!make_vmcs_current(shadow)); 8605 vmcs_write(field, value); 8606 value = vmcs_read(field); 8607 TEST_ASSERT(!make_vmcs_current(primary)); 8608 return value; 8609 } 8610 8611 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 8612 { 8613 struct vmcs_shadow_test_common *c = &l1_l2_common; 8614 8615 c->op = access; 8616 vmcs_write(VMX_INST_ERROR, 0); 8617 enter_guest(); 8618 c->reason = vmcs_read(EXI_REASON) & 0xffff; 8619 if (c->reason != VMX_VMCALL) { 8620 skip_exit_insn(); 8621 enter_guest(); 8622 } 8623 skip_exit_vmcall(); 8624 } 8625 8626 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 8627 { 8628 struct vmcs_shadow_test_common *c = &l1_l2_common; 8629 struct vmcs *shadow; 8630 u64 value; 8631 uintptr_t flags[2]; 8632 bool good_shadow; 8633 u32 vmx_inst_error; 8634 8635 report_prefix_pushf("field %lx", field); 8636 c->field = field; 8637 8638 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 8639 if (shadow != (struct vmcs *)-1ull) { 8640 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 8641 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 8642 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 8643 } else { 8644 /* 8645 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 8646 * shadowed-fields should fail with setting RFLAGS.CF. 8647 */ 8648 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 8649 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 8650 good_shadow = false; 8651 } 8652 8653 /* Intercept both VMREAD and VMWRITE. */ 8654 report_prefix_push("no VMREAD/VMWRITE permission"); 8655 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 8656 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 8657 set_bit(field, bitmap[ACCESS_VMREAD]); 8658 set_bit(field, bitmap[ACCESS_VMWRITE]); 8659 } 8660 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 8661 report("not shadowed for VMWRITE", c->reason == VMX_VMWRITE); 8662 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 8663 report("not shadowed for VMREAD", c->reason == VMX_VMREAD); 8664 report_prefix_pop(); 8665 8666 if (field >> VMCS_FIELD_RESERVED_SHIFT) 8667 goto out; 8668 8669 /* Permit shadowed VMREAD. */ 8670 report_prefix_push("VMREAD permission only"); 8671 clear_bit(field, bitmap[ACCESS_VMREAD]); 8672 set_bit(field, bitmap[ACCESS_VMWRITE]); 8673 if (good_shadow) 8674 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 8675 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 8676 report("not shadowed for VMWRITE", c->reason == VMX_VMWRITE); 8677 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 8678 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 8679 report("shadowed for VMREAD (in %ld cycles)", c->reason == VMX_VMCALL, 8680 c->time); 8681 report("ALU flags after VMREAD (%lx) are as expected (%lx)", 8682 c->flags == flags[ACCESS_VMREAD], 8683 c->flags, flags[ACCESS_VMREAD]); 8684 if (good_shadow) 8685 report("value read from shadow (%lx) is as expected (%lx)", 8686 c->value == value, c->value, value); 8687 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 8688 report("VMX_INST_ERROR (%d) is as expected (%d)", 8689 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 8690 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 8691 report_prefix_pop(); 8692 8693 /* Permit shadowed VMWRITE. */ 8694 report_prefix_push("VMWRITE permission only"); 8695 set_bit(field, bitmap[ACCESS_VMREAD]); 8696 clear_bit(field, bitmap[ACCESS_VMWRITE]); 8697 if (good_shadow) 8698 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 8699 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 8700 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 8701 report("shadowed for VMWRITE (in %ld cycles)", c->reason == VMX_VMCALL, 8702 c->time); 8703 report("ALU flags after VMWRITE (%lx) are as expected (%lx)", 8704 c->flags == flags[ACCESS_VMREAD], 8705 c->flags, flags[ACCESS_VMREAD]); 8706 if (good_shadow) { 8707 value = vmread_from_shadow(field); 8708 report("shadow VMCS value (%lx) is as expected (%lx)", 8709 value == 0, value, 0ul); 8710 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 8711 report("VMX_INST_ERROR (%d) is as expected (%d)", 8712 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 8713 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 8714 } 8715 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 8716 report("not shadowed for VMREAD", c->reason == VMX_VMREAD); 8717 report_prefix_pop(); 8718 8719 /* Permit shadowed VMREAD and VMWRITE. */ 8720 report_prefix_push("VMREAD and VMWRITE permission"); 8721 clear_bit(field, bitmap[ACCESS_VMREAD]); 8722 clear_bit(field, bitmap[ACCESS_VMWRITE]); 8723 if (good_shadow) 8724 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 8725 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 8726 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 8727 report("shadowed for VMWRITE (in %ld cycles)", c->reason == VMX_VMCALL, 8728 c->time); 8729 report("ALU flags after VMWRITE (%lx) are as expected (%lx)", 8730 c->flags == flags[ACCESS_VMREAD], 8731 c->flags, flags[ACCESS_VMREAD]); 8732 if (good_shadow) { 8733 value = vmread_from_shadow(field); 8734 report("shadow VMCS value (%lx) is as expected (%lx)", 8735 value == 0, value, 0ul); 8736 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 8737 report("VMX_INST_ERROR (%d) is as expected (%d)", 8738 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 8739 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 8740 } 8741 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 8742 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 8743 report("shadowed for VMREAD (in %ld cycles)", c->reason == VMX_VMCALL, 8744 c->time); 8745 report("ALU flags after VMREAD (%lx) are as expected (%lx)", 8746 c->flags == flags[ACCESS_VMREAD], 8747 c->flags, flags[ACCESS_VMREAD]); 8748 if (good_shadow) 8749 report("value read from shadow (%lx) is as expected (%lx)", 8750 c->value == 0, c->value, 0ul); 8751 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 8752 report("VMX_INST_ERROR (%d) is as expected (%d)", 8753 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 8754 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 8755 report_prefix_pop(); 8756 8757 out: 8758 report_prefix_pop(); 8759 } 8760 8761 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 8762 { 8763 unsigned base; 8764 unsigned index; 8765 unsigned bit; 8766 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 8767 8768 /* Run test on all possible valid VMCS fields */ 8769 for (base = 0; 8770 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 8771 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 8772 for (index = 0; index <= highest_index; index++) 8773 vmcs_shadow_test_field(bitmap, base + index); 8774 8775 /* 8776 * Run tests on some invalid VMCS fields 8777 * (Have reserved bit set). 8778 */ 8779 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 8780 vmcs_shadow_test_field(bitmap, (1ull << bit)); 8781 } 8782 8783 static void vmx_vmcs_shadow_test(void) 8784 { 8785 u8 *bitmap[2]; 8786 struct vmcs *shadow; 8787 8788 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 8789 printf("\t'Activate secondary controls' not supported.\n"); 8790 return; 8791 } 8792 8793 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 8794 printf("\t'VMCS shadowing' not supported.\n"); 8795 return; 8796 } 8797 8798 if (!(rdmsr(MSR_IA32_VMX_MISC) & 8799 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 8800 printf("\tVMWRITE can't modify VM-exit information fields.\n"); 8801 return; 8802 } 8803 8804 test_set_guest(vmx_vmcs_shadow_test_guest); 8805 8806 bitmap[ACCESS_VMREAD] = alloc_page(); 8807 bitmap[ACCESS_VMWRITE] = alloc_page(); 8808 8809 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 8810 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 8811 8812 shadow = alloc_page(); 8813 shadow->hdr.revision_id = basic.revision; 8814 shadow->hdr.shadow_vmcs = 1; 8815 TEST_ASSERT(!vmcs_clear(shadow)); 8816 8817 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 8818 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 8819 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 8820 8821 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 8822 report_prefix_push("valid link pointer"); 8823 vmx_vmcs_shadow_test_body(bitmap); 8824 report_prefix_pop(); 8825 8826 vmcs_write(VMCS_LINK_PTR, -1ull); 8827 report_prefix_push("invalid link pointer"); 8828 vmx_vmcs_shadow_test_body(bitmap); 8829 report_prefix_pop(); 8830 8831 l1_l2_common.op = ACCESS_NONE; 8832 enter_guest(); 8833 } 8834 8835 8836 8837 static int invalid_msr_init(struct vmcs *vmcs) 8838 { 8839 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8840 printf("\tPreemption timer is not supported\n"); 8841 return VMX_TEST_EXIT; 8842 } 8843 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 8844 preempt_val = 10000000; 8845 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 8846 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 8847 8848 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 8849 printf("\tSave preemption value is not supported\n"); 8850 8851 vmcs_write(ENT_MSR_LD_CNT, 1); 8852 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 8853 8854 return VMX_TEST_START; 8855 } 8856 8857 8858 static void invalid_msr_main(void) 8859 { 8860 report("Invalid MSR load", 0); 8861 } 8862 8863 static int invalid_msr_exit_handler(void) 8864 { 8865 report("Invalid MSR load", 0); 8866 print_vmexit_info(); 8867 return VMX_TEST_EXIT; 8868 } 8869 8870 static int invalid_msr_entry_failure(struct vmentry_failure *failure) 8871 { 8872 ulong reason; 8873 8874 reason = vmcs_read(EXI_REASON); 8875 report("Invalid MSR load", reason == (0x80000000u | VMX_FAIL_MSR)); 8876 return VMX_TEST_VMEXIT; 8877 } 8878 8879 /* 8880 * The max number of MSRs in an atomic switch MSR list is: 8881 * (111B + 1) * 512 = 4096 8882 * 8883 * Each list entry consumes: 8884 * 4-byte MSR index + 4 bytes reserved + 8-byte data = 16 bytes 8885 * 8886 * Allocate 128 kB to cover max_msr_list_size (i.e., 64 kB) and then some. 8887 */ 8888 static const u32 msr_list_page_order = 5; 8889 8890 static void atomic_switch_msr_limit_test_guest(void) 8891 { 8892 vmcall(); 8893 } 8894 8895 static void populate_msr_list(struct vmx_msr_entry *msr_list, 8896 size_t byte_capacity, int count) 8897 { 8898 int i; 8899 8900 for (i = 0; i < count; i++) { 8901 msr_list[i].index = MSR_IA32_TSC; 8902 msr_list[i].reserved = 0; 8903 msr_list[i].value = 0x1234567890abcdef; 8904 } 8905 8906 memset(msr_list + count, 0xff, 8907 byte_capacity - count * sizeof(*msr_list)); 8908 } 8909 8910 static int max_msr_list_size(void) 8911 { 8912 u32 vmx_misc = rdmsr(MSR_IA32_VMX_MISC); 8913 u32 factor = ((vmx_misc & GENMASK(27, 25)) >> 25) + 1; 8914 8915 return factor * 512; 8916 } 8917 8918 static void atomic_switch_msrs_test(int count) 8919 { 8920 struct vmx_msr_entry *vm_enter_load; 8921 struct vmx_msr_entry *vm_exit_load; 8922 struct vmx_msr_entry *vm_exit_store; 8923 int max_allowed = max_msr_list_size(); 8924 int byte_capacity = 1ul << (msr_list_page_order + PAGE_SHIFT); 8925 /* Exceeding the max MSR list size at exit trigers KVM to abort. */ 8926 int exit_count = count > max_allowed ? max_allowed : count; 8927 int cleanup_count = count > max_allowed ? 2 : 1; 8928 int i; 8929 8930 /* 8931 * Check for the IA32_TSC MSR, 8932 * available with the "TSC flag" and used to populate the MSR lists. 8933 */ 8934 if (!(cpuid(1).d & (1 << 4))) { 8935 report_skip(__func__); 8936 return; 8937 } 8938 8939 /* Set L2 guest. */ 8940 test_set_guest(atomic_switch_msr_limit_test_guest); 8941 8942 /* Setup atomic MSR switch lists. */ 8943 vm_enter_load = alloc_pages(msr_list_page_order); 8944 vm_exit_load = alloc_pages(msr_list_page_order); 8945 vm_exit_store = alloc_pages(msr_list_page_order); 8946 8947 vmcs_write(ENTER_MSR_LD_ADDR, (u64)vm_enter_load); 8948 vmcs_write(EXIT_MSR_LD_ADDR, (u64)vm_exit_load); 8949 vmcs_write(EXIT_MSR_ST_ADDR, (u64)vm_exit_store); 8950 8951 /* 8952 * VM-Enter should succeed up to the max number of MSRs per list, and 8953 * should not consume junk beyond the last entry. 8954 */ 8955 populate_msr_list(vm_enter_load, byte_capacity, count); 8956 populate_msr_list(vm_exit_load, byte_capacity, exit_count); 8957 populate_msr_list(vm_exit_store, byte_capacity, exit_count); 8958 8959 vmcs_write(ENT_MSR_LD_CNT, count); 8960 vmcs_write(EXI_MSR_LD_CNT, exit_count); 8961 vmcs_write(EXI_MSR_ST_CNT, exit_count); 8962 8963 if (count <= max_allowed) { 8964 enter_guest(); 8965 assert_exit_reason(VMX_VMCALL); 8966 skip_exit_vmcall(); 8967 } else { 8968 u32 exit_reason; 8969 u32 exit_reason_want; 8970 u32 exit_qual; 8971 8972 enter_guest_with_invalid_guest_state(); 8973 8974 exit_reason = vmcs_read(EXI_REASON); 8975 exit_reason_want = VMX_FAIL_MSR | VMX_ENTRY_FAILURE; 8976 report("exit_reason, %u, is %u.", 8977 exit_reason == exit_reason_want, exit_reason, 8978 exit_reason_want); 8979 8980 exit_qual = vmcs_read(EXI_QUALIFICATION); 8981 report("exit_qual, %u, is %u.", exit_qual == max_allowed + 1, 8982 exit_qual, max_allowed + 1); 8983 } 8984 8985 /* Cleanup. */ 8986 vmcs_write(ENT_MSR_LD_CNT, 0); 8987 vmcs_write(EXI_MSR_LD_CNT, 0); 8988 vmcs_write(EXI_MSR_ST_CNT, 0); 8989 for (i = 0; i < cleanup_count; i++) { 8990 enter_guest(); 8991 skip_exit_vmcall(); 8992 } 8993 free_pages_by_order(vm_enter_load, msr_list_page_order); 8994 free_pages_by_order(vm_exit_load, msr_list_page_order); 8995 free_pages_by_order(vm_exit_store, msr_list_page_order); 8996 } 8997 8998 static void atomic_switch_max_msrs_test(void) 8999 { 9000 atomic_switch_msrs_test(max_msr_list_size()); 9001 } 9002 9003 static void atomic_switch_overflow_msrs_test(void) 9004 { 9005 atomic_switch_msrs_test(max_msr_list_size() + 1); 9006 } 9007 9008 #define TEST(name) { #name, .v2 = name } 9009 9010 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 9011 struct vmx_test vmx_tests[] = { 9012 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 9013 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 9014 { "preemption timer", preemption_timer_init, preemption_timer_main, 9015 preemption_timer_exit_handler, NULL, {0} }, 9016 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 9017 test_ctrl_pat_exit_handler, NULL, {0} }, 9018 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 9019 test_ctrl_efer_exit_handler, NULL, {0} }, 9020 { "CR shadowing", NULL, cr_shadowing_main, 9021 cr_shadowing_exit_handler, NULL, {0} }, 9022 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 9023 NULL, {0} }, 9024 { "instruction intercept", insn_intercept_init, insn_intercept_main, 9025 insn_intercept_exit_handler, NULL, {0} }, 9026 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 9027 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 9028 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 9029 { "VPID", vpid_init, vpid_main, vpid_exit_handler, NULL, {0} }, 9030 { "interrupt", interrupt_init, interrupt_main, 9031 interrupt_exit_handler, NULL, {0} }, 9032 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 9033 NULL, {0} }, 9034 { "MSR switch", msr_switch_init, msr_switch_main, 9035 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 9036 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 9037 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 9038 disable_rdtscp_exit_handler, NULL, {0} }, 9039 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 9040 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 9041 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 9042 exit_monitor_from_l2_handler, NULL, {0} }, 9043 { "invalid_msr", invalid_msr_init, invalid_msr_main, 9044 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 9045 /* Basic V2 tests. */ 9046 TEST(v2_null_test), 9047 TEST(v2_multiple_entries_test), 9048 TEST(fixture_test_case1), 9049 TEST(fixture_test_case2), 9050 /* Opcode tests. */ 9051 TEST(invvpid_test_v2), 9052 /* VM-entry tests */ 9053 TEST(vmx_controls_test), 9054 TEST(vmx_host_state_area_test), 9055 TEST(vmx_guest_state_area_test), 9056 TEST(vmentry_movss_shadow_test), 9057 /* APICv tests */ 9058 TEST(vmx_eoi_bitmap_ioapic_scan_test), 9059 TEST(vmx_hlt_with_rvi_test), 9060 TEST(apic_reg_virt_test), 9061 TEST(virt_x2apic_mode_test), 9062 /* APIC pass-through tests */ 9063 TEST(vmx_apic_passthrough_test), 9064 TEST(vmx_apic_passthrough_thread_test), 9065 TEST(vmx_apic_passthrough_tpr_threshold_test), 9066 TEST(vmx_init_signal_test), 9067 /* VMCS Shadowing tests */ 9068 TEST(vmx_vmcs_shadow_test), 9069 /* Regression tests */ 9070 TEST(vmx_cr_load_test), 9071 TEST(vmx_nm_test), 9072 TEST(vmx_db_test), 9073 TEST(vmx_nmi_window_test), 9074 TEST(vmx_intr_window_test), 9075 TEST(vmx_pending_event_test), 9076 TEST(vmx_pending_event_hlt_test), 9077 TEST(vmx_store_tsc_test), 9078 /* EPT access tests. */ 9079 TEST(ept_access_test_not_present), 9080 TEST(ept_access_test_read_only), 9081 TEST(ept_access_test_write_only), 9082 TEST(ept_access_test_read_write), 9083 TEST(ept_access_test_execute_only), 9084 TEST(ept_access_test_read_execute), 9085 TEST(ept_access_test_write_execute), 9086 TEST(ept_access_test_read_write_execute), 9087 TEST(ept_access_test_reserved_bits), 9088 TEST(ept_access_test_ignored_bits), 9089 TEST(ept_access_test_paddr_not_present_ad_disabled), 9090 TEST(ept_access_test_paddr_not_present_ad_enabled), 9091 TEST(ept_access_test_paddr_read_only_ad_disabled), 9092 TEST(ept_access_test_paddr_read_only_ad_enabled), 9093 TEST(ept_access_test_paddr_read_write), 9094 TEST(ept_access_test_paddr_read_write_execute), 9095 TEST(ept_access_test_paddr_read_execute_ad_disabled), 9096 TEST(ept_access_test_paddr_read_execute_ad_enabled), 9097 TEST(ept_access_test_paddr_not_present_page_fault), 9098 TEST(ept_access_test_force_2m_page), 9099 /* Atomic MSR switch tests. */ 9100 TEST(atomic_switch_max_msrs_test), 9101 TEST(atomic_switch_overflow_msrs_test), 9102 { NULL, NULL, NULL, NULL, NULL, {0} }, 9103 }; 9104