19f17508dSLike Xu #include "pmu.h" 2879e7f07SLike Xu 3879e7f07SLike Xu struct pmu_caps pmu; 4879e7f07SLike Xu pmu_init(void)5879e7f07SLike Xuvoid pmu_init(void) 6879e7f07SLike Xu { 7dd602b6fSSean Christopherson pmu.is_intel = is_intel(); 8dd602b6fSSean Christopherson 9b883751aSLike Xu if (pmu.is_intel) { 10b883751aSLike Xu struct cpuid cpuid_10 = cpuid(10); 11dd602b6fSSean Christopherson 12f85e94a2SSean Christopherson pmu.version = cpuid_10.a & 0xff; 13f85e94a2SSean Christopherson 14f85e94a2SSean Christopherson if (pmu.version > 1) { 15f85e94a2SSean Christopherson pmu.nr_fixed_counters = cpuid_10.d & 0x1f; 16f85e94a2SSean Christopherson pmu.fixed_counter_width = (cpuid_10.d >> 5) & 0xff; 17f85e94a2SSean Christopherson } 18f85e94a2SSean Christopherson 19f85e94a2SSean Christopherson pmu.nr_gp_counters = (cpuid_10.a >> 8) & 0xff; 20f85e94a2SSean Christopherson pmu.gp_counter_width = (cpuid_10.a >> 16) & 0xff; 21f85e94a2SSean Christopherson pmu.gp_counter_mask_length = (cpuid_10.a >> 24) & 0xff; 22f85e94a2SSean Christopherson 23f85e94a2SSean Christopherson /* CPUID.0xA.EBX bit is '1' if a counter is NOT available. */ 24f85e94a2SSean Christopherson pmu.gp_counter_available = ~cpuid_10.b; 25f85e94a2SSean Christopherson 26879e7f07SLike Xu if (this_cpu_has(X86_FEATURE_PDCM)) 27879e7f07SLike Xu pmu.perf_cap = rdmsr(MSR_IA32_PERF_CAPABILITIES); 28cda64e80SLike Xu pmu.msr_gp_counter_base = MSR_IA32_PERFCTR0; 29cda64e80SLike Xu pmu.msr_gp_event_select_base = MSR_P6_EVNTSEL0; 3062ba5036SLike Xu 3162ba5036SLike Xu if (this_cpu_has_perf_global_status()) { 328a2866d1SLike Xu pmu.msr_global_status = MSR_CORE_PERF_GLOBAL_STATUS; 338a2866d1SLike Xu pmu.msr_global_ctl = MSR_CORE_PERF_GLOBAL_CTRL; 348a2866d1SLike Xu pmu.msr_global_status_clr = MSR_CORE_PERF_GLOBAL_OVF_CTRL; 3562ba5036SLike Xu } 36b883751aSLike Xu } else { 37b883751aSLike Xu if (this_cpu_has(X86_FEATURE_PERFCTR_CORE)) { 38*952cf19cSLike Xu /* Performance Monitoring Version 2 Supported */ 39*952cf19cSLike Xu if (this_cpu_has(X86_FEATURE_AMD_PMU_V2)) { 40*952cf19cSLike Xu pmu.version = 2; 41*952cf19cSLike Xu pmu.nr_gp_counters = cpuid(0x80000022).b & 0xf; 42*952cf19cSLike Xu } else { 43b883751aSLike Xu pmu.nr_gp_counters = AMD64_NUM_COUNTERS_CORE; 44*952cf19cSLike Xu } 45b883751aSLike Xu pmu.msr_gp_counter_base = MSR_F15H_PERF_CTR0; 46b883751aSLike Xu pmu.msr_gp_event_select_base = MSR_F15H_PERF_CTL0; 47b883751aSLike Xu } else { 48b883751aSLike Xu pmu.nr_gp_counters = AMD64_NUM_COUNTERS; 49b883751aSLike Xu pmu.msr_gp_counter_base = MSR_K7_PERFCTR0; 50b883751aSLike Xu pmu.msr_gp_event_select_base = MSR_K7_EVNTSEL0; 51b883751aSLike Xu } 52b883751aSLike Xu pmu.gp_counter_width = PMC_DEFAULT_WIDTH; 53b883751aSLike Xu pmu.gp_counter_mask_length = pmu.nr_gp_counters; 54b883751aSLike Xu pmu.gp_counter_available = (1u << pmu.nr_gp_counters) - 1; 55*952cf19cSLike Xu 56*952cf19cSLike Xu if (this_cpu_has_perf_global_status()) { 57*952cf19cSLike Xu pmu.msr_global_status = MSR_AMD64_PERF_CNTR_GLOBAL_STATUS; 58*952cf19cSLike Xu pmu.msr_global_ctl = MSR_AMD64_PERF_CNTR_GLOBAL_CTL; 59*952cf19cSLike Xu pmu.msr_global_status_clr = MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR; 60*952cf19cSLike Xu } 61b883751aSLike Xu } 62f33d3946SSean Christopherson 63f33d3946SSean Christopherson pmu_reset_all_counters(); 64879e7f07SLike Xu } 65