1 #include "pmu.h" 2 3 struct pmu_caps pmu; 4 pmu_init(void)5void pmu_init(void) 6 { 7 pmu.is_intel = is_intel(); 8 9 if (pmu.is_intel) { 10 struct cpuid cpuid_10 = cpuid(10); 11 12 pmu.version = cpuid_10.a & 0xff; 13 14 if (pmu.version > 1) { 15 pmu.nr_fixed_counters = cpuid_10.d & 0x1f; 16 pmu.fixed_counter_width = (cpuid_10.d >> 5) & 0xff; 17 } 18 19 pmu.nr_gp_counters = (cpuid_10.a >> 8) & 0xff; 20 pmu.gp_counter_width = (cpuid_10.a >> 16) & 0xff; 21 pmu.gp_counter_mask_length = (cpuid_10.a >> 24) & 0xff; 22 23 /* CPUID.0xA.EBX bit is '1' if a counter is NOT available. */ 24 pmu.gp_counter_available = ~cpuid_10.b; 25 26 if (this_cpu_has(X86_FEATURE_PDCM)) 27 pmu.perf_cap = rdmsr(MSR_IA32_PERF_CAPABILITIES); 28 pmu.msr_gp_counter_base = MSR_IA32_PERFCTR0; 29 pmu.msr_gp_event_select_base = MSR_P6_EVNTSEL0; 30 31 if (this_cpu_has_perf_global_status()) { 32 pmu.msr_global_status = MSR_CORE_PERF_GLOBAL_STATUS; 33 pmu.msr_global_ctl = MSR_CORE_PERF_GLOBAL_CTRL; 34 pmu.msr_global_status_clr = MSR_CORE_PERF_GLOBAL_OVF_CTRL; 35 } 36 } else { 37 if (this_cpu_has(X86_FEATURE_PERFCTR_CORE)) { 38 /* Performance Monitoring Version 2 Supported */ 39 if (this_cpu_has(X86_FEATURE_AMD_PMU_V2)) { 40 pmu.version = 2; 41 pmu.nr_gp_counters = cpuid(0x80000022).b & 0xf; 42 } else { 43 pmu.nr_gp_counters = AMD64_NUM_COUNTERS_CORE; 44 } 45 pmu.msr_gp_counter_base = MSR_F15H_PERF_CTR0; 46 pmu.msr_gp_event_select_base = MSR_F15H_PERF_CTL0; 47 } else { 48 pmu.nr_gp_counters = AMD64_NUM_COUNTERS; 49 pmu.msr_gp_counter_base = MSR_K7_PERFCTR0; 50 pmu.msr_gp_event_select_base = MSR_K7_EVNTSEL0; 51 } 52 pmu.gp_counter_width = PMC_DEFAULT_WIDTH; 53 pmu.gp_counter_mask_length = pmu.nr_gp_counters; 54 pmu.gp_counter_available = (1u << pmu.nr_gp_counters) - 1; 55 56 if (this_cpu_has_perf_global_status()) { 57 pmu.msr_global_status = MSR_AMD64_PERF_CNTR_GLOBAL_STATUS; 58 pmu.msr_global_ctl = MSR_AMD64_PERF_CNTR_GLOBAL_CTL; 59 pmu.msr_global_status_clr = MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR; 60 } 61 } 62 63 pmu_reset_all_counters(); 64 } 65