xref: /kvm-unit-tests/lib/x86/apic.c (revision 9a008986caac35c1120b8552eb610b7793fe613a)
1 #include "libcflat.h"
2 #include "apic.h"
3 #include "msr.h"
4 #include "processor.h"
5 
6 static void *g_apic = (void *)0xfee00000;
7 static void *g_ioapic = (void *)0xfec00000;
8 
9 struct apic_ops {
10     u32 (*reg_read)(unsigned reg);
11     void (*reg_write)(unsigned reg, u32 val);
12     void (*icr_write)(u32 val, u32 dest);
13     u32 (*id)(void);
14 };
15 
16 static void outb(unsigned char data, unsigned short port)
17 {
18     asm volatile ("out %0, %1" : : "a"(data), "d"(port));
19 }
20 
21 void eoi(void)
22 {
23     apic_write(APIC_EOI, 0);
24 }
25 
26 static u32 xapic_read(unsigned reg)
27 {
28     return *(volatile u32 *)(g_apic + reg);
29 }
30 
31 static void xapic_write(unsigned reg, u32 val)
32 {
33     *(volatile u32 *)(g_apic + reg) = val;
34 }
35 
36 static void xapic_icr_write(u32 val, u32 dest)
37 {
38     while (xapic_read(APIC_ICR) & APIC_ICR_BUSY)
39         ;
40     xapic_write(APIC_ICR2, dest << 24);
41     xapic_write(APIC_ICR, val);
42 }
43 
44 static uint32_t xapic_id(void)
45 {
46     return xapic_read(APIC_ID) >> 24;
47 }
48 
49 static const struct apic_ops xapic_ops = {
50     .reg_read = xapic_read,
51     .reg_write = xapic_write,
52     .icr_write = xapic_icr_write,
53     .id = xapic_id,
54 };
55 
56 static const struct apic_ops *apic_ops = &xapic_ops;
57 
58 static u32 x2apic_read(unsigned reg)
59 {
60     unsigned a, d;
61 
62     asm volatile ("rdmsr" : "=a"(a), "=d"(d) : "c"(APIC_BASE_MSR + reg/16));
63     return a | (u64)d << 32;
64 }
65 
66 static void x2apic_write(unsigned reg, u32 val)
67 {
68     asm volatile ("wrmsr" : : "a"(val), "d"(0), "c"(APIC_BASE_MSR + reg/16));
69 }
70 
71 static void x2apic_icr_write(u32 val, u32 dest)
72 {
73     asm volatile ("wrmsr" : : "a"(val), "d"(dest),
74                   "c"(APIC_BASE_MSR + APIC_ICR/16));
75 }
76 
77 static uint32_t x2apic_id(void)
78 {
79     return x2apic_read(APIC_ID);
80 }
81 
82 static const struct apic_ops x2apic_ops = {
83     .reg_read = x2apic_read,
84     .reg_write = x2apic_write,
85     .icr_write = x2apic_icr_write,
86     .id = x2apic_id,
87 };
88 
89 u32 apic_read(unsigned reg)
90 {
91     return apic_ops->reg_read(reg);
92 }
93 
94 void apic_write(unsigned reg, u32 val)
95 {
96     apic_ops->reg_write(reg, val);
97 }
98 
99 bool apic_read_bit(unsigned reg, int n)
100 {
101     reg += (n >> 5) << 4;
102     n &= 31;
103     return (apic_read(reg) & (1 << n)) != 0;
104 }
105 
106 void apic_icr_write(u32 val, u32 dest)
107 {
108     apic_ops->icr_write(val, dest);
109 }
110 
111 uint32_t apic_id(void)
112 {
113     return apic_ops->id();
114 }
115 
116 int enable_x2apic(void)
117 {
118     unsigned a, b, c, d;
119 
120     asm ("cpuid" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "0"(1));
121 
122     if (c & (1 << 21)) {
123         asm ("rdmsr" : "=a"(a), "=d"(d) : "c"(MSR_IA32_APICBASE));
124         a |= 1 << 10;
125         asm ("wrmsr" : : "a"(a), "d"(d), "c"(MSR_IA32_APICBASE));
126         apic_ops = &x2apic_ops;
127         return 1;
128     } else {
129         return 0;
130     }
131 }
132 
133 void reset_apic(void)
134 {
135     u64 disabled = rdmsr(MSR_IA32_APICBASE) & ~(APIC_EN | APIC_EXTD);
136     wrmsr(MSR_IA32_APICBASE, disabled);
137     apic_ops = &xapic_ops;
138     wrmsr(MSR_IA32_APICBASE, disabled | APIC_EN);
139 }
140 
141 u32 ioapic_read_reg(unsigned reg)
142 {
143     *(volatile u32 *)g_ioapic = reg;
144     return *(volatile u32 *)(g_ioapic + 0x10);
145 }
146 
147 void ioapic_write_reg(unsigned reg, u32 value)
148 {
149     *(volatile u32 *)g_ioapic = reg;
150     *(volatile u32 *)(g_ioapic + 0x10) = value;
151 }
152 
153 void ioapic_write_redir(unsigned line, ioapic_redir_entry_t e)
154 {
155     ioapic_write_reg(0x10 + line * 2 + 0, ((u32 *)&e)[0]);
156     ioapic_write_reg(0x10 + line * 2 + 1, ((u32 *)&e)[1]);
157 }
158 
159 ioapic_redir_entry_t ioapic_read_redir(unsigned line)
160 {
161     ioapic_redir_entry_t e;
162 
163     ((u32 *)&e)[0] = ioapic_read_reg(0x10 + line * 2 + 0);
164     ((u32 *)&e)[1] = ioapic_read_reg(0x10 + line * 2 + 1);
165     return e;
166 
167 }
168 
169 void set_mask(unsigned line, int mask)
170 {
171     ioapic_redir_entry_t e = ioapic_read_redir(line);
172 
173     e.mask = mask;
174     ioapic_write_redir(line, e);
175 }
176 
177 void enable_apic(void)
178 {
179     printf("enabling apic\n");
180     xapic_write(0xf0, 0x1ff); /* spurious vector register */
181 }
182 
183 void mask_pic_interrupts(void)
184 {
185     outb(0xff, 0x21);
186     outb(0xff, 0xa1);
187 }
188